User's Manual

21555 Non-Transparent PCI-to-PCI Bridge User Manual 31
Signal Descriptions
3.5 Miscellaneous Signals
Table 10 describes the miscellaneous signals. The letters in the “Type” column are described in Table 1.
s_par64 TS
Secondary PCI interface upper 32 bits parity.
The 21555 does not bus park this pin. This pin is tristated during the assertion of
s_rst_l. Signal s_par64 is driven to a valid value when the 64-bit extension is
disabled (s_req64_l is deasserted during s_rst_l assertion).
Signal s_par64 carries the even parity of the 36 bits of s_ad[63:32] and
s_cbe_l[7:4] for both address and data phases. Signal s_par64 is driven by the
initiator and is valid one clock cycle after the first address phase when a
dual-address command is used and s_req64_l is asserted. Signal s_par64 is also
valid one clock cycle after the second address phase of a dual-address transaction
when s_req64_l is asserted. Signal s_par64 is valid one clock cycle after valid data
is driven (indicated by assertion of s_irdy_l for write data and s_trdy_l for read
data), when both s_req64_l and s_ack64_l are asserted for that data phase. Signal
s_par64 is tristated by the device driving read or write data one clock cycle after the
s_ad lines are tristated.
Devices receiving data sample s_par64 as an input to check for possible parity
errors during 64-bit transactions.
When not driven, s_par64 is pulled up to a valid logic level through external
resistors.
s_req64_l STS
Secondary PCI interface request 64-bit transfer.
Signal s_req64_l is sampled at secondary reset to enable the 64-bit extension on
the secondary bus. When sampled low, the 64-bit extension is enabled. When
designated as a secondary bus central function, the 21555 asserts this signal during
secondary bus reset.
Signal s_req64_l is asserted by the initiator to indicate that the initiator is requesting
64-bit data transfer. Signal s_req64_l has the same timing as s_frame_l. When the
21555 is the secondary bus central function, it will assert s_req64_l low during
secondary bus reset to indicate that a 64-bit bus is supported. When deasserting,
s_req64_l is driven to a deasserted state for one clock cycle and is then sustained
by an external pull-up resistor. The 21555 samples s_req64_l during secondary bus
reset to enable the 64-bit extension signals. When s_req64_l is sampled high
during reset, the secondary 64-bit extension is disabled and assumed not
connected. The 21555 then drives s_ad[63:32], s_cbe_l[7:4], and s_par64 to valid
logic levels.
Table 10. Miscellaneous Signals
Signal Name Type Description
p_vio I
Primary interface I/O voltage. This signal must be tied to either 3.3 V or 5.0 V,
corresponding to the signaling environment of the primary PCI bus as described in
the PCI Local Bus Specification, Revision 2.2. When any device on the primary PCI
bus uses 5-V signaling levels, tie p_vio to 5.0 V. Signal p_vio is tied to 3.3 V only
when all the devices on the primary bus use 3.3-V signaling levels.
s_vio I
Secondary interface I/O voltage. This signal must be tied to either 3.3 V or 5.0 V,
corresponding to the signaling environment of the secondary PCI bus as described
in the PCI Local Bus Specification, Revision 2.2. When any device on the
secondary PCI bus uses 5-V signaling levels, tie s_vio to 5.0 V. Signal s_vio is tied
to 3.3 V only when all the devices on the secondary bus use 3.3-V signaling levels.
Table 9. Secondary PCI Bus Interface 64-Bit Extension Signals (Sheet 2 of 2)
Signal Name Type Description