User's Manual

21555 Non-Transparent PCI-to-PCI Bridge User Manual 51
PCI Bus Transactions
5.2.1 Memory Write Transactions
As a target, the 21555 disconnects memory write transactions at the following address boundaries:
• An aligned 4KB address boundary.
• An aligned page address boundary for upstream transactions falling in the Upstream Memory 2 address range.
• An aligned cache line boundary, when the MW disconnect bit is set in configuration space.
When the posted write queue fills before the master terminates the transaction, the 21555 returns a target disconnect
when the last queue entry is filled. The 21555 does not disconnect on an aligned address boundary, other than those
noted in the previous paragraph, when the write queue is almost full. That is, the memory write queue full
disconnect condition is optimized for burst length and not alignment.
As an initiator, when the 21555 has posted write data to deliver and the conditions listed in Section 5.2.2 for
initiating an MWI transaction are not met, the 21555 uses the memory write command to deliver posted memory
write data. The 21555 terminates the memory write burst when the last piece of data in the transaction is delivered,
or if the transaction is in flow-through mode, when a queue empty condition is detected. In the latter case, the
21555 master terminates the transaction on the target bus, and then initiates a new transaction when a cache line
amount of data is accumulated.
5.2.2 Memory Write and Invalidate Transactions
As a target, the 21555 disconnects MWI transactions at the following address boundaries:
• An aligned 4 KB address boundary.
• An aligned page address boundary, for upstream transactions falling in the Upstream Memory 2 address range.
• An aligned cache line boundary, for MWI transactions when less than a cache line of available space remains
in the posted write queue.
The 21555 disconnects an MWI on a cache line boundary when less than a cache line remains free in the posted
write buffer. This is a different queue full disconnect behavior than that used for the memory write command. In
this case, alignment is preserved at the expense of maximizing burst length.
When a master initiates an MWI transaction, it guarantees that it will supply one full cache line of data, or some
multiple thereof. The 21555 initiates an MWI transaction on the target bus, regardless of whether the bus command
was a memory write or an MWI on the initiator bus, when all of the following conditions are met:
• The MWI Enable bit is set in the Command register corresponding to the target interface.
• The target bus Cache Line Size is set to a valid value (8, 16, or 32 Dwords).
• At least one aligned cache line of data has been posted.
• All byte enables for the posted cache line are turned on.