Computer Hardware User's Manual

ManualsBrandsIntel ManualsComputer Hardware253666-024US

Intel® 64 and IA-32 Architectures

Software Developer’s Manual

Volume 2A:

Instruction Set Reference, A-M

NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual

consists of five volumes: Basic Architecture, Order Number 253665;

Instruction Set Reference A-M, Order Number 253666; Instruction Set

Reference N-Z, Order Number 253667; System Programming Guide,

Part 1, Order Number 253668; System Programming Guide, Part 2,

Order Number 253669. Refer to all five volumes when evaluating your

design needs.

Order Number: 253666-024US

August 2007

Summary of content (760 pages)

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Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of five volumes: Basic Architecture, Order Number 253665; Instruction Set Reference A-M, Order Number 253666; Instruction Set Reference N-Z, Order Number 253667; System Programming Guide, Part 1, Order Number 253668; System Programming Guide, Part 2, Order Number 253669.
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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CONTENTS PAGE CHAPTER 1 ABOUT THIS MANUAL 1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 OVERVIEW OF VOLUME 2A AND 2B: INSTRUCTION SET REFERENCE . . . . . . . . . . . . . . . . . . 1.3 NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE 3.1.1.5 Description Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.1.6 Description Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.1.7 Operation Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.1.8 Intel® C/C++ Compiler Intrinsics Equivalents Section . . . . . . . . . . . .
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CONTENTS PAGE CLFLUSH—Flush Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108 CLI — Clear Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110 CLTS—Clear Task-Switched Flag in CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113 CMC—Complement Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE Double-Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-231 CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-234 CVTTPD2PI—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE FLD—Load Floating Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant . . . . . . . . . . . FLDCW—Load x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLDENV—Load x87 FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FMUL/FMULP/FIMUL—Multiply . . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE JMP—Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-508 LAHF—Load Status Flags into AH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-518 LAR—Load Access Rights Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-520 LDDQU—Load Unaligned Integer 128 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE MOVNTDQ—Store Double Quadword Using Non-Temporal Hint . . . . . . . . . . . . . . . . . MOVNTI—Store Doubleword Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE PAVGB/PAVGW—Average Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal. . . . . . . . . . . . . . . . 4-64 PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than . 468 PEXTRW—Extract Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73 PHADDW/PHADDD — Packed Horizontal Add . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE PUSH—Push Word, Doubleword or Quadword Onto the Stack . . . . . . . . . . . . . . . . . . . PUSHA/PUSHAD—Push All General-Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . PUSHF/PUSHFD—Push EFLAGS Register onto the Stack . . . . . . . . . . . . . . . . . . . . . . . . PXOR—Logical Exclusive OR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RCL/RCR/ROL/ROR-—Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE SYSCALL—Fast System Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-367 SYSENTER—Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-369 SYSEXIT—Fast Return from Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-373 SYSRET—Return From Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE CHAPTER 6 SAFER MODE EXTENSIONS REFERENCE 6.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 6.2 SMX FUNCTIONALITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 6.2.1 Detecting and Enabling SMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE A.5.2.3 A.5.2.4 A.5.2.5 A.5.2.6 A.5.2.7 A.5.2.8 Escape Opcodes with DA as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25 Escape Opcodes with DB as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26 Escape Opcodes with DC as First Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27 Escape Opcodes with DD as First Byte . . . . . . . . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE FIGURES Figure 1-1. Figure 1-2. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14.
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CONTENTS PAGE TABLES Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 3-1. Table 3-2. Table 3-3. Table 3-5. Table 3-4. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 3-17. Table 3-18. Table 3-19. Table 3-20. Table 3-21. Table 3-22. Table 3-23. Table 3-24. Table 3-25. Table 3-26. Table 3-27. Table 3-28. Table 3-29. Table 3-30. Table 3-31. Table 3-32. Table 3-33. Table 3-34. Table 3-35.
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CONTENTS PAGE Table 3-38. Table 3-39. Table 3-40. Table 3-41. Table 3-42. Table 3-43. Table 3-44. Table 3-45. Table 3-46. Table 3-47. Table 3-48. Table 3-49. Table 3-50. Table 3-51. Table 3-52. Table 3-53. Table 3-54. Table 3-55. Table 3-56. Table 3-57. Table 3-58. Table 3-59. Table 3-60. Table 3-61. Table 3-62. Table 3-63. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 6-5. Table 6-6. Table 6-7. Table 6-8. Table 6-9. Table 6-10.
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CONTENTS PAGE Table A-1. Table A-2. Table A-3. Table A-4. Table A-5. Table A-6. Table A-7. Table A-8. Table A-9. Table A-10. Table A-11. Table A-12. Table A-13. Table A-14. Table A-15. Table A-16. Table A-17. Table A-18. Table A-19. Table A-20. Table A-21. Table A-22. Table B-1. Table B-2. Table B-4. Table B-3. Table B-5. Table B-6. Table B-7. Table B-8. Table B-9. Table B-11. Table B-10. Table B-12. Table B-13. Table B-14. Table B-15. Table B-16. Table B-17. Table B-18. Table B-19. Table B-20. Table B-21.
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CONTENTS PAGE Table B-23. Table B-24. Table B-25. Table B-26. Table B-27. Table B-28. Table B-29. Table B-30. Table B-31. Table B-32. Table B-33. Table B-34. Table B-35. Table B-36. Table C-1. Table C-2. Format and Encoding of SSE Cacheability & Memory Ordering Instructions. . . . . .B-67 Encoding of Granularity of Data Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-68 Formats and Encodings of SSE2 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . .
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CONTENTS PAGE xx Vol.
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CHAPTER 1 ABOUT THIS MANUAL The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B: Instruction Set Reference (order numbers 253666 and 253667) are part of a set that describes the architecture and programming environment of all Intel 64 and IA-32 architecture processors. Other volumes in this set are: • The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (Order Number 253665).
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ABOUT THIS MANUAL • • • • • • • • • Intel® Core™2 Duo processor Intel® Core™2 Quad processor Intel® Xeon® processor 3000, 3200 series Intel® Xeon® processor 5000 series Intel® Xeon® processor 5100, 5300 series Intel® Core™2 Extreme processor Intel® Core™2 Extreme Quad-core processor Intel® Xeon® processor 7100, 7300 series Intel® Pentium® Dual-Core processor P6 family processors are IA-32 processors based on the P6 family microarchitecture.
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ABOUT THIS MANUAL Chapter 1 — About This Manual. Gives an overview of all five volumes of the Intel® 64 and IA-32 Architectures Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel® manuals and documentation of interest to programmers and hardware designers. Chapter 2 — Instruction Format.
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ABOUT THIS MANUAL 1.3.1 Bit and Byte Order In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to two raised to the power of the bit position. IA-32 processors are “little endian” machines; this means the bytes of a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions. 1-4 Vol.
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ABOUT THIS MANUAL Highest Address 31 24 23 Byte 3 Data Structure 8 7 16 15 Byte 2 Byte 1 0 Byte 0 Bit offset 28 24 20 16 12 8 4 0 Lowest Address Byte Offset Figure 1-1. Bit and Byte Order 1.3.2 Reserved Bits and Software Compatibility In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as reserved, it is essential for compatibility with future processors that software treat these bits as having a future, though unknown, effect.
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ABOUT THIS MANUAL 1.3.3 Instruction Operands When instructions are represented symbolically, a subset of the IA-32 assembly language is used. In this subset, an instruction has the following format: label: mnemonic argument1, argument2, argument3 where: • • A label is an identifier which is followed by a colon. • The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands, depending on the opcode.
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ABOUT THIS MANUAL For example, a program can keep its code (instructions) and stack in separate segments. Code addresses would always refer to the code space, and stack addresses would always refer to the stack space.
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ABOUT THIS MANUAL literature types: applications notes, data sheets, manuals, papers, and specification updates. See also: • • • The data sheet for a particular Intel 64 or IA-32 processor • Intel® Fortran Compiler documentation and online help http://www.intel.com/cd/software/products/asmo-na/eng/index.htm • Intel® VTune™ Performance Analyzer documentation and online help http://www.intel.com/cd/software/products/asmo-na/eng/index.
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ABOUT THIS MANUAL • Intel 64 and IA-32 processor manuals (printed or PDF downloads): http://developer.intel.com/products/processor/manuals/index.htm • Intel® Multi-Core Technology: http://developer.intel.com/multi-core/index.htm • Hyper-Threading Technology (HT Technology): http://developer.intel.com/technology/hyperthread/ 1-10 Vol.
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CHAPTER 2 INSTRUCTION FORMAT This chapter describes the instruction format for all Intel 64 and IA-32 processors. The instruction format for protected mode, real-address mode and virtual-8086 mode is described in Section 2.1. Increments provided for IA-32e mode and its submodes are described in Section 2.2. 2.1 INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE The Intel 64 and IA-32 architectures instruction encodings are subsets of the format shown in Figure 2-1.
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INSTRUCTION FORMAT • • F2H—REPNE/REPNZ (used only with string instructions; when used with the escape opcode 0FH, this prefix is treated as a mandatory prefix for some SIMD instructions) • F3H—REP or REPE/REPZ (used only with string instructions; when used with the escape opcode 0FH, this prefix is treated as an mandatory prefix for some SIMD instructions) Group 2 — Segment override prefixes: • • 2EH—CS segment override (use with any branch instruction is reserved) 36H—SS segment override prefix (us
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INSTRUCTION FORMAT opcodes with Intel 64 or IA-32 instructions is reserved; such use may cause unpredictable behavior. The operand-size override prefix allows a program to switch between 16- and 32-bit operand sizes. Either size can be the default; use of the prefix selects the non-default size. Use of 66H followed by 0FH is treated as a mandatory prefix by some SSE/SSE2/SSE3 instructions.
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INSTRUCTION FORMAT 2.1.3 ModR/M and SIB Bytes Many instructions that refer to an operand in memory have an addressing-form specifier byte (called the ModR/M byte) following the primary opcode. The ModR/M byte contains three fields of information: • The mod field combines with the r/m field to form 32 possible values: eight registers and 24 addressing modes. • The reg/opcode field specifies either a register number or three more bits of opcode information.
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INSTRUCTION FORMAT location; the last eight (Mod = 11B) provide ways of specifying general-purpose, MMX technology and XMM registers. The Mod and R/M columns in Table 2-1 and Table 2-2 give the binary encodings of the Mod and R/M fields required to obtain the effective address listed in the first column. For example: see the row indicated by Mod = 11B, R/M = 000B. The row identifies the general-purpose registers EAX, AX or AL; MMX technology register MM0; or XMM register XMM0.
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INSTRUCTION FORMAT Table 2-1.
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INSTRUCTION FORMAT Table 2-2.
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INSTRUCTION FORMAT of the table indicate the register used as the index (SIB byte bits 3, 4 and 5) and the scaling factor (determined by SIB byte bits 6 and 7). Table 2-3.
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INSTRUCTION FORMAT 2.2 IA-32E MODE IA-32e mode has two sub-modes. These are: • Compatibility Mode. Enables a 64-bit operating system to run most legacy protected mode software unmodified. • 64-Bit Mode. Enables a 64-bit operating system to run applications written to access 64-bit address space. 2.2.1 REX Prefixes REX prefixes are instruction-prefix bytes used in 64-bit mode. They do the following: • • • Specify GPRs and SSE registers. Specify 64-bit operand size.
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INSTRUCTION FORMAT 2.2.1.1 Encoding Intel 64 and IA-32 instruction formats specify up to three registers by using 3-bit fields in the encoding, depending on the format: • • ModR/M: the reg and r/m fields of the ModR/M byte • Instructions without ModR/M: the reg field of the opcode ModR/M with SIB: the reg field of the ModR/M byte, the base and index fields of the SIB (scale, index, base) byte In 64-bit mode, these formats do not change.
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INSTRUCTION FORMAT Table 2-4. REX Prefix Fields [BITS: 0100WRXB] Field Name Bit Position Definition - 7:4 0100 W 3 0 = Operand size determined by CS.D 1 = 64 Bit Operand Size R 2 Extension of the ModR/M reg field X 1 Extension of the SIB index field B 0 Extension of the ModR/M r/m field, SIB base field, or Opcode reg field 0RG50 %\WH 5(; 35(),; 2SFRGH PRG :5 % UHJ UUU U P EEE 5UUU %EEE 20 ;ILJ Figure 2-4. Memory Addressing Without an SIB Byte; REX.
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INSTRUCTION FORMAT 0RG50 %\WH 5(; 35(),; 2SFRGH :5;% PRG UHJ UUU 6,% %\WH U P LQGH[ [[[ VFDOH VV 5UUU ;[[[ EDVH EEE %EEE 20 ;ILJ Figure 2-6. Memory Addressing With a SIB Byte 5(; 35(),; : % 2SFRGH UHJ EEE %EEE 20 ;ILJ Figure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.
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INSTRUCTION FORMAT Table 2-5. Special Cases of REX Encodings ModR/M or SIB Sub-field Encodings ModR/M Byte mod != 11 Compatibility Mode Operation Compatibility Mode Implications Additional Implications SIB byte present. SIB byte required for ESP-based addressing. r/m == b*100(ESP) ModR/M Byte mod == 0 r/m == b*101(EBP) REX prefix adds a fourth bit (b) which is not decoded (don't care). SIB byte also required for R12-based addressing. Base register not used.
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INSTRUCTION FORMAT size of the memory offset follows the address-size default (64 bits in 64-bit mode). See Table 2-6. Table 2-6. Direct Memory Offset Form of MOV Opcode Instruction A0 MOV AL, moffset A1 MOV EAX, moffset A2 MOV moffset, AL A3 MOV moffset, EAX 2.2.1.5 Immediates In 64-bit mode, the typical size of immediate operands remains 32 bits. When the operand size is 64 bits, the processor sign-extends all immediates to 64 bits prior to their use.
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INSTRUCTION FORMAT Table 2-7. RIP-Relative Addressing ModR/M and SIB Sub-field Encodings Compatibility Mode Operation 64-bit Mode Operation Additional Implications in 64-bit mode ModR/M Byte mod == 00 Disp32 RIP + Disp32 Must use SIB form with normal (zero-based) displacement addressing SIB Byte base == 101 (none) if mod = 00, Disp32 Same as legacy None r/m == 101 (none) index == 100 (none) scale = 0, 1, 2, 4 The ModR/M encoding for RIP-relative addressing does not depend on using prefix.
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INSTRUCTION FORMAT 2-16 Vol.
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CHAPTER 3 INSTRUCTION SET REFERENCE, A-M This chapter describes the instruction set for the Intel 64 and IA-32 architectures (A-M) in IA-32e, protected, Virtual-8086, and real modes of operation. The set includes general-purpose, x87 FPU, MMX, SSE/SSE2/SSE3/SSSE3, and system instructions. See also Chapter 4, “Instruction Set Reference, N-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B. For each instruction, each operand combination is described.
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INSTRUCTION SET REFERENCE, A-M 3.1.1.1 Opcode Column in the Instruction Summary Table The “Opcode” column in the table above shows the object code produced for each form of the instruction. When possible, codes are given as hexadecimal bytes in the same order in which they appear in memory. Definitions of entries other than hexadecimal bytes are as follows: • REX.W — Indicates the use of a REX prefix that affects operand size or instruction semantics.
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INSTRUCTION SET REFERENCE, A-M Table 3-1. Register Codes Associated With +rb, +rw, +rd, +ro (Contd.) REX.B Reg Field quadword register (64-Bit Mode only) Register Reg Field REX.B Register dword register Reg Field REX.B word register Register Reg Field REX.B Register byte register BL None 3 BX None 3 EBX None 3 RBX None 3 AH Not encod able (N.E.) 4 SP None 4 ESP None 4 N/A N/A N/A CH N.E. 5 BP None 5 EBP None 5 N/A N/A N/A DH N.E.
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INSTRUCTION SET REFERENCE, A-M • ptr16:16, ptr16:32 and ptr16:64 — A far pointer, typically to a code segment different from that of the instruction. The notation 16:16 indicates that the value of the pointer has two parts. The value to the left of the colon is a 16-bit selector or value destined for the code segment register. The value to the right corresponds to the offset within the destination segment.
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INSTRUCTION SET REFERENCE, A-M • r/m32 — A doubleword general-purpose register or memory operand used for instructions whose operand-size attribute is 32 bits. The doubleword generalpurpose registers are: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. The contents of memory are found at the address provided by the effective address computation. Doubleword registers R8D - R15D are available when using REX.R in 64-bit mode.
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INSTRUCTION SET REFERENCE, A-M • Sreg — A segment register. The segment register bit assignments are ES = 0, CS = 1, SS = 2, DS = 3, FS = 4, and GS = 5. • m32fp, m64fp, m80fp — A single-precision, double-precision, and double extended-precision (respectively) floating-point operand in memory. These symbols designate floating-point values that are used as operands for x87 FPU floating-point instructions.
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INSTRUCTION SET REFERENCE, A-M • N.P. — Indicates the REX prefix does not affect the legacy instruction in 64-bit mode. • • N.I. — Indicates the opcode is treated as a new instruction in 64-bit mode. N.S. — Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior. 3.1.1.
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INSTRUCTION SET REFERENCE, A-M address contained in register SI relative to the SI register’s default segment (DS) or the overridden segment. • Parentheses around the “E” in a general-purpose register name, such as (E)SI, indicates that the offset is read from the SI register if the address-size attribute is 16, from the ESI register if the address-size attribute is 32.
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INSTRUCTION SET REFERENCE, A-M Attribute for Stack” in Chapter 6, “Procedure Calls, Interrupts, and Exceptions,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. • • SRC — Represents the source operand. DEST — Represents the destination operand. The following functions are used in the algorithmic descriptions: • ZeroExtend(value) — Returns a value zero-extended to the operand-size attribute of the instruction.
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INSTRUCTION SET REFERENCE, A-M zero (00H); if it is greater than 65535, it is represented by the saturated value 65535 (FFFFH). • LowOrderWord(DEST * SRC) — Multiplies a word operand by a word operand and stores the least significant word of the doubleword result in the destination operand. • HighOrderWord(DEST * SRC) — Multiplies a word operand by a word operand and stores the most significant word of the doubleword result in the destination operand. • Push(value) — Pushes a value onto the stack.
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INSTRUCTION SET REFERENCE, A-M Table 3-2. Range of Bit Positions Specified by Bit Offset Operands Operand Size Immediate BitOffset Register BitOffset 16 0 to 15 −215 to 215 −1 32 0 to 31 −231 to 231 −1 64 0 to 63 −263 to 263 −1 The addressed bit is numbered (Offset MOD 8) within the byte at address (BitBase + (BitOffset DIV 8)) where DIV is signed division with rounding towards negative infinity and MOD returns a positive number (see Figure 3-2).
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INSTRUCTION SET REFERENCE, A-M See Appendix C, “InteL® C/C++ Compiler Intrinsics and Functional Equivalents,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for more information on using intrinsics. Intrinsics API The benefit of coding with MMX technology intrinsics and the SSE/SSE2/SSE3 intrinsics is that you can use the syntax of C function calls and C variables instead of hardware registers. This frees you from managing registers and programming assembly.
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INSTRUCTION SET REFERENCE, A-M • The __m128i data type can hold sixteen byte, eight word, or four doubleword, or two quadword integer values. The compiler aligns __m128, __m128d, and __m128i local and global data to 16-byte boundaries on the stack. To align integer, float, or double arrays, use the declspec statement as described in Intel C/C++ compiler documentation. See http://www.intel.com/support/performancetools/.
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INSTRUCTION SET REFERENCE, A-M Some intrinsics are “composites” because they require more than one instruction to implement them. You should be familiar with the hardware features provided by the SSE, SSE2, SSE3, and MMX technology when writing programs with the intrinsics. Keep the following important issues in mind: • Certain intrinsics, such as _mm_loadr_ps and _mm_cmpgt_ss, are not directly supported by the instruction set.
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INSTRUCTION SET REFERENCE, A-M letter mnemonic with the corresponding interrupt vector number and exception name. See Chapter 5, “Interrupt and Exception Handling,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for a detailed description of the exceptions. Application programmers should consult the documentation provided with their operating systems to determine the actions taken when exceptions occur. Table 3-3. Intel 64 and IA-32 General Exceptions Vector No.
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INSTRUCTION SET REFERENCE, A-M Table 3-3. Intel 64 and IA-32 General Exceptions (Contd.) Vector No. Protected Mode1 Real Address Mode Virtual 8086 Mode Name Source 18 #MC—Machine Check Model dependent machine check errors. Yes Yes Yes 19 #XM—SIMD Floating-Point Numeric Error SSE/SSE2/SSE3 floating-point instructions. Yes Yes Yes NOTES: 1. Apply to protected mode, compatibility mode, and 64-bit mode. 2. In the real-address mode, vector 13 is the segment overrun exception. 3.1.1.
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INSTRUCTION SET REFERENCE, A-M Table 3-4.
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INSTRUCTION SET REFERENCE, A-M 3.2 INSTRUCTIONS (A-M) The remainder of this chapter provides descriptions of Intel 64 and IA-32 instructions (A-M). See also: Chapter 4, “Instruction Set Reference, N-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B. 3-18 Vol.
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INSTRUCTION SET REFERENCE, A-M AAA—ASCII Adjust After Addition Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 37 AAA Invalid Valid ASCII adjust AL after addition. Description Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied source and destination operand for this instruction.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as protected mode. Virtual-8086 Mode Exceptions Same exceptions as protected mode. Compatibility Mode Exceptions Same exceptions as protected mode. 64-Bit Mode Exceptions #UD 3-20 Vol. 2A If in 64-bit mode.
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INSTRUCTION SET REFERENCE, A-M AAD—ASCII Adjust AX Before Division Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D5 0A AAD Invalid Valid ASCII adjust AX before division. D5 ib (No mnemonic) Invalid Valid Adjust AX before division to number base imm8.
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INSTRUCTION SET REFERENCE, A-M Flags Affected The SF, ZF, and PF flags are set according to the resulting binary value in the AL register; the OF, AF, and CF flags are undefined. Protected Mode Exceptions #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as protected mode. Virtual-8086 Mode Exceptions Same exceptions as protected mode. Compatibility Mode Exceptions Same exceptions as protected mode. 64-Bit Mode Exceptions #UD 3-22 Vol. 2A If in 64-bit mode.
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INSTRUCTION SET REFERENCE, A-M AAM—ASCII Adjust AX After Multiply Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D4 0A AAM Invalid Valid ASCII adjust AX after multiply. D4 ib (No mnemonic) Invalid Valid Adjust AX after multiply to number base imm8. Description Adjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD values. The AX register is the implied source and destination operand for this instruction.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #DE If an immediate value of 0 is used. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as protected mode. Virtual-8086 Mode Exceptions Same exceptions as protected mode. Compatibility Mode Exceptions Same exceptions as protected mode. 64-Bit Mode Exceptions #UD 3-24 Vol. 2A If in 64-bit mode.
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INSTRUCTION SET REFERENCE, A-M AAS—ASCII Adjust AL After Subtraction Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 3F AAS Invalid Valid ASCII adjust AL after subtraction. Description Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register is the implied source and destination operand for this instruction.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as protected mode. Virtual-8086 Mode Exceptions Same exceptions as protected mode. Compatibility Mode Exceptions Same exceptions as protected mode. 64-Bit Mode Exceptions #UD 3-26 Vol. 2A If in 64-bit mode.
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INSTRUCTION SET REFERENCE, A-M ADC—Add with Carry Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 14 ib ADC AL, imm8 Valid Valid Add with carry imm8 to AL. 15 iw ADC AX, imm16 Valid Valid Add with carry imm16 to AX. 15 id ADC EAX, imm32 Valid Valid Add with carry imm32 to EAX. REX.W + 15 id ADC RAX, imm32 Valid N.E. Add with carry imm32 sign extended to 64-bits to RAX. 80 /2 ib ADC r/m8, imm8 Valid Valid Add with carry imm8 to r/m8.
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INSTRUCTION SET REFERENCE, A-M Opcode Instruction 13 /r REX.W + 13 /r 64-Bit Mode Compat/ Leg Mode Description ADC r32, r/m32 Valid Valid Add with CF r/m32 to r32. ADC r64, r/m64 Valid N.E. Add with CF r/m64 to r64. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
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INSTRUCTION SET REFERENCE, A-M If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory operand.
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INSTRUCTION SET REFERENCE, A-M ADD—Add Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 04 ib ADD AL, imm8 Valid Valid Add imm8 to AL. 05 iw ADD AX, imm16 Valid Valid Add imm16 to AX. 05 id ADD EAX, imm32 Valid Valid Add imm32 to EAX. REX.W + 05 id ADD RAX, imm32 Valid N.E. Add imm32 signextended to 64-bits to RAX. 80 /0 ib ADD r/m8, imm8 Valid Valid Add imm8 to r/m8. REX + 80 /0 ib * ADD r/m8 , imm8 Valid N.E. Add sign-extended imm8 to r/m64.
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INSTRUCTION SET REFERENCE, A-M Description Adds the destination operand (first operand) and the source operand (second operand) and then stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is signextended to the length of the destination operand format.
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INSTRUCTION SET REFERENCE, A-M #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used but the destination is not a memory operand. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M ADDPD—Add Packed Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 58 /r ADDPD xmm1, xmm2/m128 Valid Valid Add packed double-precision floatingpoint values from xmm2/m128 to xmm1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CRO.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. ADDPD—Add Packed Double-Precision Floating-Point Values Vol.
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INSTRUCTION SET REFERENCE, A-M ADDPS—Add Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 58 /r ADDPS xmm1, xmm2/m128 Valid Valid Add packed single-precision floating-point values from xmm2/m128 to xmm1.
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INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.
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INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. 3-38 Vol.
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INSTRUCTION SET REFERENCE, A-M ADDSD—Add Scalar Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 58 /r ADDSD xmm1, xmm2/m64 Valid Valid Add the low doubleprecision floating-point value from xmm2/m64 to xmm1. Description Adds the low double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the double-precision floating-point result in the destination operand.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. ADDSD—Add Scalar Double-Precision Floating-Point Values Vol.
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INSTRUCTION SET REFERENCE, A-M ADDSS—Add Scalar Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 58 /r ADDSS xmm1, xmm2/m32 Valid Valid Add the low singleprecision floating-point value from xmm2/m32 to xmm1. Description Adds the low single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the single-precision floating-point result in the destination operand.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CRO.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) 3-44 Vol. 2A If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, A-M ADDSUBPD—Packed Double-FP Add/Subtract Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F D0 /r ADDSUBPD xmm1, xmm2/m128 Valid Valid Add/subtract double-precision floating-point values from xmm2/m128 to xmm1. Description Adds the double-precision floating-point values in the high quadword of the source and destination operands and stores the result in the high quadword of the destination operand.
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INSTRUCTION SET REFERENCE, A-M Operation xmm1[63:0] = xmm1[63:0] −xmm2/m128[63:0]; xmm1[127:64] = xmm1[127:64] +xmm2/m128[127:64]; Intel C/C++Compiler Intrinsic Equivalent ADDSUBPD __m128d _mm_addsub_pd(__m128d a, __m128d b) Exceptions When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal.
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INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. 3-48 Vol.
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INSTRUCTION SET REFERENCE, A-M ADDSUBPS—Packed Single-FP Add/Subtract Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F D0 /r ADDSUBPS xmm1, xmm2/m128 Valid Valid Add/subtract singleprecision floatingpoint values from xmm2/m128 to xmm1.
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INSTRUCTION SET REFERENCE, A-M Operation xmm1[31:0] = xmm1[31:0] −xmm2/m128[31:0]; xmm1[63:32] = xmm1[63:32] + xmm2/m128[63:32]; xmm1[95:64] = xmm1[95:64] −xmm2/m128[95:64]; xmm1[127:96] = xmm1[127:96] + xmm2/m128[127:96]; Intel C/C++Compiler Intrinsic Equivalent ADDSUBPS __m128 _mm_addsub_ps(__m128 a, __m128 b) Exceptions When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
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INSTRUCTION SET REFERENCE, A-M #XM #UD For an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1. If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. 3-52 Vol.
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INSTRUCTION SET REFERENCE, A-M AND—Logical AND Opcode Instruction 64-Bit Mode Comp/Leg Mode Description 24 ib AND AL, imm8 Valid Valid AL AND imm8. 25 iw AND AX, imm16 Valid Valid AX AND imm16. 25 id AND EAX, imm32 Valid Valid EAX AND imm32. REX.W + 25 id AND RAX, imm32 Valid N.E. RAX AND imm32 signextended to 64-bits. 80 /4 ib AND r/m8, imm8 Valid Valid r/m8 AND imm8. Valid N.E. r/m64 AND imm8 (signextended).
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INSTRUCTION SET REFERENCE, A-M Description Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.
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INSTRUCTION SET REFERENCE, A-M #UD If the LOCK prefix is used but the destination is not a memory operand. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made.
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INSTRUCTION SET REFERENCE, A-M ANDPD—Bitwise Logical AND of Packed Double-Precision FloatingPoint Values Opcode Instruction 66 0F 54 /r ANDPD xmm1, xmm2/m128 64-Bit Mode Compat/ Leg Mode Description Valid Valid Bitwise logical AND of xmm2/m128 and xmm1. Description Performs a bitwise logical AND of the two packed double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault.
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INSTRUCTION SET REFERENCE, A-M ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode 0F 54 /r ANDPS xmm1, xmm2/m128 Valid Compat/ Leg Mode Description Valid Bitwise logical AND of xmm2/m128 and xmm1. Description Performs a bitwise logical AND of the four packed single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault.
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INSTRUCTION SET REFERENCE, A-M ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 55 /r ANDNPD xmm1, xmm2/m128 Valid Valid Bitwise logical AND NOT of xmm2/m128 and xmm1.
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INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode 0F 55 /r ANDNPS xmm1, xmm2/m128 Valid Compat/ Leg Mode Description Valid Bitwise logical AND NOT of xmm2/m128 and xmm1.
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INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault.
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INSTRUCTION SET REFERENCE, A-M ARPL—Adjust RPL Field of Segment Selector Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 63 /r ARPL r/m16, r16 N. E. Valid Adjust RPL of r/m16 to not less than RPL of r16. Description Compares the RPL fields of two segment selectors. The first operand (the destination operand) contains one segment selector and the second operand (source operand) contains the other. (The RPL field is located in bits 0 and 1 of each operand.
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INSTRUCTION SET REFERENCE, A-M FI; ELSE ZF ←0; FI; Flags Affected The ZF flag is set to 1 if the RPL field of the destination operand is less than that of the source operand; otherwise, it is set to 0. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.
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INSTRUCTION SET REFERENCE, A-M BOUND—Check Array Index Against Bounds Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 62 /r BOUND r16, m16&16 Invalid Valid Check if r16 (array index) is within bounds specified by m16&16. 62 /r BOUND r32, m32&32 Invalid Valid Check if r32 (array index) is within bounds specified by m16&16. Description BOUND determines if the first operand (array index) is within the bounds of an array specified the second operand (bounds operand).
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INSTRUCTION SET REFERENCE, A-M Flags Affected None. Protected Mode Exceptions #BR If the bounds test fails. #UD If second operand is not a memory location. If the LOCK prefix is used. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #UD 3-68 Vol. 2A If in 64-bit mode.
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INSTRUCTION SET REFERENCE, A-M BSF—Bit Scan Forward Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F BC /r BSF r16, r/m16 Valid Valid Bit scan forward on r/m16. 0F BC /r BSF r32, r/m32 Valid Valid Bit scan forward on r/m32. REX.W + 0F BC BSF r64, r/m64 Valid N.E. Bit scan forward on r/m64. Description Searches the source operand (second operand) for the least significant set bit (1 bit).
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M BSR—Bit Scan Reverse Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F BD /r BSR r16, r/m16 Valid Valid Bit scan reverse on r/m16. 0F BD /r BSR r32, r/m32 Valid Valid Bit scan reverse on r/m32. REX.W + 0F BD BSR r64, r/m64 Valid N.E. Bit scan reverse on r/m64. Description Searches the source operand (second operand) for the most significant set bit (1 bit).
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M BSWAP—Byte Swap Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F C8+rd BSWAP r32 Valid* Valid Reverses the byte order of a 32bit register. REX.W + 0F C8+rd BSWAP r64 Valid N.E. Reverses the byte order of a 64bit register. NOTES: * See IA-32 Architecture Compatibility section below. Description Reverses the byte order of a 32-bit or 64-bit (destination) register.
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INSTRUCTION SET REFERENCE, A-M FI; DEST[15:8] ←TEMP[23:16]; DEST[23:16] ←TEMP[15:8]; DEST[31:24] ←TEMP[7:0]; Flags Affected None. Exceptions (All Operating Modes) #UD 3-74 Vol. 2A If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M BT—Bit Test Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F A3 BT r/m16, r16 Valid Valid Store selected bit in CF flag. 0F A3 BT r/m32, r32 Valid Valid Store selected bit in CF flag. REX.W + 0F A3 BT r/m64, r64 Valid N.E. Store selected bit in CF flag. 0F BA /4 ib BT r/m16, imm8 Valid Valid Store selected bit in CF flag. 0F BA /4 ib BT r/m32, imm8 Valid Valid Store selected bit in CF flag. REX.
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INSTRUCTION SET REFERENCE, A-M Or, it may access 2 bytes starting from the memory address for a 16-bit operand, using this relationship: Effective Address +(2 ∗ (BitOffset DIV 16)) It may do so even when only a single byte needs to be accessed to reach the given bit. When using this bit addressing mechanism, software should avoid referencing areas of memory close to address space holes. In particular, it should avoid references to memory-mapped I/O registers.
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INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M BTC—Bit Test and Complement Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F BB BTC r/m16, r16 Valid Valid Store selected bit in CF flag and complement. 0F BB BTC r/m32, r32 Valid Valid Store selected bit in CF flag and complement. REX.W + 0F BB BTC r/m64, r64 Valid N.E. Store selected bit in CF flag and complement. 0F BA /7 ib BTC r/m16, imm8 Valid Valid Store selected bit in CF flag and complement.
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INSTRUCTION SET REFERENCE, A-M prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation CF ←Bit(BitBase, BitOffset); Bit(BitBase, BitOffset) ←NOT Bit(BitBase, BitOffset); Flags Affected The CF flag contains the value of the selected bit before it is complemented. The OF, SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #GP(0) If the destination operand points to a non-writable segment.
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INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used but the destination is not a memory operand. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M BTR—Bit Test and Reset Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F B3 BTR r/m16, r16 Valid Valid Store selected bit in CF flag and clear. 0F B3 BTR r/m32, r32 Valid Valid Store selected bit in CF flag and clear. REX.W + 0F B3 BTR r/m64, r64 Valid N.E. Store selected bit in CF flag and clear. 0F BA /6 ib BTR r/m16, imm8 Valid Valid Store selected bit in CF flag and clear.
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INSTRUCTION SET REFERENCE, A-M prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation CF ←Bit(BitBase, BitOffset); Bit(BitBase, BitOffset) ←0; Flags Affected The CF flag contains the value of the selected bit before it is cleared. The OF, SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #GP(0) If the destination operand points to a non-writable segment.
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INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used but the destination is not a memory operand. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M BTS—Bit Test and Set Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F AB BTS r/m16, r16 Valid Valid Store selected bit in CF flag and set. 0F AB BTS r/m32, r32 Valid Valid Store selected bit in CF flag and set. REX.W + 0F AB BTS r/m64, r64 Valid N.E. Store selected bit in CF flag and set. 0F BA /5 ib BTS r/m16, imm8 Valid Valid Store selected bit in CF flag and set.
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INSTRUCTION SET REFERENCE, A-M prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation CF ←Bit(BitBase, BitOffset); Bit(BitBase, BitOffset) ←1; Flags Affected The CF flag contains the value of the selected bit before it is set. The OF, SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #GP(0) If the destination operand points to a non-writable segment.
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INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used but the destination is not a memory operand. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M CALL—Call Procedure Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description E8 cw CALL rel16 N.S. Valid Call near, relative, displacement relative to next instruction. E8 cd CALL rel32 Valid Valid Call near, relative, displacement relative to next instruction. 32-bit displacement sign extended to 64-bits in 64-bit mode. FF /2 CALL r/m16 N.E. Valid Call near, absolute indirect, address given in r/m16. FF /2 CALL r/m32 N.E.
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INSTRUCTION SET REFERENCE, A-M the first instruction in the called procedure. The operand can be an immediate value, a general-purpose register, or a memory location. This instruction can be used to execute four types of calls: • Near Call — A call to a procedure in the current code segment (the segment currently pointed to by the CS register), sometimes referred to as an intrasegment call.
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INSTRUCTION SET REFERENCE, A-M or 64 bits). In 64-bit mode the target operand will always be 64-bits because the operand size is forced to 64-bits for near branches. Far Calls in Real-Address or Virtual-8086 Mode. When executing a far call in realaddress or virtual-8086 mode, the processor pushes the current value of both the CS and EIP registers on the stack for use as a return-instruction pointer.
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INSTRUCTION SET REFERENCE, A-M segment selector for the new code segment and the new instruction pointer (offset) from the call gate descriptor. (The offset from the target operand is ignored when a call gate is used.) On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The segment selector for the new stack segment is specified in the TSS for the currently running task. The branch to the new code segment occurs after the stack switch.
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INSTRUCTION SET REFERENCE, A-M Far Calls in Compatibility Mode.
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INSTRUCTION SET REFERENCE, A-M pushes the segment selector and stack pointer for the calling procedure’s stack and the segment selector and instruction pointer for the calling procedure’s code segment. (Parameter copy is not supported in IA-32e mode.) Finally, the processor branches to the address of the procedure being called within the new code segment. Near/(Far) Calls in 64-bit Mode.
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INSTRUCTION SET REFERENCE, A-M Note that when using a call gate to perform a far call to a segment at the same privilege level, an implicit stack switch occurs as a result of entering 64-bit mode. The SS selector is unchanged, but stack segment accesses use a segment base of 0x0, the limit is ignored, and the default stack size is 64-bits. (The full value of RSP is used for the offset.
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INSTRUCTION SET REFERENCE, A-M THEN tempRIP ←DEST; (* DEST is r/m64 *) IF stack not large enough for a 8-byte return address THEN #SS(0); FI; Push(RIP); RIP ←tempRIP; FI; IF OperandSize = 32 THEN tempEIP ←DEST; (* DEST is r/m32 *) IF tempEIP is not within code segment limit THEN #GP(0); FI; IF stack not large enough for a 4-byte return address THEN #SS(0); FI; Push(EIP); EIP ←tempEIP; FI; IF OperandSize = 16 THEN tempEIP ←DEST AND 0000FFFFH; (* DEST is r/m16 *) IF tempEIP is not within code segment limit
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INSTRUCTION SET REFERENCE, A-M FI; Push(IP); CS ←DEST[31:16]; (* DEST is ptr16:16 or [m16:16] *) EIP ←DEST[15:0]; (* DEST is ptr16:16 or [m16:16]; clear upper 16 bits *) FI; IF far call and (PE = 1 and VM = 0) (* Protected mode or IA-32e Mode, not virtual-8086 mode*) THEN IF segment selector in target operand NULL THEN #GP(0); FI; IF segment selector index not within descriptor table limits THEN #GP(new code segment selector); FI; Read type and access rights of selected segment descriptor; IF IA32_EFER.
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INSTRUCTION SET REFERENCE, A-M tempEIP ←tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *) IF (EFER.
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INSTRUCTION SET REFERENCE, A-M tempEIP ←DEST(Offset); IF OperandSize = 16 THEN tempEIP ←tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *) IF (EFER.
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INSTRUCTION SET REFERENCE, A-M THEN #GP(code segment selector); FI; Read code segment descriptor; IF code-segment segment descriptor does not indicate a code segment or code-segment segment descriptor DPL > CPL THEN #GP(code segment selector); FI; IF IA32_EFER.
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INSTRUCTION SET REFERENCE, A-M or stack segment DPL ≠ DPL of code segment or stack segment is not a writable data segment) THEN #TS(SS selector); FI IF IA32_EFER.
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INSTRUCTION SET REFERENCE, A-M (* Segment descriptor information also loaded *) Push(oldSS:oldESP); (* From calling procedure *) Push(oldCS:oldEIP); (* Return address to calling procedure *) FI; FI; CPL ←CodeSegment(DPL) CS(RPL) ←CPL END; SAME-PRIVILEGE: IF CallGateSize = 32 THEN IF stack does not have room for 8 bytes THEN #SS(0); FI; IF CallGate(InstructionPointer) not within code segment limit THEN #GP(0); FI; CS:EIP ←CallGate(CS:EIP) (* Segment descriptor information also loaded *) Push(oldCS:oldEIP);
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INSTRUCTION SET REFERENCE, A-M THEN #GP(task gate selector); FI; IF task gate not present THEN #NP(task gate selector); FI; Read the TSS segment selector in the task-gate descriptor; IF TSS segment selector local/global bit is set to local or index not within GDT limits THEN #GP(TSS selector); FI; Access TSS descriptor in GDT; IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001) THEN #GP(TSS selector); FI; IF TSS not present THEN #NP(TSS selector); FI; SWITCH-TASKS (with nesting
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INSTRUCTION SET REFERENCE, A-M #GP(selector) If a code segment or gate or TSS selector index is outside descriptor table limits. If the segment descriptor pointed to by the segment selector in the destination operand is not for a conforming-code segment, nonconforming-code segment, call gate, task gate, or task state segment. If the DPL for a nonconforming-code segment is not equal to the CPL or the RPL for the segment’s segment selector is greater than the CPL.
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INSTRUCTION SET REFERENCE, A-M If the RPL of the new stack segment selector in the TSS is not equal to the DPL of the code segment being accessed. If DPL of the stack segment descriptor for the new stack segment is not equal to the DPL of the code segment descriptor. If the new stack segment is not a writable data segment. If segment-selector index for stack segment is outside descriptor table limits. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M If code segment or 64-bit call gate overlaps non-canonical space. If the segment descriptor pointed to by the segment selector in the destination operand is not for a conforming-code segment, nonconforming-code segment, or 64-bit call gate. If the segment descriptor pointed to by the segment selector in the destination operand is a code segment and has both the Dbit and the L- bit set.
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INSTRUCTION SET REFERENCE, A-M CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 98 CBW Valid Valid AX ←sign-extend of AL. 98 CWDE Valid Valid EAX ←sign-extend of AX. REX.W + 98 CDQE Valid N.E. RAX ←sign-extend of EAX. Description Double the size of the source operand by means of sign extension.
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INSTRUCTION SET REFERENCE, A-M CLC—Clear Carry Flag Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F8 CLC Valid Valid Clear CF flag. Description Clears the CF flag in the EFLAGS register. Operation is the same in all non-64-bit modes and 64-bit mode. Operation CF ←0; Flags Affected The CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected. Exceptions (All Operating Modes) #UD 3-106 Vol. 2A If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M CLD—Clear Direction Flag Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description FC CLD Valid Valid Clear DF flag. Description Clears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations increment the index registers (ESI and/or EDI). Operation is the same in all non-64-bit modes and 64-bit mode. Operation DF ←0; Flags Affected The DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.
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INSTRUCTION SET REFERENCE, A-M CLFLUSH—Flush Cache Line Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F AE /7 CLFLUSH m8 Valid Flushes cache line containing m8. Valid Description Invalidates the cache line that contains the linear address specified with the source operand from all levels of the processor cache hierarchy (data and instruction). The invalidation is broadcast throughout the cache coherence domain.
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INSTRUCTION SET REFERENCE, A-M Operation Flush_Cache_Line(SRC); Intel C/C++Compiler Intrinsic Equivalents CLFLUSH void _mm_clflush(void const *p) Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #UD If CPUID.01H:EDX.CLFSH[bit 19] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M CLI — Clear Interrupt Flag Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description FA CLI Valid Valid Clear interrupt flag; interrupts disabled when interrupt flag cleared. Description If protected-mode virtual interrupts are not enabled, CLI clears the IF flag in the EFLAGS register. No other flags are affected. Clearing the IF flag causes the processor to ignore maskable external interrupts.
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INSTRUCTION SET REFERENCE, A-M THEN IF IOPL ←CPL THEN IF ←0; (* Reset Interrupt Flag *) ELSE IF ((IOPL < CPL) and (CPL = 3) and (PVI = 1)) THEN VIF ←0; (* Reset Virtual Interrupt Flag *) ELSE #GP(0); FI; FI; ELSE (* VM = 1 *) IF IOPL = 3 THEN IF ←0; (* Reset Interrupt Flag *) ELSE IF (IOPL < 3) AND (VME = 1) THEN VIF ←0; (* Reset Virtual Interrupt Flag *) ELSE #GP(0); FI; FI; FI; FI; Flags Affected If protected-mode virtual interrupts are not enabled, IF is set to 0 if the CPL is equal to or less than the
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INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure. #UD If the LOCK prefix is used. 3-112 Vol.
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INSTRUCTION SET REFERENCE, A-M CLTS—Clear Task-Switched Flag in CR0 Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 06 CLTS Valid Valid Clears TS flag in CR0. Description Clears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system procedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in real-address mode to allow initialization for protected mode.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #GP(0) If the CPL is greater than 0. #UD If the LOCK prefix is used. 3-114 Vol.
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INSTRUCTION SET REFERENCE, A-M CMC—Complement Carry Flag Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F5 CMC Valid Complement CF flag. Valid Description Complements the CF flag in the EFLAGS register. CMC operation is the same in non64-bit modes and 64-bit mode. Operation EFLAGS.CF[bit 0]←NOT EFLAGS.CF[bit 0]; Flags Affected The CF flag contains the complement of its original value. The OF, ZF, SF, AF, and PF flags are unaffected.
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INSTRUCTION SET REFERENCE, A-M CMOVcc—Conditional Move Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 47 /r CMOVA r16, r/m16 Valid Valid Move if above (CF=0 and ZF=0). 0F 47 /r CMOVA r32, r/m32 Valid Valid Move if above (CF=0 and ZF=0). REX.W + 0F 47 /r CMOVA r64, r/m64 Valid N.E. Move if above (CF=0 and ZF=0). 0F 43 /r CMOVAE r16, r/m16 Valid Valid Move if above or equal (CF=0). 0F 43 /r CMOVAE r32, r/m32 Valid Valid Move if above or equal (CF=0). REX.
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INSTRUCTION SET REFERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 4D /r CMOVGE r32, r/m32 Valid Valid Move if greater or equal (SF=OF). REX.W + 0F 4D /r CMOVGE r64, r/m64 Valid N.E. Move if greater or equal (SF=OF). 0F 4C /r CMOVL r16, r/m16 Valid Valid Move if less (SF≠ OF). 0F 4C /r CMOVL r32, r/m32 Valid Valid Move if less (SF≠ OF). REX.W + 0F 4C /r CMOVL r64, r/m64 Valid N.E. Move if less (SF≠ OF).
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INSTRUCTION SET REFERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 43 /r CMOVNC r16, r/m16 Valid Valid Move if not carry (CF=0). 0F 43 /r CMOVNC r32, r/m32 Valid Valid Move if not carry (CF=0). REX.W + 0F 43 /r CMOVNC r64, r/m64 Valid N.E. Move if not carry (CF=0). 0F 45 /r CMOVNE r16, r/m16 Valid Valid Move if not equal (ZF=0). 0F 45 /r CMOVNE r32, r/m32 Valid Valid Move if not equal (ZF=0). REX.W + 0F 45 /r CMOVNE r64, r/m64 Valid N.E.
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INSTRUCTION SET REFERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description REX.W + 0F 4B /r CMOVNP r64, r/m64 Valid N.E. Move if not parity (PF=0). 0F 49 /r CMOVNS r16, r/m16 Valid Valid Move if not sign (SF=0). 0F 49 /r CMOVNS r32, r/m32 Valid Valid Move if not sign (SF=0). REX.W + 0F 49 /r CMOVNS r64, r/m64 Valid N.E. Move if not sign (SF=0). 0F 45 /r CMOVNZ r16, r/m16 Valid Valid Move if not zero (ZF=0).
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INSTRUCTION SET REFERENCE, A-M Description The CMOVcc instructions check the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and perform a move operation if the flags are in a specified state (or condition). A condition code (cc) is associated with each instruction to indicate the condition being tested for. If the condition is not satisfied, a move is not performed and execution continues with the instruction following the CMOVcc instruction.
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INSTRUCTION SET REFERENCE, A-M FI; DEST ←temp; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. 3-122 Vol.
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INSTRUCTION SET REFERENCE, A-M CMP—Compare Two Operands Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 3C ib CMP AL, imm8 Valid Valid Compare imm8 with AL. 3D iw CMP AX, imm16 Valid Valid Compare imm16 with AX. 3D id CMP EAX, imm32 Valid Valid Compare imm32 with EAX. REX.W + 3D id CMP RAX, imm32 Valid N.E. Compare imm32 signextended to 64-bits with RAX. 80 /7 ib CMP r/m8, imm8 Valid Compare imm8 with r/m8. Valid * REX + 80 /7 ib CMP r/m8 , imm8 Valid N.E.
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INSTRUCTION SET REFERENCE, A-M Description Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results. The comparison is performed by subtracting the second operand from the first operand and then setting the status flags in the same manner as the SUB instruction. When an immediate value is used as an operand, it is sign-extended to the length of the first operand.
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INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M CMPPD—Compare Packed Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F C2 /r ib CMPPD xmm1, xmm2/m128, imm8 Valid Valid Compare packed doubleprecision floating-point values in xmm2/m128 and xmm1 using imm8 as comparison predicate.
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INSTRUCTION SET REFERENCE, A-M Table 3-7. Comparison Predicate for CMPPD and CMPPS Instructions (Contd.
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INSTRUCTION SET REFERENCE, A-M Table 3-8. Pseudo-Op and CMPPD Implementation Pseudo-Op CMPPD Implementation CMPNLEPD xmm1, xmm2 CMPPD xmm1, xmm2, 6 CMPORDPD xmm1, xmm2 CMPPD xmm1, xmm2, 7 The greater-than relations that the processor does not implement require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops.
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INSTRUCTION SET REFERENCE, A-M CMPPD for inequality __m128d _mm_cmpneq_pd(__m128d a, __m128d b) CMPPD for not-less-than __m128d _mm_cmpnlt_pd(__m128d a, __m128d b) CMPPD for not-greater-than __m128d _mm_cmpngt_pd(__m128d a, __m128d b) CMPPD for not-greater-than-or-equal__m128d _mm_cmpnge_pd(__m128d a, __m128d b) CMPPD for ordered __m128d _mm_cmpord_pd(__m128d a, __m128d b) CMPPD for unordered __m128d _mm_cmpunord_pd(__m128d a, __m128d b) CMPPD for not-less-than-or-equal__m128d _mm_cmpnle_pd(__m12
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form.
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INSTRUCTION SET REFERENCE, A-M CMPPS—Compare Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F C2 /r ib CMPPS xmm1, xmm2/m128, imm8 Valid Valid Compare packed singleprecision floating-point values in xmm2/mem and xmm1 using imm8 as comparison predicate.
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INSTRUCTION SET REFERENCE, A-M Table 3-9.
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INSTRUCTION SET REFERENCE, A-M THEN DEST95:64] ←FFFFFFFFH; ELSE DEST[95:64] ←00000000H; FI; IF CMP3 = TRUE THEN DEST[127:96] ←FFFFFFFFH; ELSE DEST[127:96] ←00000000H; FI; Intel C/C++Compiler Intrinsic Equivalents CMPPS for equality __m128 _mm_cmpeq_ps(__m128 a, __m128 b) CMPPS for less-than __m128 _mm_cmplt_ps(__m128 a, __m128 b) CMPPS for less-than-or-equal __m128 _mm_cmple_ps(__m128 a, __m128 b) CMPPS for greater-than __m128 _mm_cmpgt_ps(__m128 a, __m128 b) CMPPS for greater-than-or-equal__m128
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INSTRUCTION SET REFERENCE, A-M If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. CMPPS—Compare Packed Single-Precision Floating-Point Values Vol.
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INSTRUCTION SET REFERENCE, A-M CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description A6 CMPS m8, m8 Valid Valid For legacy mode, compare byte at address DS:(E)SI with byte at address ES:(E)DI; For 64-bit mode compare byte at address (R|E)SI to byte at address (R|E)DI. The status flags are set accordingly.
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INSTRUCTION SET REFERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description A7 CMPSW Valid Valid For legacy mode, compare word at address DS:(E)SI with word at address ES:(E)DI; For 64-bit mode compare word at address (R|E)SI with word at address (R|E)DI. The status flags are set accordingly. A7 CMPSD Valid Valid For legacy mode, compare dword at address DS:(E)SI with dword at address ES:(E)DI; For 64-bit mode compare dword at address (R|E)SI with dword at address (R|E)DI.
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INSTRUCTION SET REFERENCE, A-M RDI) registers are assumed by the processor to specify the location of the source operands. The size of the source operands is selected with the mnemonic: CMPSB (byte comparison), CMPSW (word comparison), CMPSD (doubleword comparison), or CMPSQ (quadword comparison using REX.W). After the comparison, the (E/R)SI and (E/R)DI registers increment or decrement automatically according to the setting of the DF flag in the EFLAGS register.
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INSTRUCTION SET REFERENCE, A-M (R|E)DI ←(R|E)DI – 2; FI; ELSE IF (Doubleword comparison) THEN IF DF = 0 THEN (R|E)SI ←(R|E)SI +4; (R|E)DI ←(R|E)DI +4; ELSE (R|E)SI ←(R|E)SI – 4; (R|E)DI ←(R|E)DI – 4; FI; ELSE (* Quadword comparison *) THEN IF DF = 0 (R|E)SI ←(R|E)SI +8; (R|E)DI ←(R|E)DI +8; ELSE (R|E)SI ←(R|E)SI – 8; (R|E)DI ←(R|E)DI – 8; FI; FI; ELSE (* Non-64-bit Mode *) IF (byte comparison) THEN IF DF = 0 THEN (E)SI ←(E)SI +1; (E)DI ←(E)DI +1; ELSE (E)SI ←(E)SI – 1; (E)DI ←(E)DI – 1; FI; ELSE IF (Word c
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INSTRUCTION SET REFERENCE, A-M FI; (E)SI ←(E)SI – 4; (E)DI ←(E)DI – 4; FI; FI; Flags Affected The CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result of the comparison. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands Vol.
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INSTRUCTION SET REFERENCE, A-M CMPSD—Compare Scalar Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F C2 /r ib CMPSD xmm1, xmm2/m64, imm8 Valid Valid Compare low doubleprecision floating-point value in xmm2/m64 and xmm1 using imm8 as comparison predicate.
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INSTRUCTION SET REFERENCE, A-M Table 3-10. Pseudo-Ops and CMPSD (Contd.) Pseudo-Op Implementation CMPUNORDSD xmm1, xmm2 CMPSD xmm1,xmm2, 3 CMPNEQSD xmm1, xmm2 CMPSD xmm1,xmm2, 4 CMPNLTSD xmm1, xmm2 CMPSD xmm1,xmm2, 5 CMPNLESD xmm1, xmm2 CMPSD xmm1,xmm2, 6 CMPORDSD xmm1, xmm2 CMPSD xmm1,xmm2, 7 The greater-than relations not implemented in the processor require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops.
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INSTRUCTION SET REFERENCE, A-M CMPSD for greater-than-or-equal__m128d _mm_cmpge_sd(__m128d a, __m128d b) CMPSD for inequality __m128d _mm_cmpneq_sd(__m128d a, __m128d b) CMPSD for not-less-than __m128d _mm_cmpnlt_sd(__m128d a, __m128d b) CMPSD for not-greater-than __m128d _mm_cmpngt_sd(__m128d a, __m128d b) CMPSD for not-greater-than-or-equal__m128d _mm_cmpnge_sd(__m128d a, __m128d b) CMPSD for ordered __m128d _mm_cmpord_sd(__m128d a, __m128d b) CMPSD for unordered __m128d _mm_cmpunord_sd(__m128d
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INSTRUCTION SET REFERENCE, A-M If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form.
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INSTRUCTION SET REFERENCE, A-M CMPSS—Compare Scalar Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F C2 /r ib CMPSS xmm1, xmm2/m32, imm8 Valid Valid Compare low single-precision floating-point value in xmm2/m32 and xmm1 using imm8 as comparison predicate.
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INSTRUCTION SET REFERENCE, A-M Table 3-11.
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INSTRUCTION SET REFERENCE, A-M CMPSS for less-than __m128 _mm_cmplt_ss(__m128 a, __m128 b) CMPSS for less-than-or-equal __m128 _mm_cmple_ss(__m128 a, __m128 b) CMPSS for greater-than __m128 _mm_cmpgt_ss(__m128 a, __m128 b) CMPSS for greater-than-or-equal__m128 _mm_cmpge_ss(__m128 a, __m128 b) CMPSS for inequality __m128 _mm_cmpneq_ss(__m128 a, __m128 b) CMPSS for not-less-than __m128 _mm_cmpnlt_ss(__m128 a, __m128 b) CMPSS for not-greater-than __m128 _mm_cmpngt_ss(__m128 a, __m128 b) CMPSS for
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made.
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INSTRUCTION SET REFERENCE, A-M CMPXCHG—Compare and Exchange Opcode Instruction 0F B0/r 64-Bit Mode Compat/ Leg Mode Description CMPXCHG r/m8, r8 Valid Valid* Compare AL with r/m8. If equal, ZF is set and r8 is loaded into r/m8. Else, clear ZF and load r/m8 into AL. REX + 0F B0/r CMPXCHG r/m8**,r8 Valid N.E. Compare AL with r/m8. If equal, ZF is set and r8 is loaded into r/m8. Else, clear ZF and load r/m8 into AL. 0F B1/r CMPXCHG r/m16, r16 Valid Valid* Compare AX with r/m16.
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INSTRUCTION SET REFERENCE, A-M In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. IA-32 Architecture Compatibility This instruction is not supported on Intel processors earlier than the Intel486 processors.
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INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used but the destination is not a memory operand. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, A-M CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes Opcode* Instruction 64-Bit Mode Compat/ Leg Mode Description 0F C7 /1 m64 CMPXCHG8B m64 Valid Valid* Compare EDX:EAX with m64. If equal, set ZF and load ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX. REX.W + 0F C7 /1 m128 CMPXCHG16B m128 Valid N.E. Compare RDX:RAX with m128. If equal, set ZF and load RCX:RBX into m128. Else, clear ZF and load m128 into RDX:RAX.
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INSTRUCTION SET REFERENCE, A-M Operation IF (64-Bit Mode and OperandSize = 64) THEN IF (RDX:RAX = DEST) ZF ←1; DEST ←RCX:RBX; ELSE ZF ←0; RDX:RAX ←DEST; FI ELSE IF (EDX:EAX = DEST) ZF ←1; DEST ←ECX:EBX; ELSE ZF ←0; EDX:EAX ←DEST; FI; FI; Flags Affected The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are unaffected. Protected Mode Exceptions #UD If the destination is not a memory operand.
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INSTRUCTION SET REFERENCE, A-M #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #UD If the destination operand is not a memory location. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made.
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INSTRUCTION SET REFERENCE, A-M COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS Opcode Instruction 66 0F 2F /r COMISD xmm1, xmm2/m64 64-Bit Mode Compat/ Leg Mode Description Valid Valid Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.
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INSTRUCTION SET REFERENCE, A-M int _mm_comile_sd (__m128d a, __m128d b) int _mm_comigt_sd (__m128d a, __m128d b) int _mm_comige_sd (__m128d a, __m128d b) int _mm_comineq_sd (__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (if SNaN or QNaN operands), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form.
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INSTRUCTION SET REFERENCE, A-M COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 2F /r COMISS xmm1, xmm2/m32 Valid Valid Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.
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INSTRUCTION SET REFERENCE, A-M int _mm_comile_ss (__m128 a, __m128 b) int _mm_comigt_ss (__m128 a, __m128 b) int _mm_comige_ss (__m128 a, __m128 b) int _mm_comineq_ss (__m128 a, __m128 b) SIMD Floating-Point Exceptions Invalid (if SNaN or QNaN operands), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.
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INSTRUCTION SET REFERENCE, A-M CPUID—CPU Identification Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F A2 CPUID Valid Returns processor identification and feature information to the EAX, EBX, ECX, and EDX registers, as determined by input entered in EAX (in some cases, ECX as well). Valid Description The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction.
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INSTRUCTION SET REFERENCE, A-M See also: “Serializing Instructions” in Chapter 7, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618) Table 3-12.
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INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.) Initial EAX Value Information Provided about the Processor CPUID leaves > 3 < 80000000 are visible only when IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default). Deterministic Cache Parameters Leaf 04H NOTES: 04H output depends on the initial value in ECX. See also: “INPUT EAX = 4: Returns Deterministic Cache Parameters for each level on page 3-180.
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INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.
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INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.
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INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.
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INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.) Initial EAX Value Information Provided about the Processor 80000007H EAX EBX ECX EDX Reserved = 0 Reserved = 0 Reserved = 0 Reserved = 0 80000008H EAX Virtual/Physical Address size Bits 7-0: #Physical Address Bits* Bits 15-8: #Virtual Address Bits Bits 31-16: Reserved = 0 EBX ECX EDX Reserved = 0 Reserved = 0 Reserved = 0 NOTES: * If CPUID.
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INSTRUCTION SET REFERENCE, A-M Table 3-13.
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INSTRUCTION SET REFERENCE, A-M See Table 3-14 for available processor type values. Stepping IDs are provided as needed. 31 28 27 20 19 Extended Family ID EAX 16 15 14 13 12 11 Extended Model ID 8 7 Family ID 4 Model 3 0 Stepping ID Extended Family ID (0) Extended Model ID (0) Processor Type Family (0FH for the Pentium 4 Processor Family) Model Reserved OM16525 Figure 3-5. Version Information Returned by CPUID in EAX Table 3-14.
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INSTRUCTION SET REFERENCE, A-M (* Right justify and zero-extend 4-bit field. *) FI; (* Show Display_Family as HEX field. *) The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. Integrate the field into a display using the following rule: IF (Family_ID = 06H or Family_ID = 0FH) THEN Displayed_Model = (Extended_Model_ID << 4) + Model_ID; (* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.
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INSTRUCTION SET REFERENCE, A-M 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ECX POPCNT SSE4.2 SSE4.1 PDCM — Perf/Debug Capability MSR xTPR Update Control CMPXCHG16B CNXT-ID — L1 Context ID SSSE3 — SSSE3 Extensions TM2 — Thermal Monitor 2 EST — Enhanced Intel SpeedStep® Technology SMX — Safer Mode Extensions VMX — Virtual Machine Extensions DS-CPL — CPL Qualified Debug Store MONITOR — MONITOR/MWAIT SSE3 — SSE3 Extensions Reserved OM16524b Figure 3-6.
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INSTRUCTION SET REFERENCE, A-M Table 3-15. Feature Information Returned in the ECX Register Bit # Mnemonic Description 0 SSE3 Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this technology. 1-2 Reserved Reserved 3 MONITOR MONITOR/MWAIT. A value of 1 indicates the processor supports this feature. 4 DS-CPL CPL Qualified Debug Store.
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INSTRUCTION SET REFERENCE, A-M Table 3-15. Feature Information Returned in the ECX Register (Contd.) Bit # Mnemonic Description 21 - 22 Reserved Reserved 23 POPCNT A value of 1 indicates that the processor supports the POPCNT instruction.
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INSTRUCTION SET REFERENCE, A-M Table 3-16. More on Feature Information Returned in the EDX Register Bit # Mnemonic Description 0 FPU Floating Point Unit On-Chip. The processor contains an x87 FPU. 1 VME Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.
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INSTRUCTION SET REFERENCE, A-M Table 3-16. More on Feature Information Returned in the EDX Register (Contd.) Bit # Mnemonic Description 13 PGE PTE Global Bit. The global bit in page directory entries (PDEs) and page table entries (PTEs) is supported, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature. 14 MCA Machine Check Architecture.
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INSTRUCTION SET REFERENCE, A-M Table 3-16. More on Feature Information Returned in the EDX Register (Contd.) Bit # Mnemonic Description 25 SSE SSE. The processor supports the SSE extensions. 26 SSE2 SSE2. The processor supports the SSE2 extensions. 27 SS Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus. 28 HTT Multi-Threading.
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INSTRUCTION SET REFERENCE, A-M Table 3-17.
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INSTRUCTION SET REFERENCE, A-M Table 3-17. Encoding of Cache and TLB Descriptors (Contd.
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INSTRUCTION SET REFERENCE, A-M Example 3-1. Example of Cache and TLB Interpretation The first member of the family of Pentium 4 processors returns the following information about caches and TLBs when the CPUID executes with an input value of 2: EAX EBX ECX EDX 66 5B 50 01H 0H 0H 00 7A 70 00H Which means: • The least-significant byte (byte 0) of register EAX is set to 01H. This indicates that CPUID needs to be executed once with an input value of 2 to retrieve complete information about caches and TLBs.
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INSTRUCTION SET REFERENCE, A-M query maximum number of cores per physical package by executing CPUID with EAX=4 and ECX=0. INPUT EAX = 5: Returns MONITOR and MWAIT Features When CPUID executes with EAX set to 5, the processor returns information about features available to MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power management.
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INSTRUCTION SET REFERENCE, A-M This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the maximum operating frequency of the processor to the EAX, EBX, ECX, and EDX registers. Input: EAX= 0x80000000 CPUID IF (EAX & 0x80000000) CPUID Function Supported False Processor Brand String Not Supported True Processor Brand String Supported True ≥ Extended EAX Return Value = Max.
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INSTRUCTION SET REFERENCE, A-M Table 3-18 shows the brand string that is returned by the first processor in the Pentium 4 processor family. Table 3-18.
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INSTRUCTION SET REFERENCE, A-M 6FDQ %UDQG 6WULQJ LQ 5HYHUVH %\WH 2UGHU ]+0 RU 0DWFK ]+* RU 6XEVWULQJ ]+7 )DOVH ,) 6XEVWULQJ 0DWFKHG 'HWHUPLQH )UHT DQG 0XOWLSOLHU ,I ]+0 7UXH ,I ]+* 'HWHUPLQH 0XOWLSOLHU ,I ]+7 6FDQ 'LJLWV 8QWLO %ODQN 'HWHUPLQH )UHT ,Q 5HYHUVH 2UGHU 0D[ 4XDOLILHG )UHTXHQF\ )UHT [ 0XOWLSOLHU 5HSRUW (UURU 0XOWLSOLHU [ 0XOWLSOLHU [ 0XOWLSOLHU [ 5HYHUVH 'LJLWV 7R 'HFLPDO 9DOXH )UHT ;< = LI 'LJLWV = <; 20 Figure
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INSTRUCTION SET REFERENCE, A-M do not support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand index method is no longer supported. Use brand string method instead. Table 3-19 shows brand indices that have identification strings associated with them. Table 3-19.
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INSTRUCTION SET REFERENCE, A-M IA-32 Architecture Compatibility CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the Intel486 processor.
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INSTRUCTION SET REFERENCE, A-M BREAK EAX = 4H: EAX ←Deterministic Cache Parameters Leaf; (* See Table 3-12. *) EBX ←Deterministic Cache Parameters Leaf; ECX ←Deterministic Cache Parameters Leaf; EDX ←Deterministic Cache Parameters Leaf; BREAK; EAX = 5H: EAX ←MONITOR/MWAIT Leaf; (* See Table 3-12. *) EBX ←MONITOR/MWAIT Leaf; ECX ←MONITOR/MWAIT Leaf; EDX ←MONITOR/MWAIT Leaf; BREAK; EAX = 6H: EAX ←Thermal and Power Management Leaf; (* See Table 3-12.
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INSTRUCTION SET REFERENCE, A-M EAX = 80000002H: EAX ←Processor Brand String; EBX ←Processor Brand String, continued; ECX ←Processor Brand String, continued; EDX ←Processor Brand String, continued; BREAK; EAX = 80000003H: EAX ←Processor Brand String, continued; EBX ←Processor Brand String, continued; ECX ←Processor Brand String, continued; EDX ←Processor Brand String, continued; BREAK; EAX = 80000004H: EAX ←Processor Brand String, continued; EBX ←Processor Brand String, continued; ECX ←Processor Brand Strin
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INSTRUCTION SET REFERENCE, A-M EAX ←Reserved; (* Information returned for highest basic information leaf. *) EBX ←Reserved; (* Information returned for highest basic information leaf. *) ECX ←Reserved; (* Information returned for highest basic information leaf. *) EDX ←Reserved; (* Information returned for highest basic information leaf. *) BREAK; ESAC; Flags Affected None. Exceptions (All Operating Modes) #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M CVTDQ2PD—Convert Packed Doubleword Integers to Packed DoublePrecision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F E6 CVTDQ2PD xmm1, xmm2/m64 Valid Valid Convert two packed signed doubleword integers from xmm2/m128 to two packed double-precision floating-point values in xmm1.
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INSTRUCTION SET REFERENCE, A-M If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M CVTDQ2PS—Convert Packed Doubleword Integers to Packed SinglePrecision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 5B /r CVTDQ2PS xmm1, xmm2/m128 Valid Valid Convert four packed signed doubleword integers from xmm2/m128 to four packed single-precision floating-point values in xmm1.
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INSTRUCTION SET REFERENCE, A-M #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
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INSTRUCTION SET REFERENCE, A-M #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. 3-194 Vol.
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INSTRUCTION SET REFERENCE, A-M CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F E6 CVTPD2DQ xmm1, xmm2/m128 Valid Valid Convert two packed doubleprecision floating-point values from xmm2/m128 to two packed signed doubleword integers in xmm1.
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INSTRUCTION SET REFERENCE, A-M If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M CVTPD2PI—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 2D /r CVTPD2PI mm, xmm/m128 Valid Valid Convert two packed doubleprecision floating-point values from xmm/m128 to two packed signed doubleword integers in mm.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #MF If there is a pending x87 FPU exception. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #MF If there is a pending x87 FPU exception. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.
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INSTRUCTION SET REFERENCE, A-M CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 5A /r CVTPD2PS xmm1, xmm2/m128 Valid Valid Convert two packed doubleprecision floating-point values in xmm2/m128 to two packed singleprecision floating-point values in xmm1.
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INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
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INSTRUCTION SET REFERENCE, A-M CVTPI2PD—Convert Packed Doubleword Integers to Packed DoublePrecision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 2A /r CVTPI2PD xmm, mm/m64* Valid Valid Convert two packed signed doubleword integers from mm/mem64 to two packed doubleprecision floating-point values in xmm. NOTES: * Operation is different for different operand sets; see the Description section.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M #MF If there is a pending x87 FPU exception. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) 3-206 Vol. 2A If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, A-M CVTPI2PS—Convert Packed Doubleword Integers to Packed SinglePrecision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 2A /r CVTPI2PS xmm, mm/m64 Valid Valid Convert two signed doubleword integers from mm/m64 to two singleprecision floating-point values in xmm.
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INSTRUCTION SET REFERENCE, A-M #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.
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INSTRUCTION SET REFERENCE, A-M CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 5B /r CVTPS2DQ xmm1, xmm2/m128 Valid Valid Convert four packed single-precision floating-point values from xmm2/m128 to four packed signed doubleword integers in xmm1.
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INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. 3-212 Vol.
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INSTRUCTION SET REFERENCE, A-M CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 5A /r CVTPS2PD xmm1, xmm2/m64 Valid Valid Convert two packed single-precision floating-point values in xmm2/m64 to two packed double-precision floating-point values in xmm1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed DoublePrecision Floating-Point Values Vol.
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INSTRUCTION SET REFERENCE, A-M CVTPS2PI—Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 2D /r CVTPS2PI mm, xmm/m64 Valid Valid Convert two packed single-precision floating-point values from xmm/m64 to two packed signed doubleword integers in mm.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #MF If there is a pending x87 FPU exception. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
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INSTRUCTION SET REFERENCE, A-M CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 2D /r CVTSD2SI r32, xmm/m64 Valid Valid Convert one double-precision floating-point value from xmm/m64 to one signed doubleword integer r32. F2 REX.W 0F 2D /r CVTSD2SI r64, xmm/m64 Valid N.E. Convert one double-precision floating-point value from xmm/m64 to one signed quadword integer signextended into r64.
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INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid, Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
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INSTRUCTION SET REFERENCE, A-M CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 5A /r CVTSD2SS xmm1, xmm2/m64 Valid Valid Convert one double-precision floatingpoint value in xmm2/m64 to one single-precision floating-point value in xmm1.
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INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) 3-224 Vol. 2A If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, A-M CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 2A /r CVTSI2SD xmm, r/m32 Valid Valid Convert one signed doubleword integer from r/m32 to one double-precision floating-point value in xmm. F2 REX.W 0F 2A /r CVTSI2SD xmm, r/m64 Valid N.E. Convert one signed quadword integer from r/m64 to one double-precision floating-point value in xmm.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.
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INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
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INSTRUCTION SET REFERENCE, A-M CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 2A /r CVTSI2SS xmm, r/m32 Valid Valid Convert one signed doubleword integer from r/m32 to one singleprecision floating-point value in xmm. F3 REX.W 0F 2A /r CVTSI2SS xmm, r/m64 Valid N.E. Convert one signed quadword integer from r/m64 to one singleprecision floating-point value in xmm.
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INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
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INSTRUCTION SET REFERENCE, A-M CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 5A /r CVTSS2SD xmm1, xmm2/m32 Valid Valid Convert one single-precision floatingpoint value in xmm2/m32 to one double-precision floating-point value in xmm1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value Vol.
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INSTRUCTION SET REFERENCE, A-M CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 2D /r CVTSS2SI r32, xmm/m32 Valid Valid Convert one single-precision floating-point value from xmm/m32 to one signed doubleword integer in r32. F3 REX.W 0F 2D /r CVTSS2SI r64, xmm/m32 Valid N.E. Convert one single-precision floating-point value from xmm/m32 to one signed quadword integer in r64.
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INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid, Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
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INSTRUCTION SET REFERENCE, A-M CVTTPD2PI—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 2C /r CVTTPD2PI mm, xmm/m128 Valid Valid Convert two packer double-precision floating-point values from xmm/m128 to two packed signed doubleword integers in mm using truncation.
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INSTRUCTION SET REFERENCE, A-M If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #MF If there is a pending x87 FPU exception. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.
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INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
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INSTRUCTION SET REFERENCE, A-M CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F E6 CVTTPD2DQ xmm1, xmm2/m128 Valid Valid Convert two packed doubleprecision floating-point values from xmm2/m128 to two packed signed doubleword integers in xmm1 using truncation.
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INSTRUCTION SET REFERENCE, A-M If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 5B /r CVTTPS2DQ xmm1, xmm2/m128 Valid Valid Convert four single-precision floating-point values from xmm2/m128 to four signed doubleword integers in xmm1 using truncation.
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INSTRUCTION SET REFERENCE, A-M #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
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INSTRUCTION SET REFERENCE, A-M #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers Vol.
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INSTRUCTION SET REFERENCE, A-M CVTTPS2PI—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 2C /r CVTTPS2PI mm, xmm/m64 Valid Valid Convert two single-precision floatingpoint values from xmm/m64 to two signed doubleword signed integers in mm using truncation.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #MF If there is a pending x87 FPU exception. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
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INSTRUCTION SET REFERENCE, A-M CVTTSD2SI—Convert with Truncation Scalar Double-Precision FloatingPoint Value to Signed Doubleword Integer Opcode Instruction F2 0F 2C /r F2 REX.W 0F 2C /r 64-Bit Mode Compat/ Leg Mode Description CVTTSD2SI r32, Valid xmm/m64 Valid Convert one double-precision floating-point value from xmm/m64 to one signed doubleword integer in r32 using truncation. CVTTSD2SI r64, Valid xmm/m64 N.E.
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INSTRUCTION SET REFERENCE, A-M Intel C/C++Compiler Intrinsic Equivalent int _mm_cvttsd_si32(__m128d a) SIMD Floating-Point Exceptions Invalid, Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
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INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
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INSTRUCTION SET REFERENCE, A-M CVTTSS2SI—Convert with Truncation Scalar Single-Precision FloatingPoint Value to Doubleword Integer Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 2C /r CVTTSS2SI r32, xmm/m32 Valid Valid Convert one single-precision floating-point value from xmm/m32 to one signed doubleword integer in r32 using truncation. F3 REX.W 0F 2C /r CVTTSS2SI r64, xmm/m32 Valid N.E.
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INSTRUCTION SET REFERENCE, A-M Intel C/C++Compiler Intrinsic Equivalent int _mm_cvttss_si32(__m128d a) SIMD Floating-Point Exceptions Invalid, Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
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INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
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INSTRUCTION SET REFERENCE, A-M CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 99 CWD Valid Valid DX:AX ←sign-extend of AX. 99 CDQ Valid Valid EDX:EAX ←sign-extend of EAX. REX.W + 99 CQO Valid N.E. RDX:RAX←sign-extend of RAX.
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INSTRUCTION SET REFERENCE, A-M FI; RDX ←SignExtend(RAX); FI; Flags Affected None. Exceptions (All Operating Modes) #UD 3-256 Vol. 2A If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M DAA—Decimal Adjust AL after Addition Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 27 DAA Invalid Valid Decimal adjust AL after addition. Description Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and destination operand.
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INSTRUCTION SET REFERENCE, A-M Example ADD AL, BL DAA DAA Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXX After: AL=AEH BL=35H EFLAGS(0SZAPC)=110000 Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000 After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111 Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000 After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101 Flags Affected The CF and AF flags are set if the adjustment of the value results in a decimal carry in either digit of the result (see the “Operation” section above).
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INSTRUCTION SET REFERENCE, A-M DAS—Decimal Adjust AL after Subtraction Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 2F DAS Invalid Valid Decimal adjust AL after subtraction. Description Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the implied source and destination operand.
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INSTRUCTION SET REFERENCE, A-M Example SUB AL, BL DAA Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXX After: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111 Before: AL = EEH, BL = 47H, EFLAGS(OSZAPC) = 010111 After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111 Flags Affected The CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result (see the “Operation” section above). The SF, ZF, and PF flags are set according to the result.
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INSTRUCTION SET REFERENCE, A-M DEC—Decrement by 1 Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description FE /1 DEC r/m8 Valid Valid Decrement r/m8 by 1. REX + FE /1 DEC r/m8* Valid N.E. Decrement r/m8 by 1. FF /1 DEC r/m16 Valid Valid Decrement r/m16 by 1. FF /1 DEC r/m32 Valid Valid Decrement r/m32 by 1. REX.W + FF /1 DEC r/m64 Valid N.E. Decrement r/m64 by 1. 48+rw DEC r16 N.E. Valid Decrement r16 by 1. 48+rd DEC r32 N.E. Valid Decrement r32 by 1.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory operand. DEC—Decrement by 1 Vol.
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INSTRUCTION SET REFERENCE, A-M DIV—Unsigned Divide Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F6 /6 DIV r/m8 Valid Valid Unsigned divide AX by r/m8, with result stored in AL ←Quotient, AH ← Remainder. REX + F6 /6 DIV r/m8* Valid N.E. Unsigned divide AX by r/m8, with result stored in AL ←Quotient, AH ← Remainder. F7 /6 DIV r/m16 Valid Valid Unsigned divide DX:AX by r/m16, with result stored in AX ←Quotient, DX ← Remainder.
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INSTRUCTION SET REFERENCE, A-M Table 3-20.
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INSTRUCTION SET REFERENCE, A-M ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *) THEN temp ←RDX:RAX / SRC; IF temp > FFFFFFFFFFFFFFFFH THEN #DE; (* Divide error *) ELSE RAX ←temp; RDX ←RDX:RAX MOD SRC; FI; FI; FI; Flags Affected The CF, OF, SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #DE If the source operand (divisor) is 0 #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #DE If the source operand (divisor) is 0. If the quotient is too large for the designated register. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M DIVPD—Divide Packed Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 5E /r DIVPD xmm1, xmm2/m128 Valid Valid Divide packed double-precision floatingpoint values in xmm1 by packed doubleprecision floating-point values xmm2/m128.
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INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.
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INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. 3-270 Vol.
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INSTRUCTION SET REFERENCE, A-M DIVPS—Divide Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 5E /r DIVPS xmm1, xmm2/m128 Valid Valid Divide packed single-precision floatingpoint values in xmm1 by packed singleprecision floating-point values xmm2/m128.
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INSTRUCTION SET REFERENCE, A-M #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
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INSTRUCTION SET REFERENCE, A-M #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. DIVPS—Divide Packed Single-Precision Floating-Point Values Vol.
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INSTRUCTION SET REFERENCE, A-M DIVSD—Divide Scalar Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 5E /r DIVSD xmm1, xmm2/m64 Valid Valid Divide low double-precision floatingpoint value n xmm1 by low doubleprecision floating-point value in xmm2/mem64.
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INSTRUCTION SET REFERENCE, A-M If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
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INSTRUCTION SET REFERENCE, A-M If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) 3-276 Vol. 2A If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, A-M DIVSS—Divide Scalar Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 5E /r DIVSS xmm1, xmm2/m32 Valid Valid Divide low single-precision floatingpoint value in xmm1 by low singleprecision floating-point value in xmm2/m32.
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INSTRUCTION SET REFERENCE, A-M If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
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INSTRUCTION SET REFERENCE, A-M If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. DIVSS—Divide Scalar Single-Precision Floating-Point Values Vol.
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INSTRUCTION SET REFERENCE, A-M EMMS—Empty MMX Technology State Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 77 EMMS Valid Valid Set the x87 FPU tag word to empty. Description Sets the values of all the tags in the x87 FPU tag word to empty (all 1s). This operation marks the x87 FPU data registers (which are aliased to the MMX technology registers) as available for use by x87 FPU floating-point instructions.
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INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. EMMS—Empty MMX Technology State Vol.
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INSTRUCTION SET REFERENCE, A-M ENTER—Make Stack Frame for Procedure Parameters Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description C8 iw 00 ENTER imm16, 0 Valid Valid Create a stack frame for a procedure. C8 iw 01 ENTER imm16,1 Valid Valid Create a nested stack frame for a procedure. C8 iw ib ENTER imm16, imm8 Valid Valid Create a nested stack frame for a procedure. Description Creates a stack frame for a procedure.
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INSTRUCTION SET REFERENCE, A-M Operation NestingLevel ←NestingLevel MOD 32 IF 64-Bit Mode (StackSize = 64) THEN Push(RBP); FrameTemp ←RSP; ELSE IF StackSize = 32 THEN Push(EBP); FrameTemp ←ESP; FI; ELSE (* StackSize = 16 *) Push(BP); FrameTemp ←SP; FI; IF NestingLevel = 0 THEN GOTO CONTINUE; FI; IF (NestingLevel > 1) THEN FOR i ←1 to (NestingLevel - 1) DO IF 64-Bit Mode (StackSize = 64) THEN RBP ←RBP - 8; Push([RBP]); (* Quadword push *) ELSE IF OperandSize = 32 THEN IF StackSize = 32 EBP ←EBP - 4; Push([E
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INSTRUCTION SET REFERENCE, A-M FI; FI; OD; FI; IF 64-Bit Mode (StackSize = 64) THEN Push(FrameTemp); (* Quadword push *) ELSE IF OperandSize = 32 THEN Push(FrameTemp); FI; (* Doubleword push *) ELSE (* OperandSize = 16 *) Push(FrameTemp); (* Word push *) FI; CONTINUE: IF 64-Bit Mode (StackSize = 64) THEN RBP ←FrameTemp; RSP ←RSP −Size; ELSE IF StackSize = 32 THEN EBP ←FrameTemp; ESP ←ESP −Size; FI; ELSE (* StackSize = 16 *) BP ←FrameTemp; SP ←SP −Size; FI; END; Flags Affected None.
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INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #SS(0) If the new value of the SP or ESP register is outside the stack segment limit. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #SS(0) If the new value of the SP or ESP register is outside the stack segment limit. #PF(fault-code) If a page fault occurs or if a write using the final value of the stack pointer (within the current stack segment) would cause a page fault. #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M F2XM1—Compute 2x–1 Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 F0 F2XM1 Valid Valid Replace ST(0) with (2ST(0) – 1). Description Computes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in register ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range –1.0 to +1.0. If the source value is outside this range, the result is undefined.
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INSTRUCTION SET REFERENCE, A-M #U Result is too small for destination format. #P Value cannot be represented exactly in destination format. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M FABS—Absolute Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 E1 FABS Valid Valid Replace ST with its absolute value. Description Clears the sign bit of ST(0) to create the absolute value of the operand. The following table shows the results obtained when creating the absolute value of various classes of numbers. Table 3-22.
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INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. FABS—Absolute Value Vol.
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INSTRUCTION SET REFERENCE, A-M FADD/FADDP/FIADD—Add Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D8 /0 FADD m32fp Valid Valid Add m32fp to ST(0) and store result in ST(0). DC /0 FADD m64fp Valid Valid Add m64fp to ST(0) and store result in ST(0). D8 C0+i FADD ST(0), ST(i) Valid Valid Add ST(0) to ST(i) and store result in ST(0). DC C0+i FADD ST(i), ST(0) Valid Valid Add ST(i) to ST(0) and store result in ST(i).
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INSTRUCTION SET REFERENCE, A-M The table on the following page shows the results obtained when adding various classes of numbers, assuming that neither overflow nor underflow occurs. When the sum of two operands with opposite signs is 0, the result is +0, except for the round toward −∞ mode, in which case the result is −0. When the source operand is an integer 0, it is treated as a +0. When both operand are infinities of the same sign, the result is ∞ of the expected sign.
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INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Operand is an SNaN value or unsupported format. Operands are infinities of unlike sign. #D Source operand is a denormal value. #U Result is too small for destination format. #O Result is too large for destination format.
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INSTRUCTION SET REFERENCE, A-M #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M FBLD—Load Binary Coded Decimal Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description DF /4 FBLD m80 dec Valid Valid Convert BCD value to floating-point and push onto the FPU stack. Description Converts the BCD source operand into double extended-precision floating-point format and pushes the value onto the FPU stack. The source operand is loaded without rounding errors. The sign of the source operand is preserved, including that of −0.
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INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, A-M FBSTP—Store BCD Integer and Pop Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description DF /6 FBSTP m80bcd Valid Valid Store ST(0) in m80bcd and pop ST(0). Description Converts the value in the ST(0) register to an 18-digit packed BCD integer, stores the result in the destination operand, and pops the register stack.
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INSTRUCTION SET REFERENCE, A-M nation operand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation DEST ←BCD(ST(0)); PopRegisterStack; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred.
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INSTRUCTION SET REFERENCE, A-M #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made.
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INSTRUCTION SET REFERENCE, A-M FCHS—Change Sign Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 E0 FCHS Valid Valid Complements sign of ST(0). Description Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magnitude or vice versa. The following table shows the results obtained when changing the sign of various classes of numbers. Table 3-25.
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INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. 3-300 Vol.
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INSTRUCTION SET REFERENCE, A-M FCLEX/FNCLEX—Clear Exceptions Opcode* Instruction 64-Bit Mode Compat/ Leg Mode Description 9B DB E2 FCLEX Valid Valid Clear floating-point exception flags after checking for pending unmasked floatingpoint exceptions. DB E2 FNCLEX* Valid Valid Clear floating-point exception flags without checking for pending unmasked floating-point exceptions. NOTES: * See IA-32 Architecture Compatibility section below.
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INSTRUCTION SET REFERENCE, A-M FPU Flags Affected The PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are undefined. Floating-Point Exceptions None. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M FCMOVcc—Floating-Point Conditional Move Opcode* Instruction 64-Bit Mode Compat/ Leg Mode* Description DA C0+i FCMOVB ST(0), ST(i) Valid Valid Move if below (CF=1). DA C8+i FCMOVE ST(0), ST(i) Valid Valid Move if equal (ZF=1). DA D0+i FCMOVBE ST(0), ST(i) Valid Valid Move if below or equal (CF=1 or ZF=1). DA D8+i FCMOVU ST(0), ST(i) Valid Valid Move if unordered (PF=1). DB C0+i FCMOVNB ST(0), ST(i) Valid Valid Move if not below (CF=0).
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INSTRUCTION SET REFERENCE, A-M Operation IF condition TRUE THEN ST(0) ←ST(i); FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. Integer Flags Affected None. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M FCOM/FCOMP/FCOMPP—Compare Floating Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D8 /2 FCOM m32fp Valid Valid Compare ST(0) with m32fp. DC /2 FCOM m64fp Valid Valid Compare ST(0) with m64fp. D8 D0+i FCOM ST(i) Valid Valid Compare ST(0) with ST(i). D8 D1 FCOM Valid Valid Compare ST(0) with ST(1). D8 /3 FCOMP m32fp Valid Valid Compare ST(0) with m32fp and pop register stack.
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INSTRUCTION SET REFERENCE, A-M The FCOMP instruction pops the register stack following the comparison operation and the FCOMPP instruction pops the register stack twice following the comparison operation. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The FCOM instructions perform the same operation as the FUCOM instructions. The only difference is how they handle QNaN operands.
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INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS Stack underflow occurred. #IA One or both operands are NaN values or have unsupported formats. Register is marked empty. #D One or both operands are denormal values. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description DB F0+i FCOMI ST, ST(i) Valid Valid Compare ST(0) with ST(i) and set status flags accordingly. DF F0+i FCOMIP ST, ST(i) Valid Valid Compare ST(0) with ST(i), set status flags accordingly, and pop register stack.
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INSTRUCTION SET REFERENCE, A-M If the operation results in an invalid-arithmetic-operand exception being raised, the status flags in the EFLAGS register are set only if the exception is masked. The FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions clear the OF flag in the EFLAGS register (regardless of whether an invalid-operation exception is detected). The FCOMIP and FUCOMIP instructions also pop the register stack following the comparison operation.
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INSTRUCTION SET REFERENCE, A-M FI; ZF, PF, CF ←111; FI; FI; IF Instruction is FCOMIP or FUCOMIP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred; otherwise, set to 0. C0, C2, C3 Not affected. Floating-Point Exceptions #IS Stack underflow occurred. #IA (FCOMI or FCOMIP instruction) One or both operands are NaN values or have unsupported formats. (FUCOMI or FUCOMIP instruction) One or both operands are SNaN values (but not QNaNs) or have undefined formats.
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INSTRUCTION SET REFERENCE, A-M FCOS—Cosine Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 FF FCOS Valid Valid Replace ST(0) with its cosine. Description Computes the cosine of the source operand in register ST(0) and stores the result in ST(0). The source operand must be given in radians and must be within the range − 263 to +263. The following table shows the results obtained when taking the cosine of various classes of numbers. Table 3-28.
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INSTRUCTION SET REFERENCE, A-M ST(0) ←cosine(ST(0)); ELSE (* Source operand is out-of-range *) C2 ←1; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Undefined if C2 is 1. C2 Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0. C0, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Source operand is an SNaN value, ∞, or unsupported format. #D Source is a denormal value.
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INSTRUCTION SET REFERENCE, A-M FDECSTP—Decrement Stack-Top Pointer Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 F6 FDECSTP Valid Valid Decrement TOP field in FPU status word. Description Subtracts one from the TOP field of the FPU status word (decrements the top-ofstack pointer). If the TOP field contains a 0, it is set to 7. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data registers and tag register are not affected.
PAGE 361
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. FDECSTP—Decrement Stack-Top Pointer Vol.
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INSTRUCTION SET REFERENCE, A-M FDIV/FDIVP/FIDIV—Divide Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D8 /6 FDIV m32fp Valid Valid Divide ST(0) by m32fp and store result in ST(0). DC /6 FDIV m64fp Valid Valid Divide ST(0) by m64fp and store result in ST(0). D8 F0+i FDIV ST(0), ST(i) Valid Valid Divide ST(0) by ST(i) and store result in ST(0). DC F8+i FDIV ST(i), ST(0) Valid Valid Divide ST(i) by ST(0) and store result in ST(i).
PAGE 363
INSTRUCTION SET REFERENCE, A-M If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of the appropriate sign is stored in the destination operand. The following table shows the results obtained when dividing various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-29.
PAGE 364
INSTRUCTION SET REFERENCE, A-M IF Instruction = FDIVP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Operand is an SNaN value or unsupported format. #D Source is a denormal value. #Z DEST / ±0, where DEST is not equal to ±0. #U Result is too small for destination format.
PAGE 365
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode.
PAGE 366
INSTRUCTION SET REFERENCE, A-M FDIVR/FDIVRP/FIDIVR—Reverse Divide Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D8 /7 FDIVR m32fp Valid Valid Divide m32fp by ST(0) and store result in ST(0). DC /7 FDIVR m64fp Valid Valid Divide m64fp by ST(0) and store result in ST(0). D8 F8+i FDIVR ST(0), ST(i) Valid Valid Divide ST(i) by ST(0) and store result in ST(0). DC F0+i FDIVR ST(i), ST(0) Valid Valid Divide ST(0) by ST(i) and store result in ST(i).
PAGE 367
INSTRUCTION SET REFERENCE, A-M The FIDIVR instructions convert an integer source operand to double extended-precision floating-point format before performing the division. If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of the appropriate sign is stored in the destination operand. The following table shows the results obtained when dividing various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-30.
PAGE 368
INSTRUCTION SET REFERENCE, A-M FI; DEST ←SRC / DEST; FI; IF Instruction = FDIVRP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Operand is an SNaN value or unsupported format. #D Source is a denormal value. ±∞ / ±∞; ±0 / ±0 #Z SRC / ±0, where SRC is not equal to ±0. #U Result is too small for destination format.
PAGE 369
INSTRUCTION SET REFERENCE, A-M #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
PAGE 370
INSTRUCTION SET REFERENCE, A-M FFREE—Free Floating-Point Register Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description DD C0+i FFREE ST(i) Valid Valid Sets tag for ST(i) to empty. Description Sets the tag in the FPU tag register associated with register ST(i) to empty (11B). The contents of ST(i) and the FPU stack-top pointer (TOP) are not affected. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
PAGE 371
INSTRUCTION SET REFERENCE, A-M FICOM/FICOMP—Compare Integer Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description DE /2 FICOM m16int Valid Valid Compare ST(0) with m16int. DA /2 FICOM m32int Valid Valid Compare ST(0) with m32int. DE /3 FICOMP m16int Valid Valid Compare ST(0) with m16int and pop stack register. DA /3 FICOMP m32int Valid Valid Compare ST(0) with m32int and pop stack register.
PAGE 372
INSTRUCTION SET REFERENCE, A-M ESAC; IF Instruction = FICOMP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred; otherwise, set to 0. C0, C2, C3 See table on previous page. Floating-Point Exceptions #IS Stack underflow occurred. #IA One or both operands are NaN values or have unsupported formats. #D One or both operands are denormal values.
PAGE 373
INSTRUCTION SET REFERENCE, A-M #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form.
PAGE 374
INSTRUCTION SET REFERENCE, A-M FILD—Load Integer Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description DF /0 FILD m16int Valid Valid Push m16int onto the FPU register stack. DB /0 FILD m32int Valid Valid Push m32int onto the FPU register stack. DF /5 FILD m64int Valid Valid Push m64int onto the FPU register stack. Description Converts the signed-integer source operand into double extended-precision floatingpoint format and pushes the value onto the FPU register stack.
PAGE 375
INSTRUCTION SET REFERENCE, A-M #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
PAGE 376
INSTRUCTION SET REFERENCE, A-M FINCSTP—Increment Stack-Top Pointer Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 F7 FINCSTP Valid Valid Increment the TOP field in the FPU status register. Description Adds one to the TOP field of the FPU status word (increments the top-of-stack pointer). If the TOP field contains a 7, it is set to 0. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data registers and tag register are not affected.
PAGE 377
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. FINCSTP—Increment Stack-Top Pointer Vol.
PAGE 378
INSTRUCTION SET REFERENCE, A-M FINIT/FNINIT—Initialize Floating-Point Unit Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 9B DB E3 FINIT Valid Valid Initialize FPU after checking for pending unmasked floating-point exceptions. DB E3 FNINIT* Valid Valid Initialize FPU without checking for pending unmasked floating-point exceptions. NOTES: * See IA-32 Architecture Compatibility section below.
PAGE 379
INSTRUCTION SET REFERENCE, A-M Operation FPUControlWord ←037FH; FPUStatusWord ←0; FPUTagWord ←FFFFH; FPUDataPointer ←0; FPUInstructionPointer ←0; FPULastInstructionOpcode ←0; FPU Flags Affected C0, C1, C2, C3 set to 0. Floating-Point Exceptions None. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode.
PAGE 380
INSTRUCTION SET REFERENCE, A-M FIST/FISTP—Store Integer Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description DF /2 FIST m16int Valid Valid Store ST(0) in m16int. DB /2 FIST m32int Valid Valid Store ST(0) in m32int. DF /3 FISTP m16int Valid Valid Store ST(0) in m16int and pop register stack. DB /3 FISTP m32int Valid Valid Store ST(0) in m32int and pop register stack. DF /7 FISTP m64int Valid Valid Store ST(0) in m64int and pop register stack.
PAGE 381
INSTRUCTION SET REFERENCE, A-M Table 3-32. FIST/FISTP Results (Contd.) ST(0) DEST NaN * NOTES: F Means finite floating-point value. I Means integer. * Indicates floating-point invalid-operation (#IA) exception. ** 0 or ±1, depending on the rounding mode. If the source value is a non-integral value, it is rounded to an integer value, according to the rounding mode specified by the RC field of the FPU control word.
PAGE 382
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
PAGE 383
INSTRUCTION SET REFERENCE, A-M #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. FIST/FISTP—Store Integer Vol.
PAGE 384
INSTRUCTION SET REFERENCE, A-M FISTTP—Store Integer with Truncation Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description DF /1 FISTTP m16int Valid Valid Store ST(0) in m16int with truncation. DB /1 FISTTP m32int Valid Valid Store ST(0) in m32int with truncation. DD /1 FISTTP m64int Valid Valid Store ST(0) in m64int with truncation.
PAGE 385
INSTRUCTION SET REFERENCE, A-M Numeric Exceptions Invalid, Stack Invalid (stack underflow), Precision. Protected Mode Exceptions #GP(0) If the destination is in a nonwritable segment. For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #NM If CR0.EM[bit 2] = 1.
PAGE 386
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. If the LOCK prefix is used. 3-340 Vol.
PAGE 387
INSTRUCTION SET REFERENCE, A-M FLD—Load Floating Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 /0 FLD m32fp Valid Valid Push m32fp onto the FPU register stack. DD /0 FLD m64fp Valid Valid Push m64fp onto the FPU register stack. DB /5 FLD m80fp Valid Valid Push m80fp onto the FPU register stack. D9 C0+i FLD ST(i) Valid Valid Push ST(i) onto the FPU register stack. Description Pushes the source operand onto the FPU register stack.
PAGE 388
INSTRUCTION SET REFERENCE, A-M #IA Source operand is an SNaN. Does not occur if the source operand is in double extended-precision floating-point format (FLD m80fp or FLD ST(i)). #D Source operand is a denormal value. Does not occur if the source operand is in double extended-precision floating-point format. Protected Mode Exceptions #GP(0) If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
PAGE 389
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant Opcode* Instruction 64-Bit Mode Compat/ Leg Mode Description D9 E8 FLD1 Valid Valid Push +1.0 onto the FPU register stack. D9 E9 FLDL2T Valid Valid Push log210 onto the FPU register stack. D9 EA FLDL2E Valid Valid Push log2e onto the FPU register stack. D9 EB FLDPI Valid Valid Push π onto the FPU register stack. D9 EC FLDLG2 Valid Valid Push log102 onto the FPU register stack.
PAGE 391
INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS Stack overflow occurred. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M FLDCW—Load x87 FPU Control Word Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 /5 FLDCW m2byte Valid Valid Load FPU control word from m2byte. Description Loads the 16-bit source operand into the FPU control word. The source operand is a memory location. This instruction is typically used to establish or change the FPU’s mode of operation.
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INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M FLDENV—Load x87 FPU Environment Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 /4 FLDENV m14/28byte Valid Valid Load FPU environment from m14byte or m28byte. Description Loads the complete x87 FPU operating environment from memory into the FPU registers. The source operand specifies the first byte of the operating-environment data in memory. This data is typically written to the specified memory location by a FSTENV or FNSTENV instruction.
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INSTRUCTION SET REFERENCE, A-M FPU Flags Affected The C0, C1, C2, C3 flags are loaded. Floating-Point Exceptions None; however, if an unmasked exception is loaded in the status word, it is generated upon execution of the next “waiting” floating-point instruction. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.
PAGE 396
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
PAGE 397
INSTRUCTION SET REFERENCE, A-M FMUL/FMULP/FIMUL—Multiply Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D8 /1 FMUL m32fp Valid Valid Multiply ST(0) by m32fp and store result in ST(0). DC /1 FMUL m64fp Valid Valid Multiply ST(0) by m64fp and store result in ST(0). D8 C8+i FMUL ST(0), ST(i) Valid Valid Multiply ST(0) by ST(i) and store result in ST(0). DC C8+i FMUL ST(i), ST(0) Valid Valid Multiply ST(i) by ST(0) and store result in ST(i).
PAGE 398
INSTRUCTION SET REFERENCE, A-M The FIMUL instructions convert an integer source operand to double extendedprecision floating-point format before performing the multiplication. The sign of the result is always the exclusive-OR of the source signs, even if one or more of the values being multiplied is 0 or ∞. When the source operand is an integer 0, it is treated as a +0.
PAGE 399
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS #IA Stack underflow occurred. Operand is an SNaN value or unsupported format. One operand is ±0 and the other is ±∞. #D Source operand is a denormal value. #U Result is too small for destination format. #O Result is too large for destination format.
PAGE 400
INSTRUCTION SET REFERENCE, A-M #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
PAGE 401
INSTRUCTION SET REFERENCE, A-M FNOP—No Operation Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 D0 FNOP Valid Valid No operation is performed. Description Performs no FPU operation. This instruction takes up space in the instruction stream but does not affect the FPU or machine context, except the EIP register. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. FPU Flags Affected C0, C1, C2, C3 undefined. Floating-Point Exceptions None.
PAGE 402
INSTRUCTION SET REFERENCE, A-M FPATAN—Partial Arctangent Opcode* Instruction 64-Bit Mode Compat/ Leg Mode Description D9 F3 FPATAN Valid Valid Replace ST(1) with arctan(ST(1)/ ST(0)) and pop the register stack. NOTES: * See IA-32 Architecture Compatibility section below. Description Computes the arctangent of the source operand in register ST(1) divided by the source operand in register ST(0), stores the result in ST(1), and pops the FPU register stack.
PAGE 403
INSTRUCTION SET REFERENCE, A-M Table 3-35. FPATAN Results ST(0) ST(1) -∞ −F −0 +0 +F +∞ -∞ −3π/ 4* −π/2 −π/2 −π/2 −π/2 −π/4* NaN −F -p −π to −π/ 2 −π/2 −π/2 −π/ 2 to −0 -0 NaN −0 -p -p -p* −0* −0 −0 NaN +0 +p +p +π* +0* +0 +0 NaN +F +p +π to +π/ 2 +π/ 2 +π/ 2 +π/ 2 to +0 +0 NaN +∞ +3π/ 4* +π/ 2 +π/ 2 +π/ 2 +π/ 2 +π/4* NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NOTES: F Means finite floating-point value.
PAGE 404
INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS Stack underflow occurred. #IA Source operand is an SNaN value or unsupported format. #D Source operand is a denormal value. #U Result is too small for destination format. #P Value cannot be represented exactly in destination format. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used.
PAGE 405
INSTRUCTION SET REFERENCE, A-M FPREM—Partial Remainder Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 F8 FPREM Valid Valid Replace ST(0) with the remainder obtained from dividing ST(0) by ST(1). Description Computes the remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the ST(1) register (the divisor or modulus), and stores the result in ST(0).
PAGE 406
INSTRUCTION SET REFERENCE, A-M The FPREM instruction does not compute the remainder specified in IEEE Std 754. The IEEE specified remainder can be computed with the FPREM1 instruction. The FPREM instruction is provided for compatibility with the Intel 8087 and Intel287 math coprocessors. The FPREM instruction gets its name “partial remainder” because of the way it computes the remainder. This instruction arrives at a remainder through iterative subtraction.
PAGE 407
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C0 Set to bit 2 (Q2) of the quotient. C1 Set to 0 if stack underflow occurred; otherwise, set to least significant bit of quotient (Q0). C2 Set to 0 if reduction complete; set to 1 if incomplete. C3 Set to bit 1 (Q1) of the quotient. Floating-Point Exceptions #IS Stack underflow occurred. #IA Source operand is an SNaN value, modulus is 0, dividend is ∞, or unsupported format. #D Source operand is a denormal value.
PAGE 408
INSTRUCTION SET REFERENCE, A-M FPREM1—Partial Remainder Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 F5 FPREM1 Valid Valid Replace ST(0) with the IEEE remainder obtained from dividing ST(0) by ST(1). Description Computes the IEEE remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the ST(1) register (the divisor or modulus), and stores the result in ST(0).
PAGE 409
INSTRUCTION SET REFERENCE, A-M The FPREM1 instruction computes the remainder specified in IEEE Standard 754. This instruction operates differently from the FPREM instruction in the way that it rounds the quotient of ST(0) divided by ST(1) to an integer (see the “Operation” section below). Like the FPREM instruction, FPREM1 computes the remainder through iterative subtraction, but can reduce the exponent of ST(0) by no more than 63 in one execution of the instruction.
PAGE 410
INSTRUCTION SET REFERENCE, A-M C2 Set to 0 if reduction complete; set to 1 if incomplete. C3 Set to bit 1 (Q1) of the quotient. Floating-Point Exceptions #IS Stack underflow occurred. #IA Source operand is an SNaN value, modulus (divisor) is 0, dividend is ∞, or unsupported format. #D Source operand is a denormal value. #U Result is too small for destination format. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception.
PAGE 411
INSTRUCTION SET REFERENCE, A-M FPTAN—Partial Tangent Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 F2 FPTAN Valid Valid Replace ST(0) with its tangent and push 1 onto the FPU stack. Description Computes the tangent of the source operand in register ST(0), stores the result in ST(0), and pushes a 1.0 onto the FPU register stack. The source operand must be given in radians and must be less than ±263.
PAGE 412
INSTRUCTION SET REFERENCE, A-M This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation IF ST(0) < 263 THEN C2 ←0; ST(0) ←tan(ST(0)); TOP ←TOP −1; ST(0) ←1.0; ELSE (* Source operand is out-of-range *) C2 ←1; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred. Set if result was rounded up; cleared otherwise. C2 Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0. C0, C3 Undefined.
PAGE 413
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. FPTAN—Partial Tangent Vol.
PAGE 414
INSTRUCTION SET REFERENCE, A-M FRNDINT—Round to Integer Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 FC FRNDINT Valid Valid Round ST(0) to an integer. Description Rounds the source value in the ST(0) register to the nearest integral value, depending on the current rounding mode (setting of the RC field of the FPU control word), and stores the result in ST(0). If the source value is ∞, the value is not changed.
PAGE 415
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. FRNDINT—Round to Integer Vol.
PAGE 416
INSTRUCTION SET REFERENCE, A-M FRSTOR—Restore x87 FPU State Opcode Instruction 64-Bit Mode DD /4 FRSTOR m94/108byte Valid Compat/ Leg Mode Description Valid Load FPU state from m94byte or m108byte. Description Loads the FPU state (operating environment and register stack) from the memory area specified with the source operand. This state data is typically written to the specified memory location by a previous FSAVE/FNSAVE instruction.
PAGE 417
INSTRUCTION SET REFERENCE, A-M ST(7) ←SRC[ST(7)]; FPU Flags Affected The C0, C1, C2, C3 flags are loaded. Floating-Point Exceptions None; however, this operation might unmask an existing exception that has been detected but not generated, because it was masked. Here, the exception is generated at the completion of the instruction. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
PAGE 418
INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
PAGE 419
INSTRUCTION SET REFERENCE, A-M FSAVE/FNSAVE—Store x87 FPU State Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 9B DD /6 FSAVE m94/108byte Valid Valid Store FPU state to m94byte or m108byte after checking for pending unmasked floatingpoint exceptions. Then reinitialize the FPU. DD /6 FNSAVE* m94/108byte Valid Valid Store FPU environment to m94byte or m108byte without checking for pending unmasked floating-point exceptions. Then re-initialize the FPU.
PAGE 420
INSTRUCTION SET REFERENCE, A-M instructions separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. IA-32 Architecture Compatibility For Intel math coprocessors and FPUs prior to the Intel Pentium processor, an FWAIT instruction should be executed before attempting to read from the memory image stored with a prior FSAVE/FNSAVE instruction.
PAGE 421
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected The C0, C1, C2, and C3 flags are saved and then cleared. Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.
PAGE 422
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
PAGE 423
INSTRUCTION SET REFERENCE, A-M FSCALE—Scale Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 FD FSCALE Valid Valid Scale ST(0) by ST(1). Description Truncates the value in the source operand (toward 0) to an integral value and adds that value to the exponent of the destination operand. The destination and source operands are floating-point values located in registers ST(0) and ST(1), respectively. This instruction provides rapid multiplication or division by integral powers of 2.
PAGE 424
INSTRUCTION SET REFERENCE, A-M before the FXTRACT operation was performed. The FSTP ST(1) instruction overwrites the exponent (extracted by the FXTRACT instruction) with the recreated value, which returns the stack to its original state with only one register [ST(0)] occupied. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation ST(0) ←ST(0) ∗ 2RoundTowardZero(ST(1)); FPU Flags Affected C1 Set to 0 if stack underflow occurred.
PAGE 425
INSTRUCTION SET REFERENCE, A-M FSIN—Sine Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 FE FSIN Valid Valid Replace ST(0) with its sine. Description Computes the sine of the source operand in register ST(0) and stores the result in ST(0). The source operand must be given in radians and must be within the range − 263 to +263. The following table shows the results obtained when taking the sine of various classes of numbers, assuming that underflow does not occur. Table 3-40.
PAGE 426
INSTRUCTION SET REFERENCE, A-M FI; ST(0) ←sin(ST(0)); ELSE (* Source operand out of range *) C2 ←1; FPU Flags Affected C1 Set to 0 if stack underflow occurred. C2 Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0. C0, C3 Undefined. Set if result was rounded up; cleared otherwise. Floating-Point Exceptions #IS Stack underflow occurred. #IA Source operand is an SNaN value, ∞, or unsupported format. #D Source operand is a denormal value.
PAGE 427
INSTRUCTION SET REFERENCE, A-M FSINCOS—Sine and Cosine Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 FB FSINCOS Valid Valid Compute the sine and cosine of ST(0); replace ST(0) with the sine, and push the cosine onto the register stack. Description Computes both the sine and the cosine of the source operand in register ST(0), stores the sine in ST(0), and pushes the cosine onto the top of the FPU register stack.
PAGE 428
INSTRUCTION SET REFERENCE, A-M Operation IF ST(0) < 263 THEN C2 ←0; TEMP ←cosine(ST(0)); ST(0) ←sine(ST(0)); TOP ←TOP −1; ST(0) ←TEMP; ELSE (* Source operand out of range *) C2 ←1; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred; set to 1 of stack overflow occurs. C2 Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0. C0, C3 Undefined. Set if result was rounded up; cleared otherwise. Floating-Point Exceptions #IS Stack underflow or overflow occurred.
PAGE 429
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. FSINCOS—Sine and Cosine Vol.
PAGE 430
INSTRUCTION SET REFERENCE, A-M FSQRT—Square Root Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 FA FSQRT Valid Valid Computes square root of ST(0) and stores the result in ST(0). Description Computes the square root of the source value in the ST(0) register and stores the result in ST(0). The following table shows the results obtained when taking the square root of various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-42.
PAGE 431
INSTRUCTION SET REFERENCE, A-M Source operand is a negative value (except for −0). #D Source operand is a denormal value. #P Value cannot be represented exactly in destination format. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode.
PAGE 432
INSTRUCTION SET REFERENCE, A-M FST/FSTP—Store Floating Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 /2 FST m32fp Valid Valid Copy ST(0) to m32fp. DD /2 FST m64fp Valid Valid Copy ST(0) to m64fp. DD D0+i FST ST(i) Valid Valid Copy ST(0) to ST(i). D9 /3 FSTP m32fp Valid Valid Copy ST(0) to m32fp and pop register stack. DD /3 FSTP m64fp Valid Valid Copy ST(0) to m64fp and pop register stack.
PAGE 433
INSTRUCTION SET REFERENCE, A-M If the destination operand is a non-empty register, the invalid-operation exception is not generated. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation DEST ←ST(0); IF Instruction = FSTP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Indicates rounding direction of if the floating-point inexact exception (#P) is generated: 0 ←not roundup; 1 ←roundup. C0, C2, C3 Undefined.
PAGE 434
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
PAGE 435
INSTRUCTION SET REFERENCE, A-M FSTCW/FNSTCW—Store x87 FPU Control Word Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 9B D9 /7 FSTCW m2byte Valid Valid Store FPU control word to m2byte after checking for pending unmasked floating-point exceptions. D9 /7 FNSTCW* m2byte Valid Valid Store FPU control word to m2byte without checking for pending unmasked floating-point exceptions. NOTES: * See IA-32 Architecture Compatibility section below.
PAGE 436
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
PAGE 437
INSTRUCTION SET REFERENCE, A-M #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. FSTCW/FNSTCW—Store x87 FPU Control Word Vol.
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INSTRUCTION SET REFERENCE, A-M FSTENV/FNSTENV—Store x87 FPU Environment Opcode Instruction 9B D9 /6 D9 /6 64-Bit Mode Compat/ Leg Mode Description FSTENV m14/28byte Valid Valid Store FPU environment to m14byte or m28byte after checking for pending unmasked floating-point exceptions. Then mask all floatingpoint exceptions. FNSTENV* m14/28byte Valid Store FPU environment to m14byte or m28byte without checking for pending unmasked floating-point exceptions. Then mask all floatingpoint exceptions.
PAGE 439
INSTRUCTION SET REFERENCE, A-M IA-32 Architecture Compatibility When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNSTENV instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances.
PAGE 440
INSTRUCTION SET REFERENCE, A-M #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
PAGE 441
INSTRUCTION SET REFERENCE, A-M FSTSW/FNSTSW—Store x87 FPU Status Word Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 9B DD /7 FSTSW m2byte Valid Valid Store FPU status word at m2byte after checking for pending unmasked floatingpoint exceptions. 9B DF E0 FSTSW AX Valid Valid Store FPU status word in AX register after checking for pending unmasked floatingpoint exceptions.
PAGE 442
INSTRUCTION SET REFERENCE, A-M IA-32 Architecture Compatibility When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNSTSW instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances.
PAGE 443
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M FSUB/FSUBP/FISUB—Subtract Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D8 /4 FSUB m32fp Valid Valid Subtract m32fp from ST(0) and store result in ST(0). DC /4 FSUB m64fp Valid Valid Subtract m64fp from ST(0) and store result in ST(0). D8 E0+i FSUB ST(0), ST(i) Valid Valid Subtract ST(i) from ST(0) and store result in ST(0). DC E8+i FSUB ST(i), ST(0) Valid Valid Subtract ST(0) from ST(i) and store result in ST(i).
PAGE 445
INSTRUCTION SET REFERENCE, A-M The FISUB instructions convert an integer source operand to double extended-precision floating-point format before performing the subtraction. Table 3-43 shows the results obtained when subtracting various classes of numbers from one another, assuming that neither overflow nor underflow occurs. Here, the SRC value is subtracted from the DEST value (DEST −SRC = result).
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INSTRUCTION SET REFERENCE, A-M IF Instruction = FSUBP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Operand is an SNaN value or unsupported format. #D Source operand is a denormal value. #U Result is too small for destination format. #O Result is too large for destination format.
PAGE 447
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode.
PAGE 448
INSTRUCTION SET REFERENCE, A-M FSUBR/FSUBRP/FISUBR—Reverse Subtract Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D8 /5 FSUBR m32fp Valid Valid Subtract ST(0) from m32fp and store result in ST(0). DC /5 FSUBR m64fp Valid Valid Subtract ST(0) from m64fp and store result in ST(0). D8 E8+i FSUBR ST(0), ST(i) Valid Valid Subtract ST(0) from ST(i) and store result in ST(0). DC E0+i FSUBR ST(i), ST(0) Valid Valid Subtract ST(i) from ST(0) and store result in ST(i).
PAGE 449
INSTRUCTION SET REFERENCE, A-M the register stack being popped. In some assemblers, the mnemonic for this instruction is FSUBR rather than FSUBRP. The FISUBR instructions convert an integer source operand to double extendedprecision floating-point format before performing the subtraction. The following table shows the results obtained when subtracting various classes of numbers from one another, assuming that neither overflow nor underflow occurs.
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INSTRUCTION SET REFERENCE, A-M IF Instruction = FSUBRP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Operand is an SNaN value or unsupported format. #D Source operand is a denormal value. #U Result is too small for destination format. #O Result is too large for destination format.
PAGE 451
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M FTST—TEST Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 E4 FTST Valid Valid Compare ST(0) with 0.0. Description Compares the value in the ST(0) register with 0.0 and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (see table below). Table 3-45. FTST Results Condition C3 C2 C0 ST(0) > 0.0 0 0 0 ST(0) < 0.0 0 0 1 ST(0) = 0.
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INSTRUCTION SET REFERENCE, A-M #IA The source operand is a NaN value or is in an unsupported format. #D The source operand is a denormal value. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description DD E0+i FUCOM ST(i) Valid Valid Compare ST(0) with ST(i). DD E1 FUCOM Valid Valid Compare ST(0) with ST(1). DD E8+i FUCOMP ST(i) Valid Valid Compare ST(0) with ST(i) and pop register stack. DD E9 FUCOMP Valid Valid Compare ST(0) with ST(1) and pop register stack.
PAGE 455
INSTRUCTION SET REFERENCE, A-M The FUCOMP instruction pops the register stack following the comparison operation and the FUCOMPP instruction pops the register stack twice following the comparison operation. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
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INSTRUCTION SET REFERENCE, A-M #IA One or both operands are SNaN values or have unsupported formats. Detection of a QNaN value in and of itself does not raise an invalid-operand exception. #D One or both operands are denormal values. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M FXAM—ExamineModR/M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 E5 FXAM Valid Valid Classify value or number in ST(0). Description Examines the contents of the ST(0) register and sets the condition code flags C0, C2, and C3 in the FPU status word to indicate the class of value or number in the register (see the table below). Table 3-47. FXAM Results .
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INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 Sign of value in ST(0). C0, C2, C3 See Table 3-47. Floating-Point Exceptions None. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M FXCH—Exchange Register Contents Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 C8+i FXCH ST(i) Valid Valid Exchange the contents of ST(0) and ST(i). D9 C9 FXCH Valid Valid Exchange the contents of ST(0) and ST(1). Description Exchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and ST(1) are exchanged.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. 3-414 Vol.
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INSTRUCTION SET REFERENCE, A-M FXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR State Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F AE /1 FXRSTOR m512byte Valid Valid Restore the x87 FPU, MMX, XMM, and MXCSR register state from m512byte. Description Reloads the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image specified in the source operand.
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INSTRUCTION SET REFERENCE, A-M x87 FPU and SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See alignment check exception [#AC] below.) For an attempt to set reserved bits in MXCSR. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.
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INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. #AC For unaligned memory reference. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form.
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INSTRUCTION SET REFERENCE, A-M FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F AE /0 FXSAVE m512byte Valid Valid Save the x87 FPU, MMX, XMM, and MXCSR register state to m512byte. Description Saves the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location specified in the destination operand.
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INSTRUCTION SET REFERENCE, A-M Table 3-48. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR Memory Region (Contd.
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INSTRUCTION SET REFERENCE, A-M Table 3-49. Field Definitions Field Definition FCW x87 FPU Control Word (16 bits). See Figure 8-6 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for the layout of the x87 FPU control word. FSW x87 FPU Status Word (16 bits). See Figure 8-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for the layout of the x87 FPU status word. FTW x87 FPU Tag Word (8 bits).
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INSTRUCTION SET REFERENCE, A-M Table 3-49. Field Definitions (Contd.) Field Definition MXCSR MXCSR Register State (32 bits). See Figure 10-3 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for the layout of the MXCSR register. If the OSFXSR bit in control register CR4 is not set, the FXSAVE instruction may not save this register. This behavior is implementation dependent. MXCSR_ MASK MXCSR_MASK (32 bits).
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INSTRUCTION SET REFERENCE, A-M Here, a 1 is saved for any valid, zero, or special tag, and a 0 is saved for any empty tag. The operation of the FXSAVE instruction differs from that of the FSAVE instruction, the as follows: • FXSAVE instruction does not check for pending unmasked floating-point exceptions. (The FXSAVE operation in this regard is similar to the operation of the FNSAVE instruction).
PAGE 469
INSTRUCTION SET REFERENCE, A-M Table 3-50. Recreating FSAVE Format (Contd.) Exponent all 1’s Exponent all 0’s Fraction all 0’s J and M bits FTW valid bit 1 0 1 00 1 Special 10 1 0 1 10 1 Special 10 0 Empty 11 For all legal combinations above. x87 FTW The J-bit is defined to be the 1-bit binary integer to the left of the decimal place in the significand. The M-bit is defined to be the most significant bit of the fractional portion of the significand (i.e.
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INSTRUCTION SET REFERENCE, A-M Table 3-51. Layout of the 64-bit-mode FXSAVE Map with Promoted OperandSize (Contd.) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XMM2 192 XMM3 208 XMM4 224 XMM5 240 XMM6 256 XMM7 272 XMM8 288 XMM9 304 XMM10 320 XMM11 336 XMM12 352 XMM13 368 XMM14 384 XMM15 400 Reserved 416 Reserved 432 Reserved 448 Reserved 464 Reserved 480 Reserved 496 Table 3-52.
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INSTRUCTION SET REFERENCE, A-M Table 3-52. Layout of the 64-bit-mode FXSAVE Map with Default OperandSize (Contd.
PAGE 472
INSTRUCTION SET REFERENCE, A-M THEN DEST ←Save64BitPromotedFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR); ELSE DEST ←Save64BitDefaultFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR); FI; FI; ELSE DEST ←SaveLegacyFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR); Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See the description of the alignment check exception [#AC] below.
PAGE 473
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.FXSR[bit 24] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. #AC For unaligned memory reference. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form.
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INSTRUCTION SET REFERENCE, A-M Implementation Note The order in which the processor signals general-protection (#GP) and page-fault (#PF) exceptions when they both occur on an instruction boundary is given in Table 5-2 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B. This order vary for FXSAVE for different processor implementations. 3-428 Vol.
PAGE 475
INSTRUCTION SET REFERENCE, A-M FXTRACT—Extract Exponent and Significand Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 F4 FXTRACT Valid Valid Separate value in ST(0) into exponent and significand, store exponent in ST(0), and push the significand onto the register stack. Description Separates the source value in the ST(0) register into its exponent and significand, stores the exponent in ST(0), and pushes the significand onto the register stack.
PAGE 476
INSTRUCTION SET REFERENCE, A-M #IA Source operand is an SNaN value or unsupported format. #Z ST(0) operand is ±0. #D Source operand is a denormal value. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M FYL2X—Compute y ∗ log2x Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 F1 FYL2X Valid Valid Replace ST(1) with (ST(1) ∗ log2ST(0)) and pop the register stack. Description Computes (ST(1) ∗ log2 (ST(0))), stores the result in resister ST(1), and pops the FPU register stack. The source operand in ST(0) must be a non-zero positive number.
PAGE 478
INSTRUCTION SET REFERENCE, A-M Operation ST(1) ←ST(1) ∗ log2ST(0); PopRegisterStack; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Either operand is an SNaN or unsupported format. Source operand in register ST(0) is a negative finite value (not −0). #Z Source operand in register ST(0) is ±0. #D Source operand is a denormal value.
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INSTRUCTION SET REFERENCE, A-M FYL2XP1—Compute y ∗ log2(x +1) Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description D9 F9 FYL2XP1 Valid Valid Replace ST(1) with ST(1) ∗ log2(ST(0) + 1.0) and pop the register stack. Description Computes (ST(1) ∗ log2(ST(0) +1.0)), stores the result in register ST(1), and pops the FPU register stack. The source operand in ST(0) must be in the range: – ( 1 – 2 ⁄ 2 ) )to ( 1 – 2 ⁄ 2 ) The source operand in ST(1) can range from −∞ to +∞.
PAGE 480
INSTRUCTION SET REFERENCE, A-M equation is used to calculate the scale factor for a particular logarithm base, where n is the logarithm base desired for the result of the FYL2XP1 instruction: scale factor ←logn 2 This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation ST(1) ←ST(1) ∗ log2(ST(0) +1.0); PopRegisterStack; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined.
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INSTRUCTION SET REFERENCE, A-M HADDPD—Packed Double-FP Horizontal Add Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 7C /r HADDPD xmm1, xmm2/m128 Valid Valid Horizontal add packed doubleprecision floating-point values from xmm2/m128 to xmm1. Description Adds the double-precision floating-point values in the high and low quadwords of the destination operand and stores the result in the low quadword of the destination operand.
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INSTRUCTION SET REFERENCE, A-M Operation xmm1[63:0] = xmm1[63:0] + xmm1[127:64]; xmm1[127:64] = xmm2/m128[63:0] + xmm2/m128[127:64]; Intel C/C++Compiler Intrinsic Equivalent HADDPD __m128d _mm_hadd_pd(__m128d a, __m128d b) Exceptions When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. Numeric Exceptions Overflow, Underflow, Invalid, Precision, Denormal.
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INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID feature flag SSE3 is 0. If the LOCK prefix is used. 3-438 Vol.
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INSTRUCTION SET REFERENCE, A-M HADDPS—Packed Single-FP Horizontal Add Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 7C /r HADDPS xmm1, xmm2/m128 Valid Valid Horizontal add packed singleprecision floating-point values from xmm2/m128 to xmm1. Description Adds the single-precision floating-point values in the first and second dwords of the destination operand and stores the result in the first dword of the destination operand.
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INSTRUCTION SET REFERENCE, A-M In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
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INSTRUCTION SET REFERENCE, A-M Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1. #XM For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0.
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INSTRUCTION SET REFERENCE, A-M #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID feature flag SSE3 is 0. If the LOCK prefix is used. 3-442 Vol.
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INSTRUCTION SET REFERENCE, A-M HLT—Halt Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F4 HLT Valid Valid Halt Description Stops instruction execution and places the processor in a HALT state. An enabled interrupt (including NMI and SMI), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal will resume execution.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. 3-444 Vol.
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INSTRUCTION SET REFERENCE, A-M HSUBPD—Packed Double-FP Horizontal Subtract Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 7D /r HSUBPD xmm1, xmm2/m128 Valid Valid Horizontal subtract packed doubleprecision floating-point values from xmm2/m128 to xmm1. Description The HSUBPD instruction subtracts horizontally the packed DP FP numbers of both operands.
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INSTRUCTION SET REFERENCE, A-M Operation xmm1[63:0] = xmm1[63:0] −xmm1[127:64]; xmm1[127:64] = xmm2/m128[63:0] −xmm2/m128[127:64]; Intel C/C++Compiler Intrinsic Equivalent HSUBPD __m128d _mm_hsub_pd(__m128d a, __m128d b) Exceptions When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. Numeric Exceptions Overflow, Underflow, Invalid, Precision, Denormal.
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INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M If CPUID feature flag SSE3 is 0. If the LOCK prefix is used. 3-448 Vol.
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INSTRUCTION SET REFERENCE, A-M HSUBPS—Packed Single-FP Horizontal Subtract Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 7D /r HSUBPS xmm1, xmm2/m128 Valid Valid Horizontal subtract packed singleprecision floating-point values from xmm2/m128 to xmm1. Description Subtracts the single-precision floating-point value in the second dword of the destination operand from the first dword of the destination operand and stores the result in the first dword of the destination operand.
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INSTRUCTION SET REFERENCE, A-M +68%36 [PP [PP P > @ > @ > @ > @ [PP P > @ > @ > @ > @ [PP [PP P > @ [PP P > @ [PP P > @ [PP P > @ [PP > @ [PP > @ [PP > @ [PP > @ > @ > @ > @ 5(68/7 [PP > @ 20 Figure 3-13. HSUBPS—Packed Single-FP Horizontal Subtract In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
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INSTRUCTION SET REFERENCE, A-M Numeric Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM For an unmasked Streaming SIMD Extensions numeric exception (CR4.
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INSTRUCTION SET REFERENCE, A-M #NM If CR0.TS[bit 3] = 1. #XM For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If the LOCK prefix is used. If CPUID.01H:ECX.SSE3[bit 0] = 0. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M IDIV—Signed Divide Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F6 /7 IDIV r/m8 Valid Valid Signed divide AX by r/m8, with result stored in: AL ←Quotient, AH ← Remainder. REX + F6 /7 IDIV r/m8* Valid N.E. Signed divide AX by r/m8, with result stored in AL ←Quotient, AH ← Remainder. F7 /7 IDIV r/m16 Valid Valid Signed divide DX:AX by r/m16, with result stored in AX ←Quotient, DX ← Remainder.
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INSTRUCTION SET REFERENCE, A-M Table 3-55.
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INSTRUCTION SET REFERENCE, A-M THEN #DE; (* Divide error *) ELSE EAX ←temp; EDX ←EDXE:AX SignedModulus SRC; FI; FI; ELSE IF OperandSize = 64 (* Doublequadword/quadword operation *) temp ←RDX:RAX / SRC; (* Signed division *) IF (temp > 7FFFFFFFFFFFH) or (temp < 8000000000000000H) (* If a positive result is greater than 7FFFFFFFFFFFH or a negative result is less than 8000000000000000H *) THEN #DE; (* Divide error *) ELSE RAX ←temp; RDX ←RDE:RAX SignedModulus SRC; FI; FI; FI; Flags Affected The CF, OF, SF,
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INSTRUCTION SET REFERENCE, A-M #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #DE If the source operand (divisor) is 0. The signed result (quotient) is too large for the destination. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, A-M IMUL—Signed Multiply Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F6 /5 IMUL r/m8* Valid Valid AX←AL ∗ r/m byte. F7 /5 IMUL r/m16 Valid Valid DX:AX ←AX ∗ r/m word. F7 /5 IMUL r/m32 Valid Valid EDX:EAX ←EAX ∗ r/m32. REX.W + F7 /5 IMUL r/m64 Valid N.E. RDX:RAX ←RAX ∗ r/m64. 0F AF /r IMUL r16, r/m16 Valid Valid word register ←word register ∗ r/m16.
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INSTRUCTION SET REFERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 69 /r id IMUL r32, imm32 Valid Valid doubleword register ←r/m32 ∗ immediate doubleword. REX.W + 69 /r id IMUL r64, imm32 Valid N.E. Quadword register ←r/m64 ∗ immediate doubleword. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Description Performs a signed multiplication of two operands.
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INSTRUCTION SET REFERENCE, A-M signed or unsigned. The CF and OF flags, however, cannot be used to determine if the upper half of the result is non-zero. In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. Use of REX.W modifies the three forms of the instruction as follows.
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INSTRUCTION SET REFERENCE, A-M ELSE IF (NumberOfOperands = 2) THEN temp ←DEST ∗ SRC (* Signed multiplication; temp is double DEST size *) DEST ←DEST ∗ SRC (* Signed multiplication *) IF temp ≠ DEST THEN CF ←1; OF ←1; ELSE CF ←0; OF ←0; FI; ELSE (* NumberOfOperands = 3 *) DEST ←SRC1 ∗ SRC2 (* Signed multiplication *) temp ←SRC1 ∗ SRC2 (* Signed multiplication; temp is double SRC1 size *) IF temp ≠ DEST THEN CF ←1; OF ←1; ELSE CF ←0; OF ←0; FI; FI; FI; Flags Affected For the one operand form of the instruct
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INSTRUCTION SET REFERENCE, A-M #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M IN—Input from Port Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description E4 ib IN AL, imm8 Valid Valid Input byte from imm8 I/O port address into AL. E5 ib IN AX, imm8 Valid Valid Input word from imm8 I/O port address into AX. E5 ib IN EAX, imm8 Valid Valid Input dword from imm8 I/O port address into EAX. EC IN AL,DX Valid Valid Input byte from I/O port in DX into AL. ED IN AX,DX Valid Valid Input word from I/O port in DX into AX.
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INSTRUCTION SET REFERENCE, A-M FI; DEST ←SRC; (* Read from selected I/O port *) FI; ELSE (Real Mode or Protected Mode with CPL ≤IOPL *) DEST ←SRC; (* Read from selected I/O port *) Flags Affected None. Protected Mode Exceptions #GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the corresponding I/O permission bits in TSS for the I/O port being accessed is 1. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M INC—Increment by 1 Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description FE /0 INC r/m8 Valid Valid Increment r/m byte by 1. REX + FE /0 INC r/m8* Valid N.E. Increment r/m byte by 1. FF /0 INC r/m16 Valid Valid Increment r/m word by 1. FF /0 INC r/m32 Valid Valid Increment r/m doubleword by 1. INC r/m64 Valid N.E. Increment r/m quadword by 1. INC r16 N.E. Valid Increment word register by 1. INC r32 N.E.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULLsegment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory operand. 3-466 Vol.
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INSTRUCTION SET REFERENCE, A-M INS/INSB/INSW/INSD—Input from Port to String Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 6C INS m8, DX Valid Valid Input byte from I/O port specified in DX into memory location specified in ES:(E)DI or RDI.* 6D INS m16, DX Valid Valid Input word from I/O port specified in DX into memory location specified in ES:(E)DI or RDI.
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INSTRUCTION SET REFERENCE, A-M destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers, which must be loaded correctly before the INS instruction is executed. The no-operands form provides “short forms” of the byte, word, and doubleword versions of the INS instructions.
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INSTRUCTION SET REFERENCE, A-M IF (Byte transfer) THEN IF DF = 0 THEN (E)DI ←(E)DI +1; ELSE (E)DI ←(E)DI – 1; FI; ELSE IF (Word transfer) THEN IF DF = 0 THEN (E)DI ←(E)DI +2; ELSE (E)DI ←(E)DI – 2; FI; ELSE (* Doubleword transfer *) THEN IF DF = 0 THEN (E)DI ←(E)DI +4; ELSE (E)DI ←(E)DI – 4; FI; FI; FI; FI64-bit Mode: IF (Byte transfer) THEN IF DF = 0 THEN (E|R)DI ←(E|R)DI +1; ELSE (E|R)DI ←(E|R)DI – 1; FI; ELSE IF (Word transfer) THEN IF DF = 0 THEN (E)DI ←(E)DI +2; ELSE (E)DI ←(E)DI – 2; FI; ELSE (* Doub
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INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M INT n/INTO/INT 3—Call to Interrupt Procedure Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description CC INT 3 Valid Valid Interrupt 3—trap to debugger. CD ib INT imm8 Valid Valid Interrupt vector number specified by immediate byte. CE INTO Invalid Valid Interrupt 4—if overflow flag is 1.
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INSTRUCTION SET REFERENCE, A-M with the IRET instruction, which pops the EFLAGS information and return address from the stack. The interrupt vector number specifies an interrupt descriptor in the interrupt descriptor table (IDT); that is, it provides index into the IDT. The selected interrupt descriptor in turn contains a pointer to an interrupt or exception handler procedure. In protected mode, the IDT contains an array of 8-byte descriptors, each of which is an interrupt gate, trap gate, or task gate.
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INSTRUCTION SET REFERENCE, A-M When the processor is executing in virtual-8086 mode, the IOPL determines the action of the INT n instruction. If the IOPL is less than 3, the processor generates a #GP(selector) exception; if the IOPL is 3, the processor executes a protected mode interrupt to privilege level 0. The interrupt gate's DPL must be set to 3 and the target CPL of the interrupt handler procedure must be 0 to execute the protected mode interrupt to privilege level 0.
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INSTRUCTION SET REFERENCE, A-M CS ←IDT(Descriptor (vector_number ∗ 4), selector)); EIP ←IDT(Descriptor (vector_number ∗ 4), offset)); (* 16 bit offset AND 0000FFFFH *) END; PROTECTED-MODE: IF ((vector_number ∗ 8) +7) is not within IDT limits or selected IDT descriptor is not an interrupt-, trap-, or task-gate type THEN #GP((vector_number ∗ 8) +2 +EXT); FI; (* EXT is bit 0 in error code *) IF software interrupt (* Generated by INT n, INT 3, or INTO *) THEN IF gate descriptor DPL < CPL THEN #GP((vector_numbe
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INSTRUCTION SET REFERENCE, A-M or index not within GDT limits THEN #GP(TSS selector); FI; Access TSS descriptor in GDT; IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001) THEN #GP(TSS selector); FI; IF TSS not present THEN #NP(TSS selector); FI; SWITCH-TASKS (with nesting) to TSS; IF interrupt caused by fault with error code THEN IF stack limit does not allow push of error code THEN #SS(0); FI; Push(error code); FI; IF EIP not within code segment limit THEN #GP(0); FI; END; TR
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INSTRUCTION SET REFERENCE, A-M IF VM = 1 THEN #GP(new code segment selector); FI; IF code segment is conforming or code segment DPL = CPL THEN GOTO INTRA-PRIVILEGE-LEVEL-INTERRUPT; ELSE #GP(CodeSegmentSelector +EXT); (* PE = 1, interrupt or trap gate, nonconforming code segment, DPL > CPL *) FI; FI; END; INTER-PRIVILEGE-LEVEL-INTERRUPT: (* PE = 1, interrupt or trap gate, non-conforming code segment, DPL < CPL *) (* Check segment selector and descriptor for stack of new privilege level in current TSS *) IF
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INSTRUCTION SET REFERENCE, A-M or stack segment does not indicate writable data segment THEN #TS(SS selector +EXT); FI; IF stack segment not present THEN #SS(SS selector + EXT); FI; FI IF 32-bit gate THEN IF new stack does not have room for 24 bytes (error code pushed) or 20 bytes (no error code pushed) THEN #SS(segment selector +EXT); FI; FI ELSE IF 16-bit gate THEN IF new stack does not have room for 12 bytes (error code pushed) or 10 bytes (no error code pushed); THEN #SS(segment selector +EXT); FI; EL
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INSTRUCTION SET REFERENCE, A-M FI; IF 32-bit gate THEN Push(far pointer to old stack); (* Old SS and ESP, 3 words padded to 4 *) Push(EFLAGS); Push(far pointer to return instruction); (* Old CS and EIP, 3 words padded to 4 *) Push(ErrorCode); (* If needed, 4 bytes *) ELSE IF 16-bit gate THEN Push(far pointer to old stack); (* Old SS and SP, 2 words *) Push(EFLAGS(15-0]); Push(far pointer to return instruction); (* Old CS and IP, 2 words *) Push(ErrorCode); (* If needed, 2 bytes *) ELSE (* 64-bit gate *) Pu
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INSTRUCTION SET REFERENCE, A-M NewESP ←stack address; ELSE (* TSS is 16-bit *) TSSstackAddress ←(new code segment DPL ∗ 4) +2; IF (TSSstackAddress +4) > TSS limit THEN #TS(current TSS selector); FI; NewESP ←TSSstackAddress; NewSS ←TSSstackAddress +2; FI; IF segment selector is NULL THEN #TS(EXT); FI; IF segment selector index is not within its descriptor table limits or segment selector's RPL ≠ DPL of code segment THEN #TS(SS selector +EXT); FI; Access segment descriptor for stack segment in GDT or LDT; I
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INSTRUCTION SET REFERENCE, A-M TempSS ←SS; TempESP ←ESP; SS:ESP ←TSS(SS0:ESP0); (* Change to level 0 stack segment *) (* Following pushes are 16 bits for 16-bit gate and 32 bits for 32-bit gates; Segment selector pushes in 32-bit mode are padded to two words *) Push(GS); Push(FS); Push(DS); Push(ES); Push(TempSS); Push(TempESP); Push(TempEFlags); Push(CS); Push(EIP); GS ←0; (* Segment registers NULLified, invalid in protected mode *) FS ←0; DS ←0; ES ←0; CS ←Gate(CS); IF OperandSize = 32 THEN EIP ←Gate(ins
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INSTRUCTION SET REFERENCE, A-M IF instruction pointer not within code segment limit THEN #GP(0); FI; IF 32-bit gate THEN Push (EFLAGS); Push (far pointer to return instruction); (* 3 words padded to 4 *) CS:EIP ←Gate(CS:EIP); (* Segment descriptor information also loaded *) Push (ErrorCode); (* If any *) ELSE IF 16-bit gate THEN Push (FLAGS); Push (far pointer to return location); (* 2 words *) CS:IP ←Gate(CS:IP); (* Segment descriptor information also loaded *) Push (ErrorCode); (* If any *) ELSE (* 64-bi
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the instruction pointer in the IDT or in the interrupt-, trap-, or task gate is beyond the code segment limits. #GP(selector) If the segment selector in the interrupt-, trap-, or task gate is NULL. If an interrupt-, trap-, or task gate, code segment, or TSS segment selector index is outside its descriptor table limits. If the interrupt vector number is outside the IDT limits.
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INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the interrupt vector number is outside the IDT limits. #SS If stack limit violation on push. If pushing the return address, flags, or error code onto the stack exceeds the bounds of the stack segment. #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M If the stack segment for the TSS is not a writable data segment. If segment-selector index for stack segment is outside descriptor table limits. #PF(fault-code) If a page fault occurs. #BP If the INT 3 instruction is executed. #OF If the INTO instruction is executed and the OF flag is set. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode.
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INSTRUCTION SET REFERENCE, A-M #TS(selector) If an attempt to load RSP from the TSS causes an access to noncanonical space. #PF(fault-code) If a page fault occurs. #UD If the LOCK prefix is used. If the RSP from the TSS is outside descriptor table limits. INT n/INTO/INT 3—Call to Interrupt Procedure Vol.
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INSTRUCTION SET REFERENCE, A-M INVD—Invalidate Internal Caches Opcode* Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 08 INVD Valid Valid Flush internal caches; initiate flushing of external caches. NOTES: * See the IA-32 Architecture Compatibility section below. Description Invalidates (flushes) the processor’s internal caches and issues a special-function bus cycle that directs external caches to also flush themselves. Data held in internal caches is not written back to main memory.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the current privilege level is not 0. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #UD If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) The INVD instruction cannot be executed in virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. INVD—Invalidate Internal Caches Vol.
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INSTRUCTION SET REFERENCE, A-M INVLPG—Invalidate TLB Entry Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 01/7 INVLPG m Valid Valid Invalidate TLB Entry for page that contains m. NOTES: * See the IA-32 Architecture Compatibility section below. Description Invalidates (flushes) the translation lookaside buffer (TLB) entry specified with the source operand. The source operand is a memory address.
PAGE 535
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #UD Operand is a register. If the LOCK prefix is used. Virtual-8086 Mode Exceptions #GP(0) The INVLPG instruction cannot be executed at the virtual-8086 mode. 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0. #UD Operand is a register. If the LOCK prefix is used. INVLPG—Invalidate TLB Entry Vol.
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INSTRUCTION SET REFERENCE, A-M IRET/IRETD—Interrupt Return Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description CF IRET Valid Valid Interrupt return (16-bit operand size). CF IRETD Valid Valid Interrupt return (32-bit operand size). REX.W + CF IRETQ Valid N.E. Interrupt return (64-bit operand size).
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INSTRUCTION SET REFERENCE, A-M As with a real-address mode interrupt return, the IRET instruction pops the return instruction pointer, return code segment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted program or procedure. If the return is to another privilege level, the IRET instruction also pops the stack pointer and SS from the stack, before resuming program execution.
PAGE 538
INSTRUCTION SET REFERENCE, A-M EFLAGS ←(tempEFLAGS AND 257FD5H) OR (EFLAGS AND 1A0000H); ELSE (* OperandSize = 16 *) IF top 6 bytes of stack are not within stack limits THEN #SS; FI; EIP ←Pop(); (* 16-bit pop; clear upper 16 bits *) CS ←Pop(); (* 16-bit pop *) EFLAGS[15:0] ←Pop(); FI; END; PROTECTED-MODE: IF VM = 1 (* Virtual-8086 mode: PE = 1, VM = 1 *) THEN GOTO RETURN-FROM-VIRTUAL-8086-MODE; (* PE = 1, VM = 1 *) FI; IF NT = 1 THEN GOTO TASK-RETURN; (* PE = 1, VM = 0, NT = 1 *) FI; IF OperandSize = 32 T
PAGE 539
INSTRUCTION SET REFERENCE, A-M ELSE IF OperandSize = 32 THEN IF top 12 bytes of stack not within stack limits THEN #SS(0); FI; tempEIP ←Pop(); tempCS ←Pop(); tempEFLAGS ←Pop(); ELSE IF OperandSize = 16 THEN IF top 6 bytes of stack are not within stack limits THEN #SS(0); FI; tempEIP ←Pop(); tempCS ←Pop(); tempEFLAGS ←Pop(); tempEIP ←tempEIP AND FFFFH; tempEFLAGS ←tempEFLAGS AND FFFFH; FI; ELSE (* OperandSize = 64 *) THEN tempRIP ←Pop(); tempCS ←Pop(); tempEFLAGS ←Pop(); tempRSP ←Pop(); tempSS ←Pop(); FI; G
PAGE 540
INSTRUCTION SET REFERENCE, A-M THEN #GP(0); FI; EIP ←Pop(); EIP ←EIP AND 0000FFFFH; CS ←Pop(); (* 16-bit pop *) EFLAGS[15:0] ←Pop(); (* IOPL in EFLAGS not modified by pop *) FI; ELSE #GP(0); (* Trap to virtual-8086 monitor: PE FI; END; = 1, VM = 1, IOPL < 3 *) RETURN-TO-VIRTUAL-8086-MODE: (* Interrupted procedure was in virtual-8086 mode: PE = 1, CPL=0, VM IF top 24 bytes of stack are not within stack segment limits THEN #SS(0); FI; IF instruction pointer not within code segment limits THEN #GP(0); FI;
PAGE 541
INSTRUCTION SET REFERENCE, A-M IF EIP is not within code segment limit THEN #GP(0); FI; END; PROTECTED-MODE-RETURN: (* PE = 1 *) IF return code segment selector is NULL THEN GP(0); FI; IF return code segment selector addresses descriptor beyond descriptor table limit THEN GP(selector); FI; Read segment descriptor pointed to by the return code segment selector; IF return code segment descriptor is not a code segment THEN #GP(selector); FI; IF return code segment selector RPL < CPL THEN #GP(selector); FI; IF
PAGE 542
INSTRUCTION SET REFERENCE, A-M FI; END; EFLAGS(IOPL) ←tempEFLAGS; IF OperandSize = 32 or OperandSize = 64 THEN EFLAGS(VIF, VIP) ←tempEFLAGS; FI; RETURN-TO-OUTER-PRIVILEGE-LEVEL: IF OperandSize = 32 THEN IF top 8 bytes on stack are not within limits THEN #SS(0); FI; ELSE (* OperandSize = 16 *) IF top 4 bytes on stack are not within limits THEN #SS(0); FI; FI; Read return segment selector; IF stack segment selector is NULL THEN #GP(0); FI; IF return stack segment selector index is not within its descriptor
PAGE 543
INSTRUCTION SET REFERENCE, A-M IF CPL = 0 THEN EFLAGS(IOPL) ←tempEFLAGS; IF OperandSize = 32 THEN EFLAGS(VM, VIF, VIP) ←tempEFLAGS; FI; IF OperandSize = 64 THEN EFLAGS(VIF, VIP) ←tempEFLAGS; FI; FI; CPL ←RPL of the return code segment selector; FOR each of segment register (ES, FS, GS, and DS) DO IF segment register points to data or non-conforming code segment and CPL > segment descriptor DPL (* Stored in hidden part of segment register *) THEN (* Segment register invalid *) SegmentSelector ←0; (* NULL se
PAGE 544
INSTRUCTION SET REFERENCE, A-M Flags Affected All the flags and fields in the EFLAGS register are potentially modified, depending on the mode of operation of the processor. If performing a return from a nested task to a previous task, the EFLAGS register will be modified according to the EFLAGS image stored in the previous task’s TSS. Protected Mode Exceptions #GP(0) If the return code or stack segment selector is NULL. If the return instruction pointer is not within the return code segment limit.
PAGE 545
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If the return instruction pointer is not within the return code segment limit. IF IOPL not equal to 3. #PF(fault-code) If a page fault occurs. #SS(0) If the top bytes of stack are not within stack limits. #AC(0) If an unaligned memory reference occurs and alignment checking is enabled. #UD If the LOCK prefix is used. Compatibility Mode Exceptions #GP(0) If EFLAGS.NT[bit 14] = 1. Other exceptions same as in Protected Mode.
PAGE 546
INSTRUCTION SET REFERENCE, A-M If the stack segment selector RPL is not equal to the RPL of the return code segment selector. #SS(0) If an attempt to pop a value off the stack violates the SS limit. If an attempt to pop a value off the stack causes a non-canonical address to be referenced. #NP(selector) If the return code or stack segment is not present. #PF(fault-code) If a page fault occurs. #AC(0) If an unaligned memory reference occurs when the CPL is 3 and alignment checking is enabled.
PAGE 547
INSTRUCTION SET REFERENCE, A-M Jcc—Jump if Condition Is Met Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 77 cb JA rel8 Valid Valid Jump short if above (CF=0 and ZF=0). 73 cb JAE rel8 Valid Valid Jump short if above or equal (CF=0). 72 cb JB rel8 Valid Valid Jump short if below (CF=1). 76 cb JBE rel8 Valid Valid Jump short if below or equal (CF=1 or ZF=1). 72 cb JC rel8 Valid Valid Jump short if carry (CF=1). E3 cb JCXZ rel8 N.E.
PAGE 548
INSTRUCTION SET REFERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 75 cb JNZ rel8 Valid Valid Jump short if not zero (ZF=0). 70 cb JO rel8 Valid Valid Jump short if overflow (OF=1). 7A cb JP rel8 Valid Valid Jump short if parity (PF=1). 7A cb JPE rel8 Valid Valid Jump short if parity even (PF=1). 7B cb JPO rel8 Valid Valid Jump short if parity odd (PF=0). 78 cb JS rel8 Valid Valid Jump short if sign (SF=1).
PAGE 549
INSTRUCTION SET REFERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 8C cw JL rel16 N.S. Valid Jump near if less (SF≠ OF). Not supported in 64-bit mode. 0F 8C cd JL rel32 Valid Valid Jump near if less (SF≠ OF). 0F 8E cw JLE rel16 N.S. Valid Jump near if less or equal (ZF=1 or SF≠ OF). Not supported in 64-bit mode. 0F 8E cd JLE rel32 Valid Valid Jump near if less or equal (ZF=1 or SF≠ OF). 0F 86 cw JNA rel16 N.S.
PAGE 550
INSTRUCTION SET REFERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 8C cd JNGE rel32 Valid Valid Jump near if not greater or equal (SF≠ OF). 0F 8D cw JNL rel16 N.S. Valid Jump near if not less (SF=OF). Not supported in 64-bit mode. 0F 8D cd JNL rel32 Valid Valid Jump near if not less (SF=OF). 0F 8F cw JNLE rel16 N.S. Valid Jump near if not less or equal (ZF=0 and SF=OF). Not supported in 64-bit mode.
PAGE 551
INSTRUCTION SET REFERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 88 cd JS rel32 Valid Valid Jump near if sign (SF=1). 0F 84 cw JZ rel16 N.S. Valid Jump near if 0 (ZF=1). Not supported in 64-bit mode. 0F 84 cd JZ rel32 Valid Valid Jump near if 0 (ZF=1).
PAGE 552
INSTRUCTION SET REFERENCE, A-M checked is determined by the address-size attribute. These instructions are useful when used at the beginning of a loop that terminates with a conditional loop instruction (such as LOOPNE). They can be used to prevent an instruction sequence from entering a loop when RCX, ECX or CX is 0. This would cause the loop to execute 264, 232 or 64K times (not zero times).
PAGE 553
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #GP(0) If the memory address is in a non-canonical form. #UD If the LOCK prefix is used. Jcc—Jump if Condition Is Met Vol.
PAGE 554
INSTRUCTION SET REFERENCE, A-M JMP—Jump Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description EB cb JMP rel8 Valid Valid Jump short, RIP = RIP + 8-bit displacement sign extended to 64-bits E9 cw JMP rel16 N.S. Valid Jump near, relative, displacement relative to next instruction. Not supported in 64-bit mode. E9 cd JMP rel32 Valid Valid Jump near, relative, RIP = RIP + 32-bit displacement sign extended to 64-bits FF /4 JMP r/m16 N.S.
PAGE 555
INSTRUCTION SET REFERENCE, A-M • Short jump—A near jump where the jump range is limited to –128 to +127 from the current EIP value. • Far jump—A jump to an instruction located in a different segment than the current code segment but at the same privilege level, sometimes referred to as an intersegment jump. • Task switch—A jump to an instruction located in a different task.
PAGE 556
INSTRUCTION SET REFERENCE, A-M • A task switch. (The JMP instruction cannot be used to perform inter-privilege-level far jumps.) In protected mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access rights determine the type of jump to be performed.
PAGE 557
INSTRUCTION SET REFERENCE, A-M and save the previous task link information, allowing a return to the calling task with an IRET instruction. In 64-Bit Mode — The instruction’s operation size is fixed at 64 bits. If a selector points to a gate, then RIP equals the 64-bit displacement taken from gate; else RIP equals the zero-extended offset from the far pointer referenced in the instruction. See the summary chart at the beginning of this section for encoding data and limits.
PAGE 558
INSTRUCTION SET REFERENCE, A-M FI; IF far jump and (PE = 0 or (PE = 1 AND VM = 1)) (* Real-address or virtual-8086 mode *) THEN tempEIP ←DEST(Offset); (* DEST is ptr16:32 or [m16:32] *) IF tempEIP is beyond code segment limit THEN #GP(0); FI; CS ←DEST(segment selector); (* DEST is ptr16:32 or [m16:32] *) IF OperandSize = 32 THEN EIP ←tempEIP; (* DEST is ptr16:32 or [m16:32] *) ELSE (* OperandSize = 16 *) EIP ←tempEIP AND 0000FFFFH; (* Clear upper 16 bits *) FI; FI; IF far jump and (PE = 1 and VM = 0) (* IA
PAGE 559
INSTRUCTION SET REFERENCE, A-M THEN GP(new code segment selector); FI; IF DPL > CPL THEN #GP(segment selector); FI; IF segment not present THEN #NP(segment selector); FI; tempEIP ←DEST(Offset); IF OperandSize = 16 THEN tempEIP ←tempEIP AND 0000FFFFH; FI; IF (IA32_EFER.
PAGE 560
INSTRUCTION SET REFERENCE, A-M THEN #GP(0); FI; IF call gate code-segment selector index outside descriptor table limits THEN #GP(code segment selector); FI; Read code segment descriptor; IF code-segment segment descriptor does not indicate a code segment or code-segment segment descriptor is conforming and DPL > CPL or code-segment segment descriptor is non-conforming and DPL ≠ CPL THEN #GP(code segment selector); FI; IF IA32_EFER.
PAGE 561
INSTRUCTION SET REFERENCE, A-M or TSS DPL < TSS segment-selector RPL or TSS descriptor indicates TSS not available THEN #GP(TSS selector); FI; IF TSS is not present THEN #NP(TSS selector); FI; SWITCH-TASKS to TSS; IF EIP not within code segment limit THEN #GP(0); FI; END; Flags Affected All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur. Protected Mode Exceptions #GP(0) If offset in target operand, call gate, or TSS is beyond the code segment limits.
PAGE 562
INSTRUCTION SET REFERENCE, A-M If the segment selector for a TSS has its local/global bit set for local. If a TSS segment descriptor specifies that the TSS is busy or not available. #SS(0) If a memory operand effective address is outside the SS segment limit. #NP (selector) If the code segment being accessed is not present. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 563
INSTRUCTION SET REFERENCE, A-M If target offset in destination operand is non-canonical. If target offset in destination operand is beyond the new code segment limit. If the segment selector in the destination operand is NULL. If the code segment selector in the 64-bit gate is NULL. #GP(selector) If the code segment or 64-bit call gate is outside descriptor table limits. If the code segment or 64-bit call gate overlaps non-canonical space.
PAGE 564
INSTRUCTION SET REFERENCE, A-M LAHF—Load Status Flags into AH Register Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 9F LAHF Invalid* Valid Load: AH ←EFLAGS(SF:ZF:0:AF:0:PF:1:CF). NOTES: * Valid in specific steppings. See Description section. Description This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1. Operation IF 64-Bit Mode THEN IF CPUID.80000001H:ECX.
PAGE 565
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #UD If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0. If the LOCK prefix is used. LAHF—Load Status Flags into AH Register Vol.
PAGE 566
INSTRUCTION SET REFERENCE, A-M LAR—Load Access Rights Byte Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 02 /r LAR r16, r16/m16 Valid Valid r16 ←r16/m16 masked by FF00H. 0F 02 /r LAR r32, r32/m161 Valid Valid r32 ←r32/m16 masked by 00FxFF00H REX.W + 0F 02 /r LAR r64, r32/m161 Valid N.E. r64 ←r32/m16 masked by 00FxFF00H and zero extended NOTES: 1. For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are ignored.
PAGE 567
INSTRUCTION SET REFERENCE, A-M • If the segment is not a conforming code segment, it checks that the specified segment descriptor is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment selector). If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no access rights are loaded in the destination operand.
PAGE 568
INSTRUCTION SET REFERENCE, A-M ZF = 0; ELSE IF SegmentDescriptor(Type) ≠ conforming code segment and (CPL > DPL) or (RPL > DPL) or segment type is not valid for instruction THEN ZF ←0 ELSE TEMP ←Read segment descriptor ; IF OperandSize = 64 THEN DEST ←(ACCESSRIGHTWORD(TEMP) AND 00000000_00FxFF00H); ELSE (* OperandSize = 32*) DEST ←(ACCESSRIGHTWORD(TEMP) AND 00FxFF00H); ELSE (* OperandSize = 16 *) DEST ←(ACCESSRIGHTWORD(TEMP) AND FF00H); FI; FI; FI: Flags Affected The ZF flag is set to 1 if the access righ
PAGE 569
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #UD The LAR instruction cannot be executed in virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If the memory operand effective address referencing the SS segment is in a non-canonical form. #GP(0) If the memory operand effective address is in a non-canonical form. #PF(fault-code) If a page fault occurs.
PAGE 570
INSTRUCTION SET REFERENCE, A-M LDDQU—Load Unaligned Integer 128 Bits Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F F0 /r LDDQU xmm1, mem Valid Valid Load unaligned data from mem and return double quadword in xmm1. Description The instruction is functionally similar to MOVDQU xmm, m128 for loading from memory.
PAGE 571
INSTRUCTION SET REFERENCE, A-M Intel C/C++Compiler Intrinsic Equivalent LDDQU __m128i _mm_lddqu_si128(__m128i const *p) Numeric Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR4.OSFXSR[bit 9] = 0. If CR0.EM[bit 2] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
PAGE 572
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. #PF(fault-code) 3-526 Vol. 2A If a page fault occurs.
PAGE 573
INSTRUCTION SET REFERENCE, A-M LDMXCSR—Load MXCSR Register Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F,AE,/2 LDMXCSR m32 Valid Valid Load MXCSR register from m32. Description Loads the source operand into the MXCSR control/status register. The source operand is a 32-bit memory location. See “MXCSR Control and Status Register” in Chapter 10, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of the MXCSR register and its contents.
PAGE 574
INSTRUCTION SET REFERENCE, A-M If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. For an attempt to set reserved bits in MXCSR. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
PAGE 575
INSTRUCTION SET REFERENCE, A-M LDS/LES/LFS/LGS/LSS—Load Far Pointer Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description C5 /r LDS r16,m16:16 Invalid Valid Load DS:r16 with far pointer from memory. C5 /r LDS r32,m16:32 Invalid Valid Load DS:r32 with far pointer from memory. 0F B2 /r LSS r16,m16:16 Valid Valid Load SS:r16 with far pointer from memory. 0F B2 /r LSS r32,m16:32 Valid Valid Load SS:r32 with far pointer from memory. REX + 0F B2 /r LSS r64,m16:64 Valid N.E.
PAGE 576
INSTRUCTION SET REFERENCE, A-M If one of these instructions is executed in protected mode, additional information from the segment descriptor pointed to by the segment selector in the source operand is loaded in the hidden part of the selected segment register. Also in protected mode, a NULL selector (values 0000 through 0003) can be loaded into DS, ES, FS, or GS registers without causing a protection exception.
PAGE 577
INSTRUCTION SET REFERENCE, A-M FI; SegmentRegister ←SegmentSelector(SRC) ; SegmentRegister ←SegmentDescriptor([SRC]); FI; ELSE IF FS, or GS is loaded with a NULL selector: THEN SegmentRegister ←NULLSelector; SegmentRegister(DescriptorValidBit) ←0; FI; (* Hidden flag; not accessible by software *) FI; DEST ←Offset(SRC); PREOTECTED MODE OR COMPATIBILITY MODE; IF SS is loaded THEN IF SegementSelector = NULL THEN #GP(0); ELSE IF Segment selector index is not within descriptor table limits or segment selector
PAGE 578
INSTRUCTION SET REFERENCE, A-M FI; DEST ←Offset(SRC); Real-Address or Virtual-8086 Mode SegmentRegister ←SegmentSelector(SRC); FI; DEST ←Offset(SRC); Flags Affected None. Protected Mode Exceptions #UD If source operand is not a memory location. If the LOCK prefix is used. #GP(0) If a NULL selector is loaded into the SS register. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
PAGE 579
INSTRUCTION SET REFERENCE, A-M #SS #UD If a memory operand effective address is outside the SS segment limit. If source operand is not a memory location. If the LOCK prefix is used. Virtual-8086 Mode Exceptions #UD If source operand is not a memory location. If the LOCK prefix is used. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
PAGE 580
INSTRUCTION SET REFERENCE, A-M #NP(selector) If FS, or GS register is being loaded with a non-NULL segment selector and the segment is marked not present. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If source operand is not a memory location. If the LOCK prefix is used. 3-534 Vol.
PAGE 581
INSTRUCTION SET REFERENCE, A-M LEA—Load Effective Address Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 8D /r LEA r16,m Valid Valid Store effective address for m in register r16. 8D /r LEA r32,m Valid Valid Store effective address for m in register r32. REX.W + 8D /r LEA r64,m Valid N.E. Store effective address for m in register r64.
PAGE 582
INSTRUCTION SET REFERENCE, A-M Table 3-59. 64-bit Mode LEA Operation with Address and Operand Size Attributes Operand Size Address Size Action Performed 16 32 32-bit effective address is calculated (using 67H prefix). The lower 16 bits of the address are stored in the requested 16-bit register destination (using 66H prefix). 16 64 64-bit effective address is calculated (default address size).
PAGE 583
INSTRUCTION SET REFERENCE, A-M DEST ←temp[0:15]; (* 16-bit address *) FI; ELSE IF OperandSize = 32 and AddressSize = 64 THEN temp ←EffectiveAddress(SRC); (* 64-bit address *) DEST ←temp[0:31]; (* 16-bit address *) FI; ELSE IF OperandSize = 64 and AddressSize = 64 THEN DEST ←EffectiveAddress(SRC); (* 64-bit address *) FI; FI; Flags Affected None. Protected Mode Exceptions #UD If source operand is not a memory location. If the LOCK prefix is used.
PAGE 584
INSTRUCTION SET REFERENCE, A-M LEAVE—High Level Procedure Exit Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description C9 LEAVE Valid Valid Set SP to BP, then pop BP. C9 LEAVE N.E. Valid Set ESP to EBP, then pop EBP. C9 LEAVE Valid N.E. Set RSP to RBP, then pop RBP. Description Releases the stack frame set up by an earlier ENTER instruction.
PAGE 585
INSTRUCTION SET REFERENCE, A-M Flags Affected None. Protected Mode Exceptions #SS(0) If the EBP register points to a location that is not within the limits of the current stack segment. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used.
PAGE 586
INSTRUCTION SET REFERENCE, A-M LFENCE—Load Fence Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F AE /5 LFENCE Valid Valid Serializes load operations. Description Performs a serializing operation on all load-from-memory instructions that were issued prior the LFENCE instruction.
PAGE 587
INSTRUCTION SET REFERENCE, A-M LGDT/LIDT—Load Global/Interrupt Descriptor Table Register Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 01 /2 LGDT m16&32 N.E. Valid Load m into GDTR. 0F 01 /3 LIDT m16&32 N.E. Valid Load m into IDTR. 0F 01 /2 LGDT m16&64 Valid N.E. Load m into GDTR. 0F 01 /3 LIDT m16&64 Valid N.E. Load m into IDTR.
PAGE 588
INSTRUCTION SET REFERENCE, A-M IDTR(Limit) ←SRC[0:15]; IDTR(Base) ←SRC[16:47]; FI; ELSE IF 64-bit Operand Size (* In 64-Bit Mode *) THEN IDTR(Limit) ←SRC[0:15]; IDTR(Base) ←SRC[16:79]; FI; FI; ELSE (* Instruction is LGDT *) IF OperandSize = 16 THEN GDTR(Limit) ←SRC[0:15]; GDTR(Base) ←SRC[16:47] AND 00FFFFFFH; ELSE IF 32-bit Operand Size THEN GDTR(Limit) ←SRC[0:15]; GDTR(Base) ←SRC[16:47]; FI; ELSE IF 64-bit Operand Size (* In 64-Bit Mode *) THEN GDTR(Limit) ←SRC[0:15]; GDTR(Base) ←SRC[16:79]; FI; FI; FI;
PAGE 589
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #UD If source operand is not a memory location. If the LOCK prefix is used. #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #UD If source operand is not a memory location. If the LOCK prefix is used. #GP(0) The LGDT and LIDT instructions are not recognized in virtual8086 mode.
PAGE 590
INSTRUCTION SET REFERENCE, A-M LLDT—Load Local Descriptor Table Register Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 00 /2 LLDT r/m16 Valid Valid Load segment selector r/m16 into LDTR. Description Loads the source operand into the segment selector field of the local descriptor table register (LDTR). The source operand (a general-purpose register or a memory location) contains a segment selector that points to a local descriptor table (LDT).
PAGE 591
INSTRUCTION SET REFERENCE, A-M ELSE LDTR ←INVALID FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #GP(selector) If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT is not a Local Descriptor Table. Segment selector is beyond GDT limit.
PAGE 592
INSTRUCTION SET REFERENCE, A-M #PF(fault-code) If a page fault occurs. #UD If the LOCK prefix is used. 3-546 Vol.
PAGE 593
INSTRUCTION SET REFERENCE, A-M LMSW—Load Machine Status Word Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 01 /6 LMSW r/m16 Valid Valid Loads r/m16 in machine status word of CR0. Description Loads the source operand into the machine status word, bits 0 through 15 of register CR0. The source operand can be a 16-bit general-purpose register or a memory location. Only the low-order 4 bits of the source operand (which contains the PE, MP, EM, and TS flags) are loaded into CR0.
PAGE 594
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #UD If the LOCK prefix is used.
PAGE 595
INSTRUCTION SET REFERENCE, A-M LOCK—Assert LOCK# Signal Prefix Opcode* Instruction 64-Bit Mode Compat/ Leg Mode Description F0 LOCK Valid Valid Asserts LOCK# signal for duration of the accompanying instruction. NOTES: * See IA-32 Architecture Compatibility section below. Description Causes the processor’s LOCK# signal to be asserted during execution of the accompanying instruction (turns the instruction into an atomic instruction).
PAGE 596
INSTRUCTION SET REFERENCE, A-M Operation AssertLOCK#(DurationOfAccompaningInstruction); Flags Affected None. Protected Mode Exceptions #UD If the LOCK prefix is used with an instruction not listed: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, XCHG. Other exceptions can be generated by the instruction when the LOCK prefix is applied. Real-Address Mode Exceptions Same exceptions as in protected mode.
PAGE 597
INSTRUCTION SET REFERENCE, A-M LODS/LODSB/LODSW/LODSD/LODSQ—Load String Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description AC LODS m8 Valid Valid For legacy mode, Load byte at address DS:(E)SI into AL. For 64-bit mode load byte at address (R)SI into AL. AD LODS m16 Valid Valid For legacy mode, Load word at address DS:(E)SI into AX. For 64-bit mode load word at address (R)SI into AX. AD LODS m32 Valid Valid For legacy mode, Load dword at address DS:(E)SI into EAX.
PAGE 598
INSTRUCTION SET REFERENCE, A-M correct location. The location is always specified by the DS:(E)SI registers, which must be loaded correctly before the load string instruction is executed. The no-operands form provides “short forms” of the byte, word, and doubleword versions of the LODS instructions. Here also DS:(E)SI is assumed to be the source operand and the AL, AX, or EAX register is assumed to be the destination operand.
PAGE 599
INSTRUCTION SET REFERENCE, A-M FI; FI; ELSE IF RAX ←SRC; (* Quadword load *) THEN IF DF = 0 THEN (R)SI ←(R)SI +8; ELSE (R)SI ←(R)SI – 8; FI; FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
PAGE 600
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. 3-554 Vol.
PAGE 601
INSTRUCTION SET REFERENCE, A-M LOOP/LOOPcc—Loop According to ECX Counter Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description E2 cb LOOP rel8 Valid Valid Decrement count; jump short if count ≠ 0. E1 cb LOOPE rel8 Valid Valid Decrement count; jump short if count ≠ 0 and ZF = 1. E0 cb LOOPNE rel8 Valid Valid Decrement count; jump short if count ≠ 0 and ZF = 0.
PAGE 602
INSTRUCTION SET REFERENCE, A-M IF (Instruction ←LOOPE) or (Instruction ←LOOPZ) THEN IF (ZF = 1) and (Count ≠ 0) THEN BranchCond ←1; ELSE BranchCond ←0; FI; ELSE (Instruction = LOOPNE) or (Instruction = LOOPNZ) IF (ZF = 0 ) and (Count ≠ 0) THEN BranchCond ←1; ELSE BranchCond ←0; FI; FI; ELSE (* Instruction = LOOP *) IF (Count ≠ 0) THEN BranchCond ←1; ELSE BranchCond ←0; FI; FI; IF BranchCond = 1 THEN IF OperandSize = 32 THEN EIP ←EIP +SignExtend(DEST); ELSE IF OperandSize = 64 THEN RIP ←RIP +SignExtend(DEST
PAGE 603
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the offset being jumped to is beyond the limits of the CS segment. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GP If the offset being jumped to is beyond the limits of the CS segment or is outside of the effective address space from 0 to FFFFH. This condition can occur if a 32-bit address size override prefix is used. #UD If the LOCK prefix is used.
PAGE 604
INSTRUCTION SET REFERENCE, A-M LSL—Load Segment Limit Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 03 /r LSL r16, r16/m16 Valid Valid Load: r16 ←segment limit, selector r16/m16. 0F 03 /r LSL r32, r32/m16* Valid Valid Load: r32 ←segment limit, selector r32/m16. REX.W + 0F 03 /r LSL r64, r32/m16* Valid Valid Load: r64 ←segment limit, selector r32/m16 NOTES: * For all loads (regardless of destination sizing), only bits 16-0 are used. Other bits are ignored.
PAGE 605
INSTRUCTION SET REFERENCE, A-M • Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for (can be accessed with) the LSL instruction. The valid special segment and gate descriptor types are given in the following table.
PAGE 606
INSTRUCTION SET REFERENCE, A-M Read segment descriptor; IF SegmentDescriptor(Type) ≠ conforming code segment and (CPL > DPL) OR (RPL > DPL) or Segment type is not valid for instruction THEN ZF ←0; ELSE temp ←SegmentLimit([SRC]); IF (G ←1) THEN temp ←ShiftLeft(12, temp) OR 00000FFFH; ELSE IF OperandSize = 32 THEN DEST ←temp; FI; ELSE IF OperandSize = 64 (* REX.
PAGE 607
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If the memory operand effective address referencing the SS segment is in a non-canonical form. #GP(0) If the memory operand effective address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3.
PAGE 608
INSTRUCTION SET REFERENCE, A-M LTR—Load Task Register Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 00 /3 LTR r/m16 Valid Valid Load r/m16 into task register. Description Loads the source operand into the segment selector field of the task register. The source operand (a general-purpose register or a memory location) contains a segment selector that points to a task state segment (TSS).
PAGE 609
INSTRUCTION SET REFERENCE, A-M Flags Affected None. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the source operand contains a NULL segment selector. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #GP(selector) If the source selector points to a segment that is not a TSS or to one for a task that is already busy.
PAGE 610
INSTRUCTION SET REFERENCE, A-M #NP(selector) If the TSS is marked not present. #PF(fault-code) If a page fault occurs. #UD If the LOCK prefix is used. 3-564 Vol.
PAGE 611
INSTRUCTION SET REFERENCE, A-M MASKMOVDQU—Store Selected Bytes of Double Quadword Opcode Instruction 66 0F F7 /r MASKMOVDQU xmm1, xmm2 64-Bit Mode Compat/ Leg Mode Description Valid Valid Selectively write bytes from xmm1 to memory location using the byte mask in xmm2. The default memory location is specified by DS:EDI. Description Stores selected bytes from the source operand (first operand) into an 128-bit memory location.
PAGE 612
INSTRUCTION SET REFERENCE, A-M In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
PAGE 613
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault (implementation specific). #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #GP(0) If the memory address is in a non-canonical form. #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #PF(fault-code) For a page fault (implementation specific). #NM If CR0.
PAGE 614
INSTRUCTION SET REFERENCE, A-M MASKMOVQ—Store Selected Bytes of Quadword Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F F7 /r MASKMOVQ mm1, mm2 Valid Valid Selectively write bytes from mm1 to memory location using the byte mask in mm2. The default memory location is specified by DS:EDI. Description Stores selected bytes from the source operand (first operand) into a 64-bit memory location.
PAGE 615
INSTRUCTION SET REFERENCE, A-M The MASKMOVQ instruction can be used to improve performance for algorithms that need to merge data on a byte-by-byte basis. It should not cause a read for ownership; doing so generates unnecessary bandwidth since data is to be written directly using the byte-mask without allocating old data prior to the store. In 64-bit mode, the memory address is specified by DS:RDI.
PAGE 616
INSTRUCTION SET REFERENCE, A-M #MF If there is a pending FPU exception. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault (implementation specific). #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in protected mode.
PAGE 617
INSTRUCTION SET REFERENCE, A-M MAXPD—Return Maximum Packed Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 5F /r MAXPD xmm1, xmm2/m128 Valid Valid Return the maximum doubleprecision floating-point values between xmm2/m128 and xmm1.
PAGE 618
INSTRUCTION SET REFERENCE, A-M ELSE SRC[127:64]; FI; FI; Intel C/C++Compiler Intrinsic Equivalent MAXPD __m128d _mm_max_pd(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) If a memory operand effective address is outside the SS segment limit.
PAGE 619
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.
PAGE 620
INSTRUCTION SET REFERENCE, A-M MAXPS—Return Maximum Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 5F /r MAXPS xmm1, xmm2/m128 Valid Valid Return the maximum single-precision floating-point values between xmm2/m128 and xmm1.
PAGE 621
INSTRUCTION SET REFERENCE, A-M THEN DEST[127:96]; ELSE SRC[127:96]; FI; FI; Intel C/C++Compiler Intrinsic Equivalent MAXPS __m128d _mm_max_ps(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
PAGE 622
INSTRUCTION SET REFERENCE, A-M If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment.
PAGE 623
INSTRUCTION SET REFERENCE, A-M MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 5F /r MAXSD xmm1, xmm2/m64 Valid Valid Return the maximum scalar doubleprecision floating-point value between xmm2/mem64 and xmm1.
PAGE 624
INSTRUCTION SET REFERENCE, A-M Intel C/C++Compiler Intrinsic Equivalent MAXSD __m128d _mm_max_sd(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
PAGE 625
INSTRUCTION SET REFERENCE, A-M #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.
PAGE 626
INSTRUCTION SET REFERENCE, A-M MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value Opcode Instruction F3 0F 5F /r MAXSS xmm1, xmm2/m32 64-Bit Mode Compat/ Leg Mode Description Valid Valid Return the maximum scalar singleprecision floating-point value between xmm2/mem32 and xmm1.
PAGE 627
INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
PAGE 628
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
PAGE 629
INSTRUCTION SET REFERENCE, A-M MFENCE—Memory Fence Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F AE /6 MFENCE Valid Valid Serializes load and store operations. Description Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior the MFENCE instruction.
PAGE 630
INSTRUCTION SET REFERENCE, A-M MINPD—Return Minimum Packed Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 5D /r MINPD xmm1, xmm2/m128 Valid Valid Return the minimum doubleprecision floating-point values between xmm2/m128 and xmm1.
PAGE 631
INSTRUCTION SET REFERENCE, A-M THEN DEST[127:64] ELSE SRC[127:64]; FI; FI; Intel C/C++Compiler Intrinsic Equivalent MINPD __m128d _mm_min_pd(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
PAGE 632
INSTRUCTION SET REFERENCE, A-M If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form.
PAGE 633
INSTRUCTION SET REFERENCE, A-M MINPS—Return Minimum Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 5D /r MINPS xmm1, xmm2/m128 Valid Valid Return the minimum single-precision floating-point values between xmm2/m128 and xmm1.
PAGE 634
INSTRUCTION SET REFERENCE, A-M THEN DEST[127:96] ELSE SRC[127:96]; FI; FI; Intel C/C++Compiler Intrinsic Equivalent MINPS __m128d _mm_min_ps(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
PAGE 635
INSTRUCTION SET REFERENCE, A-M If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment.
PAGE 636
INSTRUCTION SET REFERENCE, A-M MINSD—Return Minimum Scalar Double-Precision Floating-Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 5D /r MINSD xmm1, xmm2/m64 Valid Valid Return the minimum scalar doubleprecision floating-point value between xmm2/mem64 and xmm1.
PAGE 637
INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
PAGE 638
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
PAGE 639
INSTRUCTION SET REFERENCE, A-M MINSS—Return Minimum Scalar Single-Precision Floating-Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 5D /r MINSS xmm1, xmm2/m32 Valid Valid Return the minimum scalar singleprecision floating-point value between xmm2/mem32 and xmm1.
PAGE 640
INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
PAGE 641
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
PAGE 642
INSTRUCTION SET REFERENCE, A-M MONITOR—Set Up Monitor Address Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description OF 01 C8 MONITOR Valid Valid Sets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a write-back memory caching type. The default address is DS:EAX.
PAGE 643
INSTRUCTION SET REFERENCE, A-M Operation MONITOR sets up an address range for the monitor hardware using the content of EAX as an effective address and puts the monitor hardware in armed state. Always use memory of the write-back caching type. A store to the specified address range will trigger the monitor hardware. The content of ECX and EDX are used to communicate other information to the monitor hardware.
PAGE 644
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #GP(0) If the linear address of the operand in the CS, DS, ES, FS, or GS segment is in a non-canonical form. If RCX ←0. #SS(0) If the linear address of the operand in the SS segment is in a non-canonical form. #PF(fault-code) For a page fault. #UD If the current privilege level is not 0. If CPUID.01H:ECX.MONITOR[bit 3] = 0. 3-598 Vol.
PAGE 645
INSTRUCTION SET REFERENCE, A-M MOV—Move Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 88 /r MOV r/m8,r8 Valid Valid Move r8 to r/m8. REX + 88 /r MOV r/m8***,r8*** Valid N.E. Move r8 to r/m8. 89 /r MOV r/m16,r16 Valid Valid Move r16 to r/m16. 89 /r MOV r/m32,r32 Valid Valid Move r32 to r/m32. REX.W + 89 /r MOV r/m64,r64 Valid N.E. Move r64 to r/m64. 8A /r MOV r8,r/m8 Valid Valid Move r/m8 to r8. REX + 8A /r MOV r8***,r/m8*** Valid N.E. Move r/m8 to r8.
PAGE 646
INSTRUCTION SET REFERENCE, A-M Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description REX.W + A3 MOV moffs64*,RAX Valid N.E. Move RAX to (offset). B0+ rb MOV r8, imm8 Valid Valid Move imm8 to r8. REX + B0+ rb MOV r8***, imm8 Valid N.E. Move imm8 to r8. B8+ rw MOV r16, imm16 Valid Valid Move imm16 to r16. B8+ rd MOV r32, imm32 Valid Valid Move imm32 to r32. REX.W + B8+ rd MOV r64, imm64 Valid N.E. Move imm64 to r64.
PAGE 647
INSTRUCTION SET REFERENCE, A-M below). The segment descriptor data is obtained from the GDT or LDT entry for the specified segment selector. A NULL segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers without causing a protection exception. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded with a NULL value causes a general protection exception (#GP) and no memory reference occurs.
PAGE 648
INSTRUCTION SET REFERENCE, A-M Loading a segment register while in protected mode results in special checks and actions, as described in the following listing. These checks are performed on the segment selector and the segment descriptor to which it points.
PAGE 649
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If attempt is made to load SS register with NULL segment selector. If the destination operand is in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #GP(selector) If segment selector index is outside descriptor table limits.
PAGE 650
INSTRUCTION SET REFERENCE, A-M #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If attempt is made to load the CS register. If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #GP(0) If the memory address is in a non-canonical form.
PAGE 651
INSTRUCTION SET REFERENCE, A-M MOV—Move to/from Control Registers Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 20 /0 MOV r32,CR0 N.E. Valid Move CR0 to r32. 0F 20 /0 MOV r64,CR0 Valid N.E. Move extended CR0 to r64. 0F 20 /2 MOV r32,CR2 N.E. Valid Move CR2 to r32. 0F 20 /2 MOV r64,CR2 Valid N.E. Move extended CR2 to r64. 0F 20 /3 MOV r32,CR3 N.E. Valid Move CR3 to r32. 0F 20 /3 MOV r64,CR3 Valid N.E. Move extended CR3 to r64. 0F 20 /4 MOV r32,CR4 N.E.
PAGE 652
INSTRUCTION SET REFERENCE, A-M and CR3 remain clear after any load of those registers; attempts to set them have no impact. On Pentium 4, Intel Xeon and P6 family processors, CR0.ET remains set after any load of CR0; attempts to clear this bit have no impact. At the opcode level, the reg field within the ModR/M byte specifies which of the control registers is loaded or read. The 2 bits in the mod field are always 11B. The r/m field specifies the general-purpose register loaded or read.
PAGE 653
INSTRUCTION SET REFERENCE, A-M If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1 when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1). If an attempt is made to write a 1 to any reserved bit in CR4. If any of the reserved bits are set in the page-directory pointers table (PDPT) and the loading of a control register causes the PDPT to be loaded into the processor. #UD If the LOCK prefix is used.
PAGE 654
INSTRUCTION SET REFERENCE, A-M MOV—Move to/from Debug Registers Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 21/r MOV r32, DR0-DR7 N.E. Valid Move debug register to r32 0F 21/r MOV r64, DR0-DR7 Valid N.E. Move extended debug register to r64. 0F 23 /r MOV DR0-DR7, r32 N.E. Valid Move r32 to debug register 0F 23 /r MOV DR0-DR7, r64 Valid N.E. Move r64 to extended debug register.
PAGE 655
INSTRUCTION SET REFERENCE, A-M Flags Affected The OF, SF, ZF, AF, PF, and CF flags are undefined. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. #UD If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or DR5. If the LOCK prefix is used. #DB If any debug register is accessed while the DR7.GD[bit 13] = 1. Real-Address Mode Exceptions #UD If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or DR5.
PAGE 656
INSTRUCTION SET REFERENCE, A-M MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 28 /r MOVAPD xmm1, xmm2/m128 Valid Valid Move packed double-precision floating-point values from xmm2/m128 to xmm1. 66 0F 29 /r MOVAPD xmm2/m128, xmm1 Valid Valid Move packed double-precision floating-point values from xmm1 to xmm2/m128.
PAGE 657
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
PAGE 658
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. 3-612 Vol.
PAGE 659
INSTRUCTION SET REFERENCE, A-M MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 28 /r MOVAPS xmm1, xmm2/m128 Valid Valid Move packed single-precision floating-point values from xmm2/m128 to xmm1. 0F 29 /r MOVAPS xmm2/m128, xmm1 Valid Valid Move packed single-precision floating-point values from xmm1 to xmm2/m128.
PAGE 660
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
PAGE 661
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values Vol.
PAGE 662
INSTRUCTION SET REFERENCE, A-M MOVD/MOVQ—Move Doubleword/Move Quadword Opcode Instruction 0F 6E /r 64-Bit Mode Compat/ Leg Mode Description MOVD mm, r/m32 Valid Valid Move doubleword from r/m32 to mm. REX.W + 0F 6E /r MOVQ mm, r/m64 Valid N.E. Move quadword from r/m64 to mm. 0F 7E /r MOVD r/m32, mm Valid Valid Move doubleword from mm to r/m32. REX.W + 0F 7E /r MOVQ r/m64, mm Valid N.E. Move quadword from mm to r/m64.
PAGE 663
INSTRUCTION SET REFERENCE, A-M Operation MOVD instruction when destination operand is MMX technology register: DEST[31:0] ←SRC; DEST[63:32] ←00000000H; MOVD instruction when destination operand is XMM register: DEST[31:0] ←SRC; DEST[127:32] ←000000000000000000000000H; MOVD instruction when source operand is MMX technology or XMM register: DEST ←SRC[31:0]; MOVQ instruction when destination operand is XMM register: DEST[63:0] ←SRC[63:0]; DEST[127:64] ←0000000000000000H; MOVQ instruction when destination oper
PAGE 664
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used. #NM If CR0.TS[bit 3] = 1. #MF (MMX register operations only) If there is a pending FPU exception. #PF(fault-code) If a page fault occurs.
PAGE 665
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. (XMM register operations only) if CR4.OSFXSR[bit 9] = 0. (XMM register operations only) if CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #NM If CR0.TS[bit 3] = 1. #MF (MMX register operations only) If there is a pending FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 666
INSTRUCTION SET REFERENCE, A-M MOVDDUP—Move One Double-FP and Duplicate Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 12 /r MOVDDUP xmm1, xmm2/m64 Valid Valid Move one double-precision floatingpoint value from the lower 64-bit operand in xmm2/m64 to xmm1 and duplicate. Description The linear address corresponds to the address of the least-significant byte of the referenced memory data. When a memory address is indicated, the 8 bytes of data at memory location m64 are loaded.
PAGE 667
INSTRUCTION SET REFERENCE, A-M xmm1[127:64] = m64; ELSE (* Move instruction *) xmm1[63:0] = xmm2[63:0]; xmm1[127:64] = xmm2[63:0]; FI; Intel C/C++Compiler Intrinsic Equivalent MOVDDUP __m128d _mm_movedup_pd(__m128d a) __m128d _mm_loaddup_pd(double const * dp) Exceptions None Numeric Exceptions None Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault.
PAGE 668
INSTRUCTION SET REFERENCE, A-M Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in protected mode.
PAGE 669
INSTRUCTION SET REFERENCE, A-M MOVDQA—Move Aligned Double Quadword Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 6F /r MOVDQA xmm1, xmm2/m128 Valid Valid Move aligned double quadword from xmm2/m128 to xmm1. 66 0F 7F /r MOVDQA xmm2/m128, xmm1 Valid Valid Move aligned double quadword from xmm1 to xmm2/m128. Description Moves a double quadword from the source operand (second operand) to the destination operand (first operand).
PAGE 670
INSTRUCTION SET REFERENCE, A-M #SS(0) If a memory operand effective address is outside the SS segment limit. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH. #NM #UD If CR0.TS[bit 3] = 1. If CR0.
PAGE 671
INSTRUCTION SET REFERENCE, A-M MOVDQU—Move Unaligned Double Quadword Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 6F /r MOVDQU xmm1, xmm2/m128 Valid Valid Move unaligned double quadword from xmm2/m128 to xmm1. F3 0F 7F /r MOVDQU xmm2/m128, Valid xmm1 Valid Move unaligned double quadword from xmm1 to xmm2/m128. Description Moves a double quadword from the source operand (second operand) to the destination operand (first operand).
PAGE 672
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #PF(fault-code) If a page fault occurs.
PAGE 673
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. MOVDQU—Move Unaligned Double Quadword Vol.
PAGE 674
INSTRUCTION SET REFERENCE, A-M MOVDQ2Q—Move Quadword from XMM to MMX Technology Register Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F D6 MOVDQ2Q mm, xmm Valid Valid Move low quadword from xmm to mmx register. Description Moves the low quadword from the source operand (second operand) to the destination operand (first operand). The source operand is an XMM register and the destination operand is an MMX technology register.
PAGE 675
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. MOVDQ2Q—Move Quadword from XMM to MMX Technology Register Vol.
PAGE 676
INSTRUCTION SET REFERENCE, A-M MOVHLPS— Move Packed Single-Precision Floating-Point Values High to Low Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description OF 12 /r MOVHLPS xmm1, xmm2 Valid Valid Move two packed singleprecision floating-point values from high quadword of xmm2 to low quadword of xmm1.
PAGE 677
INSTRUCTION SET REFERENCE, A-M Virtual 8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. MOVHLPS— Move Packed Single-Precision Floating-Point Values High to Low Vol.
PAGE 678
INSTRUCTION SET REFERENCE, A-M MOVHPD—Move High Packed Double-Precision Floating-Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 16 /r MOVHPD xmm, m64 Valid Valid Move double-precision floating-point value from m64 to high quadword of xmm. 66 0F 17 /r MOVHPD m64, xmm Valid Valid Move double-precision floating-point value from high quadword of xmm to m64.
PAGE 679
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 680
INSTRUCTION SET REFERENCE, A-M If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) 3-634 Vol. 2A If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 681
INSTRUCTION SET REFERENCE, A-M MOVHPS—Move High Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 16 /r MOVHPS xmm, m64 Valid Valid Move two packed single-precision floating-point values from m64 to high quadword of xmm. 0F 17 /r MOVHPS m64, xmm Valid Valid Move two packed single-precision floating-point values from high quadword of xmm to m64.
PAGE 682
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH.
PAGE 683
INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. MOVHPS—Move High Packed Single-Precision Floating-Point Values Vol.
PAGE 684
INSTRUCTION SET REFERENCE, A-M MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description OF 16 /r MOVLHPS xmm1, xmm2 Valid Valid Move two packed single-precision floating-point values from low quadword of xmm2 to high quadword of xmm1.
PAGE 685
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High Vol.
PAGE 686
INSTRUCTION SET REFERENCE, A-M MOVLPD—Move Low Packed Double-Precision Floating-Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 12 /r MOVLPD xmm, m64 Valid Valid Move double-precision floating-point value from m64 to low quadword of xmm register. 66 0F 13 /r MOVLPD m64, xmm Valid Valid Move double-precision floating-point nvalue from low quadword of xmm register to m64.
PAGE 687
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH.
PAGE 688
INSTRUCTION SET REFERENCE, A-M MOVLPS—Move Low Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 12 /r MOVLPS xmm, m64 Valid Valid Move two packed single-precision floating-point values from m64 to low quadword of xmm. 0F 13 /r MOVLPS m64, xmm Valid Valid Move two packed single-precision floating-point values from low quadword of xmm to m64.
PAGE 689
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH.
PAGE 690
INSTRUCTION SET REFERENCE, A-M #AC(0) 3-644 Vol. 2A If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 691
INSTRUCTION SET REFERENCE, A-M MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 50 /r MOVMSKPD r32, xmm Valid Valid Extract 2-bit sign mask from xmm and store in r32. 66 REX.W 0F 50 /r MOVMSKPD r64, xmm Valid N.E. Extract 2-bit sign mask from xmm and store in r64. Zero extend 32-bit results to 64-bits.
PAGE 692
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. 3-646 Vol.
PAGE 693
INSTRUCTION SET REFERENCE, A-M MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 50 /r MOVMSKPS r32, xmm Valid Valid Extract 4-bit sign mask from xmm and store in r32. REX.W + 0F 50 /r MOVMSKPS r64, xmm Valid N.E. Extract 4-bit sign mask from xmm and store in r64. Zero extend 32-bit results to 64-bits.
PAGE 694
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual 8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. 3-648 Vol.
PAGE 695
INSTRUCTION SET REFERENCE, A-M MOVNTDQ—Store Double Quadword Using Non-Temporal Hint Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F E7 /r MOVNTDQ m128, xmm Valid Valid Move double quadword from xmm to m128 using non-temporal hint. Description Moves the double quadword in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory.
PAGE 696
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
PAGE 697
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. MOVNTDQ—Store Double Quadword Using Non-Temporal Hint Vol.
PAGE 698
INSTRUCTION SET REFERENCE, A-M MOVNTI—Store Doubleword Using Non-Temporal Hint Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F C3 /r MOVNTI m32, r32 Valid Valid Move doubleword from r32 to m32 using non-temporal hint. REX.W + 0F C3 /r MOVNTI m64, r64 Valid N.E. Move quadword from r64 to m64 using non-temporal hint.
PAGE 699
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #UD If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.
PAGE 700
INSTRUCTION SET REFERENCE, A-M MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 2B /r MOVNTPD m128, xmm Valid Valid Move packed double-precision floating-point values from xmm to m128 using non-temporal hint.
PAGE 701
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
PAGE 702
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. 3-656 Vol.
PAGE 703
INSTRUCTION SET REFERENCE, A-M MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 2B /r MOVNTPS m128, xmm Valid Valid Move packed single-precision floatingpoint values from xmm to m128 using non-temporal hint.
PAGE 704
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
PAGE 705
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint Vol.
PAGE 706
INSTRUCTION SET REFERENCE, A-M MOVNTQ—Store of Quadword Using Non-Temporal Hint Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F E7 /r MOVNTQ m64, mm Valid Valid Move quadword from mm to m64 using non-temporal hint. Description Moves the quadword in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to minimize cache pollution during the write to memory.
PAGE 707
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 708
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) 3-662 Vol. 2A If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 709
INSTRUCTION SET REFERENCE, A-M MOVQ—Move Quadword Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 6F /r MOVQ mm, mm/m64 Valid Valid Move quadword from mm/m64 to mm. 0F 7F /r MOVQ mm/m64, mm Valid Valid Move quadword from mm to mm/m64. F3 0F 7E MOVQ xmm1, xmm2/m64 Valid Valid Move quadword from xmm2/mem64 to xmm1. 66 0F D6 MOVQ xmm2/m64, xmm1 Valid Valid Move quadword from xmm1 to xmm2/mem64.
PAGE 710
INSTRUCTION SET REFERENCE, A-M DEST[127:64] ←0000000000000000H; Flags Affected None. SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) If the destination operand is in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0.
PAGE 711
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in real address mode. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #UD If CR0.EM[bit 2] = 1.
PAGE 712
INSTRUCTION SET REFERENCE, A-M MOVQ2DQ—Move Quadword from MMX Technology to XMM Register Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F D6 MOVQ2DQ xmm, mm Valid Valid Move quadword from mmx to low quadword of xmm. Description Moves the quadword from the source operand (second operand) to the low quadword of the destination operand (first operand). The source operand is an MMX technology register and the destination operand is an XMM register.
PAGE 713
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions Same exceptions as in protected mode. MOVQ2DQ—Move Quadword from MMX Technology to XMM Register Vol.
PAGE 714
INSTRUCTION SET REFERENCE, A-M MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String \ Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description A4 MOVS m8, m8 Valid Valid For legacy mode, Move byte from address DS:(E)SI to ES:(E)DI. For 64-bit mode move byte from address (R|E)SI to (R|E)DI. A5 MOVS m16, m16 Valid Valid For legacy mode, move word from address DS:(E)SI to ES:(E)DI. For 64-bit mode move word at address (R|E)SI to (R|E)DI.
PAGE 715
INSTRUCTION SET REFERENCE, A-M At the assembly-code level, two forms of this instruction are allowed: the “explicitoperands” form and the “no-operands” form. The explicit-operands form (specified with the MOVS mnemonic) allows the source and destination operands to be specified explicitly. Here, the source and destination operands should be symbols that indicate the size and location of the source value and the destination, respectively.
PAGE 716
INSTRUCTION SET REFERENCE, A-M (E)SI ←(E)SI – 1; (E)DI ←(E)DI – 1; FI; ELSE IF (Word move) THEN IF DF = 0 (E)SI ←(E)SI +2; (E)DI ←(E)DI +2; FI; ELSE (E)SI ←(E)SI – 2; (E)DI ←(E)DI – 2; FI; ELSE IF (Doubleword move) THEN IF DF = 0 (E)SI ←(E)SI +4; (E)DI ←(E)DI +4; FI; ELSE (E)SI ←(E)SI – 4; (E)DI ←(E)DI – 4; FI; FI; 64-bit Mode: IF (Byte move) THEN IF DF = 0 THEN (R|E)SI ←(R|E)SI +1; (R|E)DI ←(R|E)DI +1; ELSE (R|E)SI ←(R|E)SI – 1; (R|E)DI ←(R|E)DI – 1; FI; ELSE IF (Word move) THEN IF DF = 0 (R|E)SI ←(R|E)S
PAGE 717
INSTRUCTION SET REFERENCE, A-M (R|E)SI ←(R|E)SI +4; (R|E)DI ←(R|E)DI +4; FI; ELSE (R|E)SI ←(R|E)SI – 4; (R|E)DI ←(R|E)DI – 4; FI; ELSE IF (Quadword move) THEN IF DF = 0 (R|E)SI ←(R|E)SI +8; (R|E)DI ←(R|E)DI +8; FI; ELSE (R|E)SI ←(R|E)SI – 8; (R|E)DI ←(R|E)DI – 8; FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
PAGE 718
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode.
PAGE 719
INSTRUCTION SET REFERENCE, A-M MOVSD—Move Scalar Double-Precision Floating-Point Value Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F2 0F 10 /r MOVSD xmm1, xmm2/m64 Valid Valid Move scalar double-precision floating-point value from xmm2/m64 to xmm1 register. F2 0F 11 /r MOVSD xmm2/m64, Valid xmm1 Valid Move scalar double-precision floating-point value from xmm1 register to xmm2/m64.
PAGE 720
INSTRUCTION SET REFERENCE, A-M MOVSD void _mm_store_sd (double *p, __m128d a) MOVSD __m128d _mm_store_sd (__m128d a, __m128d b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
PAGE 721
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 722
INSTRUCTION SET REFERENCE, A-M MOVSHDUP—Move Packed Single-FP High and Duplicate Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 16 /r MOVSHDUP xmm1, xmm2/m128 Valid Valid Move two single-precision floatingpoint values from the higher 32-bit operand of each qword in xmm2/m128 to xmm1 and duplicate each 32-bit operand to the lower 32-bits of each qword. Description The linear address corresponds to the address of the least-significant byte of the referenced memory data.
PAGE 723
INSTRUCTION SET REFERENCE, A-M Operation IF (Source == m128) THEN (* Load instruction *) xmm1[31:0] = m128[63:32]; xmm1[63:32] = m128[63:32]; xmm1[95:64] = m128[127:96]; xmm1[127:96] = m128[127:96]; ELSE (* Move instruction *) xmm1[31:0] = xmm2[63:32]; xmm1[63:32] = xmm2[63:32]; xmm1[95:64] = xmm2[127:96]; xmm1[127:96] = xmm2[127:96]; FI; Intel C/C++Compiler Intrinsic Equivalent MOVSHDUP __m128 _mm_movehdup_ps(__m128 a) Exceptions General protection exception if not aligned on 16-byte boundary, regardle
PAGE 724
INSTRUCTION SET REFERENCE, A-M Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
PAGE 725
INSTRUCTION SET REFERENCE, A-M MOVSLDUP—Move Packed Single-FP Low and Duplicate Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 12 /r MOVSLDUP xmm1, xmm2/m128 Valid Valid Move two single-precision floating-point values from the lower 32-bit operand of each qword in xmm2/m128 to xmm1 and duplicate each 32-bit operand to the higher 32-bits of each qword. Description The linear address corresponds to the address of the least-significant byte of the referenced memory data.
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INSTRUCTION SET REFERENCE, A-M Operation IF (Source == m128) THEN (* Load instruction *) xmm1[31:0] = m128[31:0]; xmm1[63:32] = m128[31:0]; xmm1[95:64] = m128[95:64]; xmm1[127:96] = m128[95::64]; ELSE (* Move instruction *) xmm1[31:0] = xmm2[31:0]; xmm1[63:32] = xmm2[31:0]; xmm1[95:64] = xmm2[95:64]; xmm1[127:96] = xmm2[95:64]; FI; Intel C/C++Compiler Intrinsic Equivalent MOVSLDUP __m128 _mm_moveldup_ps(__m128 a) Exceptions General protection exception if not aligned on 16-byte boundary, regardless of s
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INSTRUCTION SET REFERENCE, A-M Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1.If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M MOVSS—Move Scalar Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 10 /r MOVSS xmm1, xmm2/m32 Valid Valid Move scalar single-precision floating-point value from xmm2/m32 to xmm1 register. F3 0F 11 /r MOVSS xmm2/m32, Valid xmm Valid Move scalar single-precision floating-point value from xmm1 register to xmm2/m32.
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INSTRUCTION SET REFERENCE, A-M MOVSS void _mm_store_ss(float * p, __m128 a) MOVSS __m128 _mm_move_ss(__m128 a, __m128 b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
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INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) 3-684 Vol.
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INSTRUCTION SET REFERENCE, A-M MOVSX/MOVSXD—Move with Sign-Extension Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F BE /r MOVSX r16, r/m8 Valid Valid Move byte to word with signextension. 0F BE /r MOVSX r32, r/m8 Valid Valid Move byte to doubleword with sign-extension. REX + 0F BE /r MOVSX r64, r/m8* Valid N.E. Move byte to quadword with sign-extension. 0F BF /r MOVSX r32, r/m16 Valid Valid Move word to doubleword, with sign-extension. REX.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 66 0F 10 /r MOVUPD xmm1, xmm2/m128 Valid Valid Move packed double-precision floating-point values from xmm2/m128 to xmm1. 66 0F 11 /r MOVUPD xmm2/m128, xmm Valid Valid Move packed double-precision floating-point values from xmm1 to xmm2/m128.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values Vol.
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INSTRUCTION SET REFERENCE, A-M MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 10 /r MOVUPS xmm1, xmm2/m128 Valid Valid Move packed single-precision floatingpoint values from xmm2/m128 to xmm1. 0F 11 /r MOVUPS xmm2/m128, xmm1 Valid Valid Move packed single-precision floatingpoint values from xmm1 to xmm2/m128.
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INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
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INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. 3-692 Vol.
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INSTRUCTION SET REFERENCE, A-M MOVZX—Move with Zero-Extend Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F B6 /r MOVZX r16, r/m8 Valid Valid Move byte to word with zeroextension. 0F B6 /r MOVZX r32, r/m8 Valid Valid Move byte to doubleword, zero-extension. REX.W + 0F B6 /r MOVZX r64, r/m8* Valid N.E. Move byte to quadword, zeroextension. 0F B7 /r MOVZX r32, r/m16 Valid Valid Move word to doubleword, zero-extension. REX.W + 0F B7 /r MOVZX r64, r/m16 Valid N.E.
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INSTRUCTION SET REFERENCE, A-M #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If the LOCK prefix is used. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit.
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INSTRUCTION SET REFERENCE, A-M MUL—Unsigned Multiply Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F6 /4 MUL r/m8 Valid Valid Unsigned multiply (AX ←AL ∗ r/m8). REX + F6 /4 MUL r/m8* Valid N.E. Unsigned multiply (AX ←AL ∗ r/m8). F7 /4 MUL r/m16 Valid Valid Unsigned multiply (DX:AX ←AX ∗ r/m16). F7 /4 MUL r/m32 Valid Valid Unsigned multiply (EDX:EAX ←EAX ∗ r/m32). REX.W + F7 /4 MUL r/m64 Valid N.E. Unsigned multiply (RDX:RAX ←RAX ∗ r/m64.
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INSTRUCTION SET REFERENCE, A-M Operation IF (Byte operation) THEN AX ←AL ∗ SRC; ELSE (* Word or doubleword operation *) IF OperandSize = 16 THEN DX:AX ←AX ∗ SRC; ELSE IF OperandSize = 32 THEN EDX:EAX ←EAX ∗ SRC; FI; ELSE (* OperandSize = 64 *) RDX:RAX ←RAX ∗ SRC; FI; FI; Flags Affected The OF and CF flags are set to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and PF flags are undefined.
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INSTRUCTION SET REFERENCE, A-M #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If the LOCK prefix is used. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form.
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INSTRUCTION SET REFERENCE, A-M MULPD—Multiply Packed Double-Precision Floating-Point Values Opcode Instruction 66 0F 59 /r MULPD xmm1, xmm2/m128 64-Bit Mode Compat/ Leg Mode Description Valid Valid Multiply packed double-precision floating-point values in xmm2/m128 by xmm1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. 3-700 Vol.
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INSTRUCTION SET REFERENCE, A-M MULPS—Multiply Packed Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 59 /r MULPS xmm1, xmm2/m128 Valid Valid Multiply packed single-precision floating-point values in xmm2/mem by xmm1.
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INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.
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INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. MULPS—Multiply Packed Single-Precision Floating-Point Values Vol.
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INSTRUCTION SET REFERENCE, A-M MULSD—Multiply Scalar Double-Precision Floating-Point Values Opcode Instruction F2 0F 59 /r MULSD xmm1, xmm2/m64 64-Bit Mode Compat/ Leg Mode Description Valid Valid Multiply the low double-precision floating-point value in xmm2/mem64 by low double-precision floating-point value in xmm1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #AC(0) 3-706 Vol. 2A If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, A-M MULSS—Multiply Scalar Single-Precision Floating-Point Values Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description F3 0F 59 /r MULSS xmm1, xmm2/m32 Valid Valid Multiply the low single-precision floatingpoint value in xmm2/mem by the low single-precision floating-point value in xmm1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. MULSS—Multiply Scalar Single-Precision Floating-Point Values Vol.
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INSTRUCTION SET REFERENCE, A-M MWAIT—Monitor Wait Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description OF 01 C9 MWAIT Valid Valid A hint that allow the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Description MWAIT instruction provides hints to allow the processor to enter an implementationdependent optimized state.
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INSTRUCTION SET REFERENCE, A-M processor will exit the state and handle the interrupt. If an SMI caused the processor to exit the implementation-dependent-optimized state, execution will resume at the instruction following MWAIT after handling of the SMI. Unlike the HLT instruction, the MWAIT instruction does not support a restart at the MWAIT instruction.
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INSTRUCTION SET REFERENCE, A-M Table 3-63.
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INSTRUCTION SET REFERENCE, A-M EDX = 0 (* Hints *) IF ( !trigger_store_happened) { MONITOR EAX, ECX, EDX IF ( !trigger_store_happened ) { MWAIT EAX, ECX } } The above code sequence makes sure that a triggering store does not happen between the first check of the trigger and the execution of the monitor instruction. Without the second check that triggering store would go un-noticed. Typical usage of MONITOR and MWAIT would have the above code sequence within a loop.
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INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #GP(0) If the linear address of the operand in the CS, DS, ES, FS, or GS segment is in a non-canonical form. If RCX ≠ 0. #SS(0) If the linear address of the operand in the SS segment is in a non-canonical form. #PF(fault-code) For a page fault. #UD If the current privilege level is not 0. If CPUID.01H:ECX.MONITOR[bit 3] = 0. 3-714 Vol.