Datasheet

Datasheet, Volume 2 195
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Processor Integrated I/O (IIO) Configuration Registers
3.3.4.8 ERRPINST—Error Pin Status Register
This register reflects the state of the error pin assertion. The status bit of the
corresponding error pin is set upon the deassertion to assertion transition of the error
pin. This bit is cleared by the software with writing 1 to the corresponding bit.
3.3.4.9 ERRPINDAT—Error Pin Data Register
This register provides the data value when the error pin is configured as a general
purpose output.
ERRPINST
Bus: 0 Device: 5 Function: 2 Offset: A8
Bit Attr
Reset
Value
Description
31:3 RV 0h Reserved
2RW1CS 0b
Error[2] Pin Status
This bit is set upon the transition of deassertion to assertion of the Error pin.
Software write 1 to clear the status.
1RW1CS 0b
Error[1] Pin Status
This bit is set upon the transition of deassertion to assertion of the Error pin.
Software write 1 to clear the status.
0RW1CS 0b
Error[0] Pin Status
This bit is set upon the transition of deassertion to assertion of the Error pin.
Software write 1 to clear the status.
ERRPINDAT
Bus: 0 Device: 5 Function: 2 Offset: AC
Bit Attr
Reset
Value
Description
31:3 RV 0h Reserved
2RW-LB 0b
Error[2] Pin Data
This bit acts as the general purpose output for the Error[2] pin. Software sets/
clears this bit to assert/deassert Error[2] pin. This bit applies only when
ERRPINCTL[5:4]=01; otherwise it is reserved.
0 = Deassert Error[2] pin
1 = Assert Error[2] pin
1RW-LB 0b
Error[1] Pin Data
This bit acts as the general purpose output for the Error[1] pin. Software sets/
clears this bit to assert/deassert Error[1] pin. This bit applies only when
ERRPINCTL[3:2]=01; otherwise it is reserved.
0 = Deassert Error[1] pin
1 = Assert Error[1] pin
0RW-LB 0b
Error[0] Pin Data
This bit acts as the general purpose output for the Error[0] pin. Software sets/
clears this bit to assert/deassert Error[0] pin. This bit applies only when
ERRPINCTL[1:0]=01; otherwise it is reserved.
0 = Deassert Error[0] pin
1 = Assert Error[0] pin