Datasheet

Datasheet, Volume 2 221

Processor Integrated I/O (IIO) Configuration Registers
3.3.6.9 RDINDEX—Alternate Index to read Indirect I/OxAPIC Register
3.3.6.10 RDWINDOW—Alternate Window to read Indirect 
I/OxAPIC Register
3RO 1b
No Soft Reset
This bit indicates I/OxAPIC does not reset its registers when transitioning from
D3hot to D0.
2RV0hReserved
1:0 RW-V 0h
Power State
This 2-bit field is used to determine the current power state of the function and to
set a new power state as well.
00 = D0
01 = D1 (not supported by IOAPIC)
10 = D2 (not supported by IOAPIC)
11 = D3_hot
If Software tries to write 01 or 10 to this field, the power state does not change
from the existing power state (which is either D0 or D3hot), nor do these bits 1:0
change value.
When in D3hot state, I/OxAPIC will
• respond to only Type 0 configuration transactions targeted at the device’s
configuration space, when in D3hot state
• will not respond to memory (That is, D3hot state is equivalent to MSE )
accesses to MBAR region.
Note: ABAR region access still go through in D3hot state, if it enabled.
• will not generate any MSI writes
RDINDEX
Bus: 0 Device: 5 Function: 4 Offset: 80
Bit Attr
Reset
Value
Description
7:0 RW 0h
Index
When PECI/JTAG wants to read the indirect RTE registers of I/OxAPIC, this
register is used to point to the index of the indirect register, as defined in the 
I/OxAPIC indirect memory space. Software writes to this register and then does a
read of the RDWINDOW register to read the contents at that index.
Note: Hardware does not preclude software from accessing this register over the
coherent interface, but that is not what this register is defined for.
RDWINDOW
Bus: 0 Device: 5 Function: 4 Offset: 90
Bit Attr
Reset
Value
Description
31:0 RO 0h
Window
When SMBUS/JTAG reads this register, the data contained in the indirect register
pointed to by the RDINDEX register is returned on the read.
PMCSR
Bus: 0 Device: 5 Function: 4 Offset: 70
Bit Attr
Reset
Value
Description