Datasheet

Datasheet, Volume 2 291
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Processor Uncore Configuration Registers
Table 4-9. Memory Controller DIMM Timing and Interleave Registers: Bus N, 
Device 15, Function 2–5 Offset 00h–FCh
DID VID 0h DIMMMTR_0 80h
PCISTS PCICMD 4h DIMMMTR_1 84h
CCR RID 8h DIMMMTR_2 88h
BIST HDR PLAT CLSR Ch
8Ch
10h TADCHNILVOFFSET_0 90h
14h TADCHNILVOFFSET_1 94h
18h TADCHNILVOFFSET_2 98h
1Ch TADCHNILVOFFSET_3 9Ch
20h TADCHNILVOFFSET_4 A0h
24h TADCHNILVOFFSET_5 A4h
28h TADCHNILVOFFSET_6 A8h
SDID SVID 2Ch TADCHNILVOFFSET_7 ACh
30h TADCHNILVOFFSET_8 B0h
CAPPTR 34h TADCHNILVOFFSET_9 B4h
38h TADCHNILVOFFSET_10 B8h
MAXLAT MINGNT INTPIN INTL 3Ch TADCHNILVOFFSET_11 BCh
PXPCAP 40h
C0h
44h C4h
48h C8h
4Ch CCh
50h D0h
54h D4h
58h D8h
5Ch DCh
60h E0h
64h E4h
68h E8h
6Ch ECh
70h F0h
74h F4h
78h F8h
7Ch FCh