Datasheet
Datasheet, Volume 2 63
Processor Integrated I/O (IIO) Configuration Registers
3.2.4.35 MSINXTPTR—MSI Next Pointer Register
3.2.4.36 MSIMSGCTL—MSI Control Register
MSINXTPTR
Bus: 0 Device: 0 Function: 0 Offset: 61h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 61h
Bus: 0 Device: 2 Function: 0–3 Offset: 61h
Bus: 0 Device: 3 Function: 0–3 Offset: 61h
Bit Attr
Reset
Value
Description
7:0 RW-O 90h
Next Ptr
This field is set to 90h for the next capability list (PCI Express capability structure)
in the chain.
0_3_0_Port3_NTB: Attr: RW-O; Reset Value: 80h
MSIMSGCTL
Bus: 0 Device: 0 Function: 0 Offset: 62h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 62h
Bus: 0 Device: 2 Function: 0–3 Offset: 62h
Bus: 0 Device: 3 Function: 1–3 Offset: 62h
Bit Attr
Reset
Value
Description
15:9 RV 0h Reserved
8RO 1b
Per-vector masking capable
This bit indicates that PCI Express ports support MSI per-vector masking.
7RO 0b
Bus 64-bit Address Capable
This field is hardwired to 0h since the message addresses are only 32-bit
addresses (fore example, FEEx_xxxxh).
6:4 RW 000b
Multiple Message Enable
Applicable only to PCI Express ports. Software writes to this field to indicate the
number of allocated messages, which is aligned to a power of two. When MSI is
enabled, the software will allocate at least one message to the device. A value of
000 indicates 1 message. Any value greater than or equal to 001 indicates a
message of 2.
See MSIDR for discussion on how the interrupts are distributed among the various
sources of interrupts based on the number of messages allocated by software for
the PCI Express ports.
3:1 RO 001b
Multiple Message Capable
The processor Express ports support two messages for all their internal events.
0RW0b
MSI Enable
Software sets this bit to select INTx style interrupt or MSI interrupt for root port
generated interrupts.
0 = INTx interrupt mechanism is used for root port interrupts, provided the
override bits in Section 3.2.4.86, “MISCCTRLSTS—Miscellaneous Control and
Status Register” on page 103) allow it.
1 = MSI interrupt mechanism is used for root port interrupts, provided the
override bits in MISCCTRLSTS allow it.
Bits 4:2 and bit 2 MISCCTRLSTS can disable both MSI and INTx interrupt from
being generated on root port interrupt events.