Datasheet

Datasheet, Volume 2 67
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.44 PXPCAP—PCI Express* Capabilities Register
PXPCAP
Bus: 0 Device: 0 Function: 0 Offset: 92h
Bus: 0 Device: 1 Function: 0–1 Offset: 92h
Bus: 0 Device: 2 Function: 0–3 Offset: 92h
Bus: 0 Device: 3 Function: 0–3 Offset: 92h 2
Bit Attr
Reset
Value
Description
15:14 RV 0h Reserved
13:9 RO 00h
Interrupt Message Number
This field applies to root ports. This field indicates the interrupt message number
that is generated for PM/HP/BW-change events. When there are more than one
MSI interrupt Number allocated for the root port MSI interrupts, this register field
is required to contain the offset between the base Message Data and the MSI
Message that is generated when there are PM/HP/BW-change interrupts. IIO
assigns the first vector for PM/HP/BW-change events and so this field is set to 0.
8RW-O 0b
Slot Implemented
This bit applies only to the root ports.
1 = Indicates that the PCI Express link associated with the port is connected to a
slot.
0 = Indicates no slot is connected to this port.
Notes:This register bit is of type “write once” and is set by BIOS.
7:4 RO 4h
Device/Port Type
This field identifies the type of device. It is set to 0100 for all the Express ports.
3:0 RW-O 2h
Capability Version
This field identifies the version of the PCI Express capability structure, which is 2h
as of now. This register field is left as RW-O to cover any unknowns with PCIe 3.0.