Datasheet

Processor Configuration Registers
162 Datasheet, Volume 2
1RW 0bUncore
SERR Enable (SERREN)
0 = No forwarding of error messages from secondary side to
primary side that could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result
in SERR message when individually enabled by the Root
Control register.
0RW 0bUncore
Parity Error Response Enable (PEREN)
This bit controls whether or not the Master Data Parity Error bit in
the Secondary Status register is set when the root port receives
across the link (upstream) a Read Data Completion Poisoned TLP.
0 = Master Data Parity Error bit in Secondary Status register can
NOT be set.
1 = Master Data Parity Error bit in Secondary Status register CAN
be set.
B/D/F/Type: 0/6/0/PCI
Address Offset: 3E–3Fh
Reset Value: 0000h
Access: RO, RW
Size: 16 bits
BIOS Optimal Default 0h
Bit Attr
Reset
Value
RST/
PWR
Description