Intel® Pentium® Dual-Core Processor Specification Update December 2010 Revision 010
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Contents Preface ...............................................................................................................................5 Summary Tables of Changes ..................................................................................................7 Identification Information .................................................................................................... 15 Errata ......................................................................................................
Revision History Document Number Revision Description 316515 -001 Initial release 316515 -002 • Added T2080 product SKU 316515 -003 • Updated erratum AN45 Date February 2007 March 2007 April 2007 • Updated Summary Table of Changes 316515 -004 • Updated Summary Table of Changes 316515 -005 • Added processors for the Mobile 965 Express Chipset Family July 2007 August 2007 • Added M-0 stepping errata 316515 -006 • Added Processors based on the Intel Mobile 965 series chipset.
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors. Errata may cause the products’ behavior to deviate from published specifications.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed Processor steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: A = Dual-Core Intel® Xeon® processor 7000Δ sequence C = Intel® Celeron® processor D = Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor Q6000 sequence AL = Dual-Core Intel® Xeon® processor 7100 Δ series AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® Dual-Core processor AO = Quad-Core Intel® Xeon® processor 3200Δ series AP = Dual-Core Intel® Xeon® processor 3000Δ series AQ = Intel® Pentium® Dual-Core Desktop processor E2000Δ sequence AR = Intel® Celeron® Processor 500Δ series AS = Intel® Xeon® processor
Summary Tables of Changes Number D0 M0 Plans ERRATA AN12 X Fixed FP Inexact-Result Exception Flag May Not Be Set AN13 X Fixed A Locked Data Access that Spans Across Two Pages May Cause the System to Hang AN14 X X No Fix MOV To/From Debug Registers Causes Debug Exception AN15 X X No Fix INIT Does Not Clear Global Entries in the TLB AN16 X Fixed Use of Memory Aliasing with Inconsistent Memory Type May Cause System Hang AN17 X Fixed Machine Check Exception May Occur when Interlea
Summary Tables of Changes Number D0 M0 Plans AN35 X X No Fix AN36 ERRATA Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unexpected Thermal Interrupts Erratum removed AN37 X AN38 X No Fix The Processor May Report a #TS Instead of a #GP Fault X Fixed BTS Message May be Lost when the STPCLK# Signal is Active AN39 X Fixed Certain Performance Monitoring Counters Related to Bus, L2 Cache and Power Management are Inaccurate AN40 X X No Fix A Write to an APIC Register S
Summary Tables of Changes Number D0 AN58 X AN59 X AN60 X AN61 AN62 M0 Plans ERRATA No Fix MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data after a Machine Check Exception (MCE) Fixed Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable Behavior X No Fix Code Breakpoint May Be Taken after POP SS Instruction if It Is Followed by an Instruction that Faults X X No Fix Incorrect Address Computed
Summary Tables of Changes Number D0 M0 Plans AN81 X X No Fix AN82 X AN83 AN84 AN85 AN86 AN87 AN88 AN89 AN90 X X X X X X X ERRATA Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions No Fix Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May Be Incorrect No Fix Erratum Removed No Fix Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions No Fix EIP May Be Incorrect after Shutdown in IA-32e Mode No Fix Upper 32
Summary Tables of Changes Number D0 AN105 M0 Plans ERRATA X No Fix BIST Failure after Reset AN106 X X No Fix Instruction Fetch May Cause a Livelock during Snoops of the L1 Data Cache AN107 X X No Fix Use of Memory Aliasing with Inconsistent Memory Type May Cause a System Hang or a Machine Check Exception AN108 X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations AN109 X X No Fix Using Memory Type Aliasing with Cacheable and WC Memory T
Identification Information Identification Information Component Marking Information Figure 1. Intel® Pentium® Dual-Core Mobile Processor on 65-nm Process (MicroFCPGA/FCBGA) S-Spec Markings Table 1. Pentium Dual-Core Mobile Processor on 65-nm Process Identification Information QDF/SSPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM (GHz) Notes SL9VX T2060 Micro-FCPGA D-0 06ECh 533 1.6/800 1 SL9VY T2080 Micro-FCPGA D-0 06ECh 533 1.
Identification Information Table 2. Pentium Dual-Core Mobile Processor on 65-nm Process Identification Information for 965 Express Chipset Family QDF/SSPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM (GHz) Notes SLAEC T2310 Micro-FCPGA M-0 06FDh 533 1.46/800 1 SLA4J T2370 Micro-FCPGA M-0 06FDh 533 1.73/800 1 SLA4K T2330 Micro-FCPGA M-0 06FDh 533 1.60/800 1 NOTES: 1. VCC_CORE=1.2125 V-1.025 V for HFM Range/LFM.
Errata Errata AN1. FST Instruction with Numeric and Null Segment Exceptions May Take Numeric Exception with Incorrect FPU Operand Pointer Problem: If execution of an FST (Store Floating Point Value) instruction would generate both numeric and Null segment exceptions, the numeric exceptions may be taken first and with the Null x87 FPU Instruction Operand (Data) Pointer.
Errata AN3. Erratum removed AN4. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Problem: Under certain conditions as described in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, the processor performs REP MOVS or REP STOS as fast strings.
Errata AN6. VM Bit Is Cleared on Second Fault Handled by Task Switch from Virtual-8086 (VM86) Problem: Following a task switch to any fault handler that was initiated while the processor was in VM86 mode, if there is an additional fault while servicing the original task switch then the VM bit will be incorrectly cleared in EFLAGS, data segments will not be pushed and the processor will not return to the correct mode upon completion of the second fault handler via IRET.
Errata AN9. LTR Instruction May Result in Unexpected Behavior Problem: Under certain circumstances an LTR (Load Task Register) instruction may result in an unexpected behavior if all the following conditions are met: 1. Invalid data selector of the TR (Task Register) resulting with either #GP (General Protection Fault) or #NP (Segment Not Present Fault). 2. GDT (Global Descriptor Table) is not 8-bytes aligned.
Errata AN12. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is not exactly represented in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit may not be set when this rounding occurs.
Errata AN13. A Locked Data Access that Spans across Two Pages May Cause the System to Hang Problem: An instruction with lock data access that spans across two pages may, given some rare internal conditions, hang the system. Implication: When this erratum occurs, the system may hang. Intel has not observed this erratum with any commercially available software or system. Workaround: A locked data access should always be aligned. Status: For the steppings affected, see the Summary Tables of Changes.
Errata AN16. Use of Memory Aliasing with Inconsistent Memory Type May Cause System Hang Problem: Software that implements memory aliasing by having more than one linear addresses mapped to the same physical page with different cache types may cause the system to hang. This would occur if one of the addresses is non-cacheable used in code segment and the other a cacheable address.
Errata AN18. Erratum removed AN19. Erratum removed AN20. LOCK# Asserted during a Special Cycle Shutdown Transaction May Unexpectedly Deassert Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is received during a snoop phase and the Locked transaction is pipelined on the front side bus (FSB), LOCK# may unexpectedly deassert. Implication: When this erratum occurs, the system may hang during shutdown.
Errata AN24. Disabling of Single-step on Branch Operation May Be Delayed following a POPFD Instruction Problem: Disabling of Single-step On Branch Operation may be delayed, if the following conditions are met: “Single Step On Branch Mode” is enabled (DebugCtlMSR.BTF and EFLAGS.TF are set) POPFD used to clear EFLAGS.TF A jump instruction (JMP, Jcc, etc.
Errata AN26.
Errata AN29. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store Instruction May Incorrectly Increment Performance Monitoring Count for Saturating SIMD Instructions Retired (Event CFh) Problem: Performance monitoring for Event CFH normally increments on saturating SIMD instruction retired. Regardless of DR7 programming, if the linear address of a retiring memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in DR3, the CFH counter may be incorrectly incremented.
Errata AN31. Data Breakpoint/Single Step on MOV SS/POP SS May Be Lost after Entry into SMM Problem: Data Breakpoint/Single Step exceptions are normally blocked for one instruction following MOV SS/POP SS instructions. Immediately after executing these instructions, if the processor enters SMM (System Management Mode), upon RSM (resume from SMM) operation, normal processing of Data Breakpoint/Single Step exceptions is restored.
Errata AN34. Pending x87 FPU Exceptions (#MF) following STI May Be Serviced before Higher Priority Interrupts Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag) instruction are serviced immediately after the STI instruction is executed.
Errata AN38. BTS Message May Be Lost When the STPCLK# Signal Is Active Problem: STPCLK# is asserted to enable the processor to enter a low-power state. Under some circumstances, when STPCLK# becomes active, a pending BTS (Branch Trace Store) message may be either lost and not written or written with corrupted branch address to the Debug Store area. Implication: BTS messages may be lost in the presence of STPCLK# assertions. Workaround: None identified.
Errata AN41. IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly Problem: The IO_SMI bit in SMRAM’s location 7FA4H is set to 1 by the CPU to indicate a System Management Interrupt (SMI) occurred as the result of executing an instruction that reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by: • A non-I/O instruction. • SMI is pending while a lower priority event interrupts • A REP I/O read • An I/O read that redirects to MWAIT.
Errata AN46. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment Selector” to SS and CS Registers Problem: According to the processor specification, attempting to load a Null segment selector into the CS and SS segment registers should generate a General Protection Fault (#GP). Although loading a Null segment selector to the other segment registers is allowed, the processor will generate an exception when the segment register holding a Null selector is used to access memory.
Errata AN48. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates real-address mode address wraparound at 1 megabyte. However, if all of the following conditions are met, address bit 20 may not be masked.
Errata AN50. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur it is possible that the load portion of the instruction will have executed before the exception handler is entered. 1. If an instruction that performs a memory load causes a code segment limit violation 2. If a waiting X87 floating-point instruction or MMX™ technology (MMX) instruction that performs a memory load has a floating-point exception pending 3.
Errata AN52. #GP Fault Is Not Generated on Writing IA32_MISC_ENABLE [34] When Execute Disable Bit Is Not Supported Problem: #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a processor which does not support Execute Disable Bit functionality. Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN53.
Errata AN55. Erratum removed AN56. Split Locked Stores May Not Trigger the Monitoring Hardware Problem: Logical processors normally resume program execution following the MWAIT, when another logical processor performs a write access to a WB cacheable address within the address range used to perform the MONITOR operation.
Errata AN58. MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data after a Machine Check Exception (MCE) Problem: When an MCE occurs during execution of a RDMSR instruction for MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock Count (IA32_MPERF), the current and subsequent RDMSR instructions for these MSRs may contain incorrect data.
Errata AN61. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4GB limit while the processor is operating in 32-bit mode.
Errata AN65. A Thermal Interrupt Is Not Generated When the Current Temperature Is Invalid Problem: When the DTS (Digital Thermal Sensor) crosses one of its programmed thresholds it generates an interrupt and logs the event (IA32_THERM_STATUS MSR (019Ch) bits [9,7]). Due to this erratum, if the DTS reaches an invalid temperature (as indicated IA32_THERM_STATUS MSR bit[31]) it does not generate an interrupt even if one of the programmed thresholds is crossed and the corresponding log bits become set.
Errata AN68. BTM/BTS Branch-From Instruction Address May Be Incorrect for Software Interrupts Problem: When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software interrupt may result in the overwriting of BTM/BTS branch-from instruction address by the LBR (Last Branch Record) branch-from instruction address. Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts. Workaround: None identified.
Errata AN72. Erratum removed AN73. Unaligned Accesses to Paging Structures May Cause the Processor to Hang Problem: When an unaligned access is performed on paging structure entries, accessing a portion of two different entries simultaneously, the processor may livelock. Implication: When this erratum occurs, the processor may live lock causing a system hang. Workaround: Do not perform unaligned access on paging structure entries.
Errata AN77. Performance Monitoring Events for Hardware Prefetch Requests (4EH) and Hardware Prefetch Request Cache Misses (4FH) May Not Be Accurate Problem: Performance monitoring events that count hardware prefetch requests and prefetch misses may not be accurate. Implication: This erratum may cause inaccurate counting for Hardware Prefetch Requests and Hardware Prefetch Request Cache Misses.
Errata AN81. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if only a small number of MMX instructions (including EMMS) are executed immediately after the last FP instruction, a FP to MMX transition may not be counted.
Errata AN84. Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions Problem: Many Performance Monitoring Events require core-specificity, which specifies which core’s events are to be counted (local core, other core, or both cores). Due to this erratum, some Bus Performance Monitoring events may not count when the corespecificity is set to the local core.
Errata AN87. Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to code execution, a #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced.
Errata AN90. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected.
Errata AN93. B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint Problem: B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly cleared when the following sequence happens: 1. POP instruction to SS (Stack Segment) selector. 2. Next instruction is FP (Floating Point) that gets FP assist followed by code breakpoint. Implication: B0-B3 bits in DR6 may not be properly cleared. Workaround: None identified.
Errata AN96. Erratum removed AN97. Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL Is Counted Incorrectly for PMULUDQ Instruction Problem: Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL (Event select 0B3H, Umask 01H) counts the number of SIMD packed multiply micro-ops executed. The count for PMULUDQ micro-ops might be lower than expected. No other instruction is affected. Implication: The count value returned by the performance monitoring event SIMD_UOP_TYPE_EXEC.
Errata AN99. Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to both code #DB (Debug Exception) and code Segment Limit Violation #GP (General Protection Fault).
Errata AN101. A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware Problem: The MONITOR instruction is used to arm the address monitoring hardware for the subsequent MWAIT instruction. The hardware is triggered on subsequent memory store operations to the monitored address range. Due to this erratum, REP STOS/MOVS fast string operations to the monitored address range may prevent the actual triggering store to be propagated to the monitoring hardware.
Errata AN104. Erratum removed AN105. BIST Failure after Reset Problem: The processor may show an erroneous BIST (built-in self test) result in bit [17] of EAX register when coming out of reset. Implication: When this erratum occurs, an erroneous BIST failure will be reported in EAX bit [17]. This failure can be ignored since it is not accurate. Workaround: It is possible for BIOS to workaround this erratum by masking off bit [17] of the EAX register after coming out of reset.
Errata AN107. Use of Memory Aliasing with Inconsistent Memory Type May Cause a System Hang or a Machine Check Exception Problem: Software that implements memory aliasing by having more than one linear addresses mapped to the same physical page with different cache types may cause the system to hang or to report a machine check exception (MCE). This would occur if one of the addresses is non-cacheable and used in a code segment and the other is a cacheable address.
Errata AN109. Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations Problem: Memory type aliasing occurs when a single physical page is mapped to two or more different linear addresses, each with different memory types. Memory type aliasing with a cacheable memory type and WC (write combining) may cause the processor to perform incorrect operations leading to memory ordering violations for WC operations.
Errata AN112 A 64-bit Register IP-relative Instruction May Return Unexpected Results Problem: Under an unlikely and complex sequence of conditions in 64-bit mode, a register IPrelative instruction result may be incorrect Implication: A register IP-relative instruction result may be incorrect and could cause software to read from or write to an incorrect memory location. This may result in an unexpected page fault or unpredictable system behavior.
Specification Changes Specification Changes There are no specification changes in this specification update revision.
Specification Clarifications Specification Clarifications There are no specification clarifications in this specification update revision.
Documentation Changes Documentation Changes There are no documentation changes in this specification update revision. Documentation changes for the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volumes 1, 2A, 2B, 3A and 3B will be posted in a separate document, Intel® 64 and IA-32 Architectures Optimization Reference Manual Documentation Changes.
