Specification Update

Summary Tables of Changes
14 Specification Update
Number D0 M0 Plans ERRATA
AN105 X No Fix BIST Failure after Reset
AN106 X X No Fix
Instruction Fetch May Cause a Livelock during Snoops of the L1
Data Cache
AN107 X X No Fix
Use of Memory Aliasing with Inconsistent Memory Type May Cause a
System Hang or a Machine Check Exception
AN108 X X No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
AN109 X X No Fix
Using Memory Type Aliasing with Cacheable and WC Memory Types
May Lead to Memory Ordering Violations
AN110 X No Fix
RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
AN111 X X Plan Fix NMIs May Not Be Blocked by a VM-Entry Failure
AN112 X X No Fix
A 64-bit Register IP-relative Instruction May Return Unexpected
Results
Number SPECIFICATION CHANGES
There are no Specification Changes in this Specification Update revision.
Number SPECIFICATION CLARIFICATIONS
There are no Specification Clarifications in this Specification Update revision.
Number DOCUMENTATION CHANGES
There are no Documentation Changes in this Specification Update revision.
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