Intel386™ EX Embedded Microprocessor User’s Manual Intel386™ EXTB Embedded Microprocessor Intel386™ EXTC Embedded Microprocessor
Intel386™ EX Embedded Microprocessor User’s Manual 1996
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CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 1.2 NOTATIONAL CONVENTIONS..................................................................................... 1-3 1.3 SPECIAL TERMINOLOGY ............................................................................................ 1-4 1.4 RELATED DOCUMENTS ........................................................................................
Intel386™ EX MICROPROCESSOR USER’S MANUAL 4.5.2 Enabling and Disabling the Expanded I/O Space .....................................................4-8 4.5.2.1 Programming REMAPCFG Example ...................................................................4-8 4.6 ADDRESSING MODES ................................................................................................. 4-9 4.6.1 DOS-compatible Mode ..............................................................................................4-9 4.6.
CONTENTS 6.3.4 Interrupt Acknowledge Cycle ..................................................................................6-23 6.3.5 Halt/Shutdown Cycle ...............................................................................................6-26 6.3.6 Refresh Cycle .........................................................................................................6-28 6.3.7 BS8 Cycle .............................................................................................................
Intel386™ EX MICROPROCESSOR USER’S MANUAL 7.3.4.2 SMRAM State Dump Area .................................................................................7-14 7.3.5 Resume Instruction (RSM) ......................................................................................7-15 7.4 THE Intel386 EX PROCESSOR IDENTIFIER REGISTERS ....................................... 7-15 7.5 PROGRAMMING CONSIDERATIONS........................................................................ 7-16 7.5.
CONTENTS 9.3.3 Initialization Command Word 1 (ICW1) ...................................................................9-20 9.3.4 Initialization Command Word 2 (ICW2) ...................................................................9-21 9.3.5 Initialization Command Word 3 (ICW3) ...................................................................9-22 9.3.6 Initialization Command Word 4 (ICW4) ...................................................................9-24 9.3.7 Operation Command Word 1 (OCW1) ....
Intel386™ EX MICROPROCESSOR USER’S MANUAL CHAPTER 11 ASYNCHRONOUS SERIAL I/O UNIT 11.1 OVERVIEW ................................................................................................................. 11-1 11.1.1 SIO Signals .............................................................................................................11-3 11.2 SIO OPERATION ........................................................................................................ 11-4 11.2.1 Baud-rate Generator .......
CONTENTS 12.2.4 Bus Control Arbitration ............................................................................................12-9 12.2.5 Ending DMA Transfers ..........................................................................................12-10 12.2.6 Buffer-transfer Modes ...........................................................................................12-12 12.2.6.1 Single Buffer-Transfer Mode ............................................................................12-12 12.2.
Intel386™ EX MICROPROCESSOR USER’S MANUAL 13.2.3 Receiver ................................................................................................................13-12 13.3 REGISTER DEFINITIONS......................................................................................... 13-16 13.3.1 Pin Configuration Register (PINCFG) ...................................................................13-17 13.3.2 SIO and SSIO Configuration Register (SIOCFG) ..............................................
CONTENTS 15.2.3 Refresh Addresses .................................................................................................15-4 15.2.4 Bus Arbitration ........................................................................................................15-5 15.3 RCU OPERATION ....................................................................................................... 15-5 15.4 REGISTER DEFINITIONS..........................................................................................
Intel386™ EX MICROPROCESSOR USER’S MANUAL CHAPTER 18 JTAG TEST-LOGIC UNIT 18.1 OVERVIEW ................................................................................................................. 18-1 18.2 TEST-LOGIC UNIT OPERATION................................................................................ 18-3 18.2.1 Test Access Port (TAP) ..........................................................................................18-3 18.2.2 Test Access Port (TAP) Controller ......................
CONTENTS APPENDIX D SYSTEM REGISTER QUICK REFERENCE D.1 PERIPHERAL REGISTER ADDRESSES..................................................................... D-1 D.2 CLKPRS ....................................................................................................................... D-7 D.3 CSnADH (UCSADH)..................................................................................................... D-8 D.4 CSnADL (UCSADL) ........................................................................
Intel386™ EX MICROPROCESSOR USER’S MANUAL D.37 D.38 D.39 D.40 D.41 D.42 D.43 D.44 D.45 D.46 D.47 D.48 D.49 D.50 D.51 D.52 D.53 D.54 D.55 D.56 D.57 D.58 D.59 D.60 D.61 D.62 D.63 D.64 D.65 D.66 D.67 D.68 D.69 D.70 D.71 D.72 D.73 D.74 xiv OCW1 (MASTER AND SLAVE).................................................................................. OCW2 (MASTER AND SLAVE).................................................................................. OCW3 (MASTER AND SLAVE)......................................
CONTENTS APPENDIX E INSTRUCTION SET SUMMARY E.1 INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY.................................. E-1 E.2 INSTRUCTION ENCODING ....................................................................................... E-22 E.2.1 32-bit Extensions of the Instruction Set ................................................................ E-23 E.2.2 Encoding of Instruction Fields ............................................................................... E-24 E.2.2.
Intel386™ EX MICROPROCESSOR USER’S MANUAL FIGURES Figure 2-1 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 xvi Page Intel386™ EX Embedded Processor Block Diagram ...................................................2-2 Instruction Pipelining ....................................................................................................
CONTENTS FIGURES Figure 6-16 6-17 6-18 6-19 7-1 7-2 7-3 7-4 7-5 7-6 7-7 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 10-1 10-2 10-3 10-4 10-5 10-6 Page Intel386 EX Processor to SRAM/FLASH Interface.....................................................6-41 Intel386 EX Processor to PSRAM Interface ...............................................................6-42 Intel386 EX Processor to Paged DRAM Interface............................
Intel386™ EX MICROPROCESSOR USER’S MANUAL FIGURES Figure 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 xviii Page Mode 1 – Writing a New Count.................................................................................10-10 Mode 2 – Basic Operation .................................................
CONTENTS FIGURES Figure 11-21 11-22 11-23 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 12-24 12-25 12-26 12-27 12-28 12-29 12-30 12-31 12-32 12-33 12-34 13-1 13-2 13-3 13-4 13-5 13-6 Page Modem Control Register (MCRn) .............................................................................11-30 Modem Status Register (MSRn)...............................................................................
Intel386™ EX MICROPROCESSOR USER’S MANUAL FIGURES Figure 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 16-1 16-2 16-3 16-4 16-5 16-6 17-1 17-2 17-3 xx Page SSIO Transmitter with Autotransmit Mode Disabled ..................................................13-8 Transmit Data by Polling ......................................................................................
CONTENTS FIGURES Figure 17-4 17-5 18-1 18-2 18-3 18-4 18-5 18-6 B-1 B-2 E-1 Page WDT Reload Value Registers (WDTRLDH and WDTRLDL)....................................17-10 Power Control Register (PWRCON).........................................................................17-11 Test Logic Unit Connections ......................................................................................18-2 TAP Controller (Finite-State Machine)........................................................................
Intel386™ EX MICROPROCESSOR USER’S MANUAL TABLES Table 2-1 2-2 4-1 4-2 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 6-1 6-2 6-3 7-1 7-2 7-3 8-1 8-2 9-1 9-2 10-1 10-2 10-3 10-4 10-5 10-6 11-1 11-2 11-3 11-4 11-5 11-6 12-1 12-2 12-3 12-4 13-1 xxii Page PC-compatible Peripherals...........................................................................................2-3 Embedded Application-specific Peripherals .................................................................
CONTENTS TABLES Table 13-2 13-3 14-1 14-2 15-1 15-2 16-1 16-2 16-3 17-1 17-2 18-1 18-2 18-3 18-4 18-5 A-1 A-2 A-3 A-4 D-1 E-1 E-2 E-3 E-4 E-5 E-6 E-7 E-8 E-9 E-10 E-11 E-12 E-13 E-14 E-15 Page Maximum and Minimum Baud-rate Output Frequencies ............................................13-6 SSIO Registers.........................................................................................................13-16 CSU Signals ..................................................................................
1 GUIDE TO THIS MANUAL
CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the Intel386™ EX Embedded Processor. It is intended for use by hardware designers familiar with the principles of microprocessors and with the Intel386 processor architecture. This chapter is organized as follows: • • • • • • • Manual Contents (see below) 1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Chapter 9 — Interrupt Control Unit — describes the interrupt sources and priority options and explains how to program the interrupt control unit. Chapter 10 — Timer/Counter Unit — describes the timer/counters and their available count formats and operating modes. Chapter 11 — Asynchronous Serial I/O (SIO) Unit — explains how to use the universal asynchronous receiver/transmitters (UARTs) to transmit and receive serial data.
GUIDE TO THIS MANUAL 1.2 NOTATIONAL CONVENTIONS The following notations are used throughout this manual. # The pound symbol (#) appended to a signal name indicates that the signal is active low. Variables Variables are shown in italics. Variables must be replaced with correct values. New Terms New terms are shown in italics. See the Glossary for a brief definition of commonly used terms. Instructions Instruction mnemonics are shown in upper case.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Register Bits When the text refers to more that one bit, the range may appear as two numbers separated by a colon (example: 7:0 or 15:0). The first bit shown (7 or 15 in the example) is the most-significant bit and the second bit shown (0) is the least-significant bit. Register Names Register names are shown in upper case. If a register name contains a lowercase, italic character, it represents more than one register.
GUIDE TO THIS MANUAL Reserved Bits Reserved bits are not used in this device, but they may be used in future implementations. Follow these guidelines to ensure compatibility with future devices: • Avoid any software dependence on the state of undefined register bits. • Use a read-modify-write sequence to load registers. • Mask undefined bits when testing the values of defined bits. • Do not depend on the state of undefined bits when storing undefined bits to memory or to another register.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 1.5 ELECTRONIC SUPPORT SYSTEMS Intel’s FaxBack* service and application BBS provide up-to-date technical information. Intel also maintains several forums on CompuServe and offers a variety of information on the World Wide Web. These systems are available 24 hours a day, 7 days a week, providing technical information whenever you need it. 1.5.1 FaxBack Service FaxBack is an on-demand publishing system that sends documents to your fax machine.
GUIDE TO THIS MANUAL 7. Microprocessor, PCI, and peripheral catalog 8. Quality and reliability and change notification catalog 9. iAL (Intel Architecture Labs) technology catalog 1.5.2 Bulletin Board System (BBS) The bulletin board system (BBS) lets you download files to your computer. The application BBS has the latest ApBUILDER software, hypertext manuals and datasheets, software drivers, firmware upgrades, code examples, application notes and utilities, and quality and reliability data.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 1.7 PRODUCT LITERATURE You can order product literature from the following Intel literature centers. 1-800-548-4725 U.S. and Canada 708-296-9333 U.S. (from overseas) 44(0)1793-431155 Europe (U.K.
2 ARCHITECTURAL OVERVIEW
CHAPTER 2 ARCHITECTURAL OVERVIEW The Intel386™ EX embedded processor (Figure 2-1) is based on the static Intel386 SX processor. This highly integrated device retains those personal computer functions that are useful in embedded applications and integrates peripherals that are typically needed in embedded systems. The Intel386 EX processor provides a PC-compatible development platform in a device that is optimized for embedded applications.
Address Data Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Bus Interface Unit Chip-select Unit JTAG Unit Address Intel386™ CX Core Core Enhancements - A20 Gate - CPU Reset - SMM Data Clock and Power Management Unit DRAM Refresh Control Unit Watchdog Timer Unit Bus Monitor Asynchronous Serial I/O 2 channels (16450 compatible) Synchronous Serial I/O 1 channel, full duplex Timer/counter Unit 3 channels (82C54 compatible) I/O Ports INTR Interrupt Control Unit DMA Controller 2 channels (8237A comp
ARCHITECTURAL OVERVIEW 2.2 INTEGRATED PERIPHERALS The Intel386 EX processor integrates both PC-compatible peripherals (Table 2-1) and peripherals that are specific to embedded applications (Table 2-2). Table 2-1. PC-compatible Peripherals Name Description Interrupt Control Unit (ICU) Consists of two 82C59A programmable interrupt controllers (PICs) configured as master and slave. You may cascade up to six external 82C59A PICs to expand the external interrupt lines to 52.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 2-2. Embedded Application-specific Peripherals Name Description System Management Mode (SMM) The Intel386 EX processor provides a mechanism for system management with a combination of hardware and CPU microcode enhancements. An externally generated system management interrupt (SMI#) allows the execution of system-wide routines that are independent and transparent to the operating system.
3 CORE OVERVIEW
CHAPTER 3 CORE OVERVIEW The Intel386™ EX processor core is based upon the Intel386 CX processor, which is an enhanced version of the Intel386 SX processor. This chapter describes the Intel386 CX processor enhancements over the Intel386 SX processor, internal architecture of the Intel386 CX processor, and the core interface on the Intel386 EX processor.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 3.2 Intel386 CX PROCESSOR INTERNAL ARCHITECTURE The internal architecture of the Intel386 CX processor consists of functional units that operate in parallel. Fetching, decoding, execution, memory management and bus accesses for several instructions are performed simultaneously. This parallel operation is called pipelined instruction processing.
CORE OVERVIEW Figure 3-2 shows the internal architecture of the Intel386 CX processor.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The six functional units of the Intel386 CX processor are: • • • • • • Core Bus Unit Instruction Prefetch Unit Instruction Decode Unit Execution Unit Segmentation Unit Paging Unit 3.2.1 Core Bus Unit The Core Bus Unit provides the interface between the processor and its environment. It accepts internal requests for instruction fetches (from the Instruction Prefetch Unit) and data transfers (from the Execution Unit), and prioritizes the requests.
CORE OVERVIEW 3.2.4 Execution Unit The Execution Unit executes the instructions from the Instruction Queue and therefore communicates with all other units required to complete the instruction. The functions of its three subunits are given below. • The Control Unit contains microcode and special parallel hardware that speeds multiply, divide, and effective address calculation.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 3.3 CORE Intel386 EX PROCESSOR INTERFACE The Intel386 EX processor peripherals are connected to the Intel386 CX processor core through an internal Bus Interface Unit (BIU). The BIU controls internal peripheral accesses and external memory and I/O accesses.
4 SYSTEM REGISTER ORGANIZATION
CHAPTER 4 SYSTEM REGISTER ORGANIZATION This chapter provides an overview of the system registers incorporated in the Intel386™ EX processor, focusing on register organization from an address architecture viewpoint. The chapters that cover the individual peripherals describe the registers in detail. This chapter is organized as follows: • • • • • • • 4.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL — Power management control registers — Chip-select unit control registers — Refresh control unit registers — Watchdog timer control registers — Synchronous serial I/O control registers — Parallel I/O port control registers 4.1.1 Intel386 Processor Core Architecture Registers These registers are a superset of the 8086 and 80286 processor registers. All 16-bit 8086 and 80286 registers are contained within the 32-bit Intel386 processor core registers.
SYSTEM REGISTER ORGANIZATION FFFFH (64K) General Slot I/O FD00H Platform I/O (Reserved) FC00H (63K) 0C00H (3K) General Slot I/O 0900H Platform I/O (Reserved) 0800H (2K) General Slot I/O 0500H Platform I/O (Reserved) 0400H (1K) General Slot I/O 0100H (256) Platform I/O (Reserved) 0000H (0) A2498-01 Figure 4-1. PC/AT I/O Address Space (10-bit Decode) 4.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL (See Figure 4-2.) Thus, each slot has 1 Kbyte addresses (in four 256-byte segments) that can potentially contain extended peripheral registers.
SYSTEM REGISTER ORGANIZATION The Intel386 EX processor uses slot 15 for the registers needed for integrated peripherals. Using this slot avoids conflicts with other devices in an EISA system, since EISA systems typically do not use slot 15. 4.4 ORGANIZATION OF PERIPHERAL REGISTERS The registers associated with the integrated peripherals are physically located in slot 15 of the I/O space. There are sixteen 4 Kbyte address slots in I/O space. Slot 0 refers to 0H–0FFFH; slot 15 refers to 0F000H–0FFFFH.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 4.5 I/O ADDRESS DECODING TECHNIQUES One of the key features of the Intel386 EX processor is that it is configurable for compatibility with the standard PC/AT architecture. In a PC/AT system, the platform I/O resources are located in the slot 0 I/O address space.
SYSTEM REGISTER ORGANIZATION Address Configuration Register REMAPCFG Expanded Addr: PC/AT Address: Reset State: 0022H 0022H 0000H 15 8 ESE — — — — — — — — S1R S0R ISR IMR DR — TR 7 0 Bit Number Bit Mnemonic Function 15 ESE 0 = Disables expanded I/O space 1 = Enables expanded I/O space 14–7 — Reserved.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 4.5.2 Enabling and Disabling the Expanded I/O Space The Intel386 EX processor’s expanded I/O space is enabled by a specific write sequence to I/O addresses 22H and 23H (Figure 4-4).
SYSTEM REGISTER ORGANIZATION 4.6 ADDRESSING MODES Combinations of the value of ESE bit and the individual remap bits in the REMAPCFG register yield four different peripheral addressing modes for I/O address decoding. 4.6.1 DOS-compatible Mode DOS-compatible mode is achieved by clearing ESE and all the peripheral remap bits. In this mode, all PC/AT-compatible peripherals are mapped into the DOS I/O space. Only address lines A9:0 are decoded for internal peripherals.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 3FFH On-chip UART-0 On-chip UART-1 FFFFH On-chip 8259A-2 On-chip Timer REMAPCFG Register 23H 0 22H 0 0 0 0 0 0 0 0 0 F000H On-chip 8259A-1 On-chip DMA 0H DOS I/O Space Expanded I/O Space Note: Shaded area indicates that expanded I/O space peripherals are not accessible A2495-02 Figure 4-5.
SYSTEM REGISTER ORGANIZATION 4.6.2 Nonintrusive DOS Mode This mode is achieved by first setting the ESE bit (using the three sequential writes), setting the individual peripherals’ remap bits, and then clearing the ESE bit. Peripherals whose remap bits are set are mapped out of DOS I/O space. Like DOS-compatible mode, only address lines A9:0 are decoded internally. This mode is useful for connecting an external peripheral instead of using the integrated peripheral.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 3FFH On-chip UART-0 On-chip UART-1 FFFFH On-chip 8259A-2 On-chip Timer REMAPCFG Register 23H 0 22H 0 0 0 0 0 0 1 0 0 F000H On-chip 8259A-1 Internal DMA 0H DOS I/O Space Expanded I/O Space Note: Shaded area indicates that the on-chip DMA and expanded I/O space peripherals are not accessible A2496-02 Figure 4-6.
SYSTEM REGISTER ORGANIZATION 3FFH On-chip UART-2 On-chip UART-1 FFFFH Other Peripherals UART-0 On-chip 8259A-2 UART-1 Timer On-chip Timer 8259A-2 REMAPCFG Register 0 23H 1 22H 0 0 0 0 8259A-1 0 0 On-chip 8259A-1 0 On-chip DMA 0 F000H Expanded I/O Space On-chip DMA 0H DOS I/O Space A2501-02 Figure 4-7.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 3FFH FFFFH Other Peripherals UART-0 UART-1 Timer 8259A-2 REMAPCFG Register 23H 1 22H 0 0 1 1 1 8259A-1 1 1 0 1 On-chip DMA F000H Expanded I/O Space 0H DOS I/O Space A2502-02 Figure 4-8.
SYSTEM REGISTER ORGANIZATION 4.7 PERIPHERAL REGISTER ADDRESSES Table 4-2 lists the addresses and names of all user-accessible peripheral registers. I/O Registers can be accessed as bytes or words. Word accesses to byte registers result in two sequential 8-bit I/O transfers. The default (reset) value of each register is shown in the Reset Value column. An X in this column signifies that the register bits are undefined.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 4-2.
SYSTEM REGISTER ORGANIZATION Table 4-2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 4-2.
SYSTEM REGISTER ORGANIZATION Table 4-2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 4-2.
5 DEVICE CONFIGURATION
CHAPTER 5 DEVICE CONFIGURATION The Intel386™ EX processor provides many possible signal to pin connections as well as peripheral to peripheral connections. This chapter describes the available configurations and how to configure them. This chapter is organized as follows: • • • • • Introduction (see below) Peripheral Configuration (page 5-3) Pin Configuration (page 5-23) Device Configuration Procedure (page 5-28) Configuration Example (page 5-28) 5.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Figure 5-1 shows Peripheral A and its connections to other peripherals and the package pins. The “Internal Connection Logic” provides three kinds of connections: • Connections between peripherals • Connections to package pins via multiplexers • Direct connections to package pins without multiplexers The internal connection logic is controlled by the Peripheral A configuration register.
DEVICE CONFIGURATION 5.2 PERIPHERAL CONFIGURATION This section describes the configuration of each on-chip peripheral. For more detailed information on the peripheral itself, see the chapter describing that peripheral. The symbology used for signals that share a device pin is shown in Figure 5-2. Of the two signal names by a pin, the upper signal is associated with the peripheral in the figure. The lower signal in parentheses is the alternate signal, which connects to a different peripheral or the core.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL configured DMA channel. SIO and SSIO inputs to the DMA are selected by the DMA configuration register (Figure 5-3). 5.2.1.3 Using The Timer To Initiate DMA Transfers A timer output (OUT1, OUT2) can initiate periodic data transfers by the DMA. A DMA channel is programmed for the transfer, then a timer output pulse triggers the transfer.
DEVICE CONFIGURATION DMACFG.2:0 DMA 3 DREQ0 0 1 2 3 4 5 6 7 RBFDMA0 (SIO0) TXEDMA1 (SIO1) SSTBE (SSIO) OUT1 (TCU) RBFDMA1 (SIO1) TXEDMA0 (SIO0) SSRBF (SSIO) To SIO1 DMACFG.3 0 DMAACK0# From CSU DRQ0 (DCD1#)† PINCFG.4 1 DACK0# (CS5#) DMACFG.6:4 3 DREQ1 0 1 2 3 4 5 6 7 RBFDMA1 (SIO1 ) TXEDMA0 (SIO0) SSRBF (SSIO) OUT2 (TCU) RBFDMA0 (SIO0) TXEDMA1 (SIO1) SSTBE (SSIO) To SIO1 DRQ1 (RXD1) DMACFG.7 0 DMAACK1# From SIO1 To ICU DMAINT PINCFG.2 1 0 PINCFG.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DMA Configuration DMACFG (read/write) Expanded Addr: ISA Addr: Reset State: F830H — 00H 7 0 D1MSK Bit Number 7 D1REQ2 D1REQ1 D1REQ0 D0MSK Bit Mnemonic D1MSK D0REQ2 D0REQ1 D0REQ0 Function DMA Acknowledge 1 Mask: 0 = DMA channel 1’s acknowledge (DMAACK1#) signal is not masked. 1 = Masks DMA channel 1’s acknowledge (DMAACK1#) signal. Useful when channel 1’s request (DREQ1) input is connected to an internal peripheral.
DEVICE CONFIGURATION 5.2.2 Interrupt Control Unit Configuration The interrupt control unit (ICU) comprises two 82C59A interrupt controllers connected in cascade, as shown in Figure 5-4. (See Chapter 9 for more information.) Figure 5-5 describes the interrupt configuration register (INTCFG).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 5-1. Master’s IR3 Connections Function IR3 connected to SIOINT1 P3.1 selected at pin (P3.1) IR3 connected to SIOINT1 OUT1 connected to pin (TMROUT1) IR3 internally driven low P3.1 selected at pin (P3.1) IR3 connected to pin (INT8) IR3 connected to SIOINT1 P3.1 selected at pin (P3.1) IR3 connected to SIOINT1 pin (INT8) must not be left floating NOTE: INTCFG.6 MCR1.3 P3CFG.1 0 X 0 0 X 1 1 0 0 1 0 1 1 1 0 1 1 1 INTCFG.5 MCR0.
DEVICE CONFIGURATION IR0 8259A Master IR1 IR2 INT INTR (to core) OUT0 (TCU) P3CFG.2 0 1 1 P3CFG.2 VSS To/From I/O Port 3 INTCFG.6 0 1 IR3 SIOINT1 OUT1(TCU) 0 1 IR4 0 MCR1.3 SIOINT1 1 1 INTCFG.6 0 1 INTCFG.5 SIOINT0 1 INT0 (P3.2)† P3CFG.1 0 P3.1 0 INT8 TMROUT1 (P3.1) MCR0.3 SIOINT0 P3GFG.0 1 INTCFG.5 INT9 1 TMROUT0 0 P3.0 OUT0(TCU) (P3.0) 0 1 P3CFG.3 INT1 (P3.3) To/From I/O Port 3 0 P3CFG.4 1 INT2 (P3.4) To/From I/O Port 3 0 0 P3CFG.3 IR5 0 1 VSS 0 1 VSS 0 1 VSS P3CFG.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Interrupt Configuration INTCFG (read/write) Expanded Addr: ISA Addr: Reset State: F832H — 00H 7 0 CE Bit Number 7 IR3 IR4 SWAP IR6 Bit Mnemonic CE IR5/IR4 IR1 IR0 Function Cascade Enable: 0 = Disables the cascade signals CAS2:0 from appearing on the A18:16 address lines during interrupt acknowledge cycles. 1 = Enables the cascade signals CAS2:0, providing access to external slave 82C59A devices.
DEVICE CONFIGURATION 5.2.3 Timer/counter Unit Configuration The three-channel Timer/counter Unit (TCU) and its configuration register (TMRCFG) are shown in Figure 5-6 and Figure 5-7. The clock inputs can be external signals (TMRCLK2:0) or the on-chip programmable clock (PSCLK). All clock inputs can be held low by programming bits in the TMRCFG register. The gate inputs can be controlled through software using TMRCFG.6 and the appropriate GTnCON bits in the TMRCFG register.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL TMRCFG.7 Timer/Counter Unit TMRCFG.0 PSCLK 0 CLKIN0 TMRCLK0 (INT4)† 1 TMRCFG.6 GATE0 TMRCFG.1 VCC 0 0 1 To ICU 1 TMRCFG.1 TMRGATE0 (INT5) To ICU To ICU P3CFG.0 1 OUT0 To/From I/O Port 3 TMRCFG.2 PSCLK 0 CLKIN1 0 TMRCLK1 (INT6) 1 TMRCFG.6 GATE1 To ICU TMRCFG.3 VCC 0 0 1 1 TMRCFG.3 TMRGATE1 (INT7) To ICU To ICU, DMA P3CFG.1 1 OUT1 To/From I/O Port 3 0 TMRCFG.4 CLKIN2 PSCLK 0 PINCFG.
DEVICE CONFIGURATION . Timer Configuration TMRCFG (read/write) Expanded Addr: ISA Addr: Reset State: F834H — 00H 7 TMRDIS Bit Number 7 0 SWGTEN GT2CON CK2CON GT1CON Bit Mnemonic TMRDIS CK1CON GT0CON CK0CON Function Timer Disable: 0 = Enables the CLKINn signals. 1 = Disables the CLKIN n signals. 6 SWGTEN Software GATEn Enable 0 = Connects GATE n to either the VCC pin or the TMRGATEn pin.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 5.2.4 Asynchronous Serial I/O Configuration Figures 5-8 and 5-9 show the asynchronous serial I/O unit configuration, consisting of channels SIO0 and SIO1. Each channel has one output (SIOINT0, SIOINT1) to the interrupt control unit (see Figure 5-4) and two outputs to the DMA unit. (These signals do not go to package pins.
DEVICE CONFIGURATION SIO0 SIOCFG.0 1 BCLKIN 1 SERCLK To/From I/O Port 3 SIOINT0 RBFDMA0 TXEDMA0 Transmit Data To ICU To DMA To DMA SIOCFG.6 1 P2CFG.6 1 0 P2CFG.7 To/From I/O Port 2 0 1 P1CFG.1 0 1 To/From I/O Port 1 DSR0# (P1.3) 0 1 P1CFG.0 DCD0# (P1.0) 0 To/From I/O Port 1 1 Data Terminal Ready 0 1 P1CFG.2 1 0 P1CFG.4 To/From I/O Port 1 VCC To/From I/O Port 1 DTR0# (P1.2) RI0# (P1.4) 0 1 RTS0# (P1.1) P1CFG.3 0 1 TXD0 (P2.6) CTS0# (P2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SIO1 SIOCFG.1 1 BCLKIN 1 SERCLK Receive Data To/From I/O Port 3 0 To ICU To DMA To DMA Transmit Data SIOCFG.7 1 PINCFG.2 1 0 PINCFG.3 From DMA 0 To/From DMA 1 0 1 Request to Send From SSIO Data Set Ready COMCLK (P3.7)† RXD1 (DRQ1) To DMA SIOINT1 RBFDMA1 TXEDMA1 Clear to Send P3CFG.7 0 0 TXD1 (DACK1#) CTS1# (EOP#) PINCFG.
DEVICE CONFIGURATION SIO and SSIO Configuration SIOCFG (read/write) Expanded Addr: ISA Addr: Reset State: F836H — 00H 7 0 S1M Bit Number 7 S0M Bit Mnemonic S1M — — — SSBSRC S1BSRC S0BSRC Function SIO1 Modem Signal Connections: 0 = Connects the SIO1 modem input signals to the package pins. 1 = Connects the SIO1 modem input signals internally. 6 S0M SIO0 Modem Signal Connections: 0 = Connects the SIO0 modem input signals to the package pins.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 5.2.5 Synchronous Serial I/O Configuration The synchronous serial I/O unit (SSIO) is shown in Figure 5-11. Its single configuration register bit is in the SIOCFG register (Figure 5-10). The transmit buffer empty and receive buffer full signals (SSTBE and SSRBF) go to the DMA unit (Figure 5-2), and an interrupt signal (SSIOINT) goes to the ICU (Figure 5-4).
DEVICE CONFIGURATION 5.2.6 Chip-select Unit and Clock and Power Management Unit Configuration Figure 5-12 shows the multiplexing of signals of the Chip-select Unit and the Clock and Power Management Unit. The Chip-select signals, CS6# and CS5# are multiplexed with the REFRESH# signal from the Refresh Control Unit and the DACK0# signal from the DMA Unit, respectively. Bits 6 and 4 in the PINCFG register (see Figure 5-15) control these multiplexers.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CSU 1 P2CFG.0 CS0# To/From I/O Port 2 0 1 P2CFG.1 CS1# To/From I/O Port 2 0 1 P2CFG.2 CS2# To/From I/O Port 2 To/From I/O Port 2 CS4# To/From I/O Port 2 0 1 P2CFG.4 0 1 PINCFG.4 CS5# DACK0# (DMA) REFRESH# (RCU) CS2# (P2.2) CS3# (P2.3) CS4# (P2.4) CS5# (DACK0#) 0 1 PINCFG.6 CS6# CS1# (P2.1) 0 1 P2CFG.3 CS3# CSO# (P2.0) CS6# (REFRESH#) 0 Clock and Power Management Unit 1 P3CFG.6 PWRDOWN To/From I/O Port 3 PWRDOWN (P3.
DEVICE CONFIGURATION 5.2.7 Core Configuration Three coprocessor signals (ERROR#, PEREQ, and BUSY# in Figure 5-13) can be routed to the core, as determined by bit 5 of the PINCFG register (see Figure 5-15). Due to signal multiplexing at the pins, the coprocessor and Timer/counter2 cannot be used simultaneously. PINCFG.5 Core 0 ERROR# PINCFG.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Setting bit 0 in the PORT92 register (see Figure 5-14) resets the core without resetting the peripherals. Unlike the RESET pin, which is asynchronous and can be used to synchronize internal clocks to CLK2, this core-only reset is synchronized with the on-chip clocks and does not affect the on-chip clock synchronization. After the CPU-RESET this bit is still set to 1. It must be cleared and then set to cause another core-only reset.
DEVICE CONFIGURATION 5.3 PIN CONFIGURATION Most of the microprocessor’s package pins support two peripheral functions. Some of these pins are routed to two peripheral inputs without the use of a multiplexer. These input-signal pairs are listed in Table 5-3. The pin is connected to both peripheral inputs. The remaining pins supporting two signals have multiplexers. For each such pin, a bit in a pin configuration register enables one of the signals.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Pin Configuration PINCFG (read/write) Expanded Addr: ISA Addr: Reset State: F826H — 00H 7 0 — Bit Number PM6 PM5 Bit Mnemonic 7 — 6 PM6 PM4 PM3 PM2 PM1 PM0 Function Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit. Pin Mode: 0 = Selects CS6# at the package pin. 1 = Selects REFRESH# at the package pin.
DEVICE CONFIGURATION Port 1 Configuration P1CFG (read/write) Expanded Addr: ISA Addr: Reset State: F820H — 00H 7 0 PM7 Bit Number 7 PM6 PM5 Bit Mnemonic PM7 PM4 PM3 PM2 PM1 PM0 Function Pin Mode: 0 = Selects P1.7 at the package pin. 1 = Selects HLDA at the package pin. 6 PM6 Pin Mode: 0 = Selects P1.6 at the package pin. 1 = Selects HOLD at the package pin. 5 PM5 Pin Mode: 0 = Selects P1.5 at the package pin. 1 = Selects LOCK# at the package pin. 4 PM4 Pin Mode: 0 = Selects P1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Port 2 Configuration P2CFG (read/write) Expanded Addr: ISA Addr: Reset State: F822H — 00H 7 0 PM7 Bit Number 7 PM6 PM5 Bit Mnemonic PM7 PM4 PM3 PM2 PM1 Function Pin Mode: 0 = Selects P2.7 at the package pin. 1 = Selects CTS0# at the package pin. 6 PM6 Pin Mode: 0 = Selects P2.6 at the package pin. 1 = Selects TXD0 at the package pin. 5 PM5 Pin Mode: 0 = Selects P2.5 at the package pin. 1 = Selects RXD0 at the package pin.
DEVICE CONFIGURATION Port 3 Configuration P3CFG (read/write) Expanded Addr: ISA Addr: Reset State: F824H — 00H 7 0 PM7 Bit Number 7 PM6 PM5 Bit Mnemonic PM7 PM4 PM3 PM2 PM1 PM0 Function Pin Mode: 0 = Selects P3.7 at the package pin. 1 = Selects COMCLK at the package pin. 6 PM6 Pin Mode: 0 = Selects P3.6 at the package pin. 1 = Selects PWRDOWN at the package pin. 5 PM5 Pin Mode: 0 = Selects P3.5 at the package pin. 1 = Connects master IR7 to the package pin (INT3).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 5.
DEVICE CONFIGURATION — Counter 2: Clock input is on-chip programmable clock (PSCLK); no signals connected to package pins • DMA Unit: — Not Used • Asynchronous Serial I/O channel 0 (SIO0): — Clock input is the internal clock SERCLK — RXD0, TXD0 connected to package pins — Modem Signals connected internally.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Bit # 7 P1CFG Value Bit # 0 7 0 = P1.7 1 = HLDA 6 0 = P1.6 0 6 0 = P1.5 0 5 0 = P1.4 0 4 0 = P1.3 0 3 0 = P1.2 0 2 0 = P1.1 0 1 6 0 = P2.5 0 = P2.4 0 = P2.3 0 = P2.2 0 = P2.1 0 = P1.0 0 0 0 = P2.0 1 5 Value 0 = P3.7 0 = P3.6 0 = P3.5 1 4 0 = P3.4 1 3 0 = P3.3 1 2 0 = P3.2 1 1 0 = P3.1 0 0 Pins w/o Muxes 0 = P3.
DEVICE CONFIGURATION Bit # 7 DMACFG 0 = Enables DACK1# at chip pin Value 1 1 = Disables DACK1# at chip pin 6–4 000 = DRQ1 pin (external peripheral) connected to DREQ1 000 001 = SIO channel 1’s receive buffer full signal (RBFDMA1) connected to DREQ1 010 = SIO channel 0’s transmit buffer empty signal (TXEDMA0) to DREQ1 011 =SSIO receive holding buffer full signal (SSRBF) to DREQ1 100 = TCU counter 2’s output signal (OUT2) to DREQ1 101 = SIO channel 0’s receive buffer full signal (RBFDMA0) to DREQ1 110
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Bit # 7 TMRCFG 0 = All clock inputs enabled Value 0 1 = CLK2, CLK1, CLK0 forced to 0 6 0 = Connects GATEn to either the VCC pin or the TMRGATE n pin 0 1 = Turns GATEn on or off, depending on whether bits 1, 3, and 5 are set or clear 5 0 = With bit 6 clear: VCC to GATE2; with bit 6 set: GATE2 off. 0 1 = With bit 6 clear: TMRGATE2 pin conn. to GATE2; with bit 6 set: GATE2 on.
DEVICE CONFIGURATION Bit # Value INTCFG 7 0 = CAS2:0 disabled to pins 0 6 0 = SIOINT1 connected to master IR3 5 0 = SIOINT0 connected to master IR4 4 0 = DMAINT connected to slave IR4. INT6 connected to slave IR5. 3 0 = VSS connected to slave IR6 2 0 = VSS connected to slave IR5 1 = CAS2:0 enabled from pins 0 1 = P3.1 connected to IR3 0 1 = P3.0 connected to IR4 1 1 = INT6 connected to slave IR4. DMAINT connected to slave IR5.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Bit # 7 P1CFG Value 0 = P1.7 Bit # 7 1 = HLDA 6 0 = P1.6 6 0 = P1.5 5 0 = P1.4 4 0 = P1.3 3 0 = P1.2 2 1 1 = RTS0# 0 6 0 = P1.0 0 0 = P2.5 5 0 = P2.4 4 3 0 = P3.5 0 = P3.4 0 = P3.3 1 = INT1 0 = P2.2 2 0 = P3.2 1 = INT0 0 = P2.1 1 0 = P3.1 1 = mux 0 = P2.0 Pins w/o Muxes 0 = P3.6 1 = INT2 0 = P2.3 Value 0 = P3.7 1 = INT3 0 1 = CS0# PINCFG 0 = P3.
DEVICE CONFIGURATION Bit # 7 DMACFG Value 0 = Enables DACK1# at chip pin 1 = Disables DACK1# at chip pin 6–4 000 = DRQ1 pin (external peripheral) connected to DREQ1 001 = SIO channel 1’s receive buffer full signal (RBFDMA1) connected to DREQ1 010 = SIO channel 0’s transmit buffer empty signal (TXEDMA0) to DREQ1 011 =SSIO receive holding buffer full signal (SSRBF) to DREQ1 100 = TCU counter 2’s output signal (OUT2) to DREQ1 101 = SIO channel 0’s receive buffer full signal (RBFDMA0) to DREQ1 110 = SIO c
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Bit # 7 TMRCFG 0 = All clock inputs enabled 1 = CLK2, CLK1, CLK0 forced to 0 6 0 = Connects GATEn to either the VCC pin or the TMRGATE n pin. 5 0 = With bit 6 clear: VCC to GATE2; with bit 6 set: GATE2 off. 1 = Turns GATEn on or off, depending on whether bits 1, 3, and 5 are set or clear. 1 = With bit 6 clear: TMRGATE2 pin conn. to GATE2; with bit 6 set: GATE2 on.
DEVICE CONFIGURATION Bit # INTCFG 7 0 = CAS2:0 disabled to pins 6 0 = SIOINT1 connected to master IR3 5 0 = SIOINT0 connected to master IR4 4 0 = DMAINT connected to slave IR4. INT6 connected to slave IR5. 3 0 = VSS connected to slave IR6 2 0 = VSS connected to slave IR5 Value 1 = CAS2:0 enabled from pins 1 = P3.1 connected to IR3 1 = P3.0 connected to IR4 1 = INT6 connected to slave IR4. DMAINT connected to slave IR5.
6 BUS INTERFACE UNIT
CHAPTER 6 BUS INTERFACE UNIT The processor communicates with memory, I/O, and other devices through bus operations. Address, data, status, and control information define a bus cycle. The Bus Interface Unit supports read and write cycles to external memory and I/O devices. It also contains the signals that allow external bus masters to request and acquire control of the bus.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • Data status pins indicate that data is available on the data bus for a write (WR#) or that the processor is ready to accept data for a read (RD#). These pins are available so that certain system configurations can easily connect the processor directly to memory or I/O without external logic.
BUS INTERFACE UNIT 6.1.1 Bus Signal Descriptions Table 6-1 describes the signals associated with the BIU. Table 6-1. Bus Interface Unit Signals (Sheet 1 of 2) Signal A25:1 Device Pin or Internal Signal only Device pins Description Address Bus: Outputs physical memory or I/O addresses. These signals are valid when ADS# is active and remain valid until the next T1, T2P, or Ti. ADS# Device pin Address Strobe: Indicates that the processor is driving a valid bus-cycle definition and address.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 6-1. Bus Interface Unit Signals (Sheet 2 of 2) Signal Device Pin or Internal Signal only Description M/IO# D/C# W/R# REFRESH# Device pins NA# Device pin Next Address: RD# Device pin Read Enable: Bus Cycle Definition Signals (Memory/IO, Data/Control, Write/Read, and Refresh): These four status outputs define the current bus cycle type, as shown in Table 6-2. Requests address pipelining.
BUS INTERFACE UNIT 6.2 BUS OPERATION The processor generates eight different types of bus operations: • • • • • • • • Memory data read (data fetch) Memory data write Memory code read (instruction fetch) I/O data read (data fetch) I/O data write Halt or shutdown Refresh Interrupt acknowledge These operations are defined by the states of four bus status pins: M/IO#, D/C#, W/R# and REFRESH#. Table 6-2 lists the various combinations and their definitions. Table 6-2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Cycle 1 Nonpipelined External (Write) [Late Ready] State T1 T2 Cycle 2 Nonpipelined External (Read) T1 Idle Cycle 3 Cycle Nonpipelined External (Write) [Late Ready] T2 Ti T1 T2 Cycle 4 Nonpipelined External (Read) T1 T2 CLK2 CLKOUT A25:1, BHE# BLE#, D/C# M/IO# Valid 1 Valid 2 Valid 3 Valid 4 Valid 1 Valid 2 Valid 3 Valid 4 REFRESH# W/R# WR# RD# ADS# NA# READY# LBA# BS8# LOCK# D15:0 Out 1 In 2 Out 3 In 4 A2305-02 Figure 6-1.
BUS INTERFACE UNIT 6.2.1 Bus States The processor uses a double-frequency clock input (CLK2). This clock is internally divided by two and synchronized to the falling edge of RESET (see Figure 8-2 in Chapter 8) to generate the internal processor clock signal. Each processor clock cycle is two CLK2 cycles wide. Each bus cycle is composed of at least two bus states: T1 and T2. Each bus state in turn consists of two CLK2 cycles, which can be thought of as Phase 1 (PH1) and Phase 2 (PH2) of the bus state.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Memory read and memory write cycles can be locked to prevent another bus master from using the local bus. This allows for indivisible read-modify-write operations. Reset Asserted READY# Asserted • No Request Always No Request Ti T1 Request Pending Bus States: T1 - First clock of a non-pipelined bus cycle (CPU drives new address and asserts ADS#). T2 - Subsequent clocks of a bus cycle when NA# has not been sampled asserted in the current bus cycle.
BUS INTERFACE UNIT NOTE Pipelining is also supported during memory cycles initiated by the two integrated DMA units. Refer to “Pipelined Cycle” on page 6-19 for a description of pipelined cycles. 6.2.3 Data Bus Transfers and Operand Alignment The processor can address up to 64 Mbytes (226 bytes, addresses 0000000H–3FFFFFFH) of physical memory and up to 64 Kbytes (216 bytes, addresses 0000H–FFFFH) of I/O. The device maintains separate physical memory and I/O spaces.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • A doubleword (32-bit) transfer at (byte) address 03H requires three transfers, one word transfer and two byte transfers: — The first word transfer activates word address 04H and uses D15:0 (to write or read the middle 2 bytes of the 32-bit doubleword) — The next transfer activates word address 06H and uses D7:0 (to write or read the upper byte of the 32-bit word) — The last transfer activates word address 02H and uses D15:8 (to write or read the lower by
BUS INTERFACE UNIT LBA# Bus Unit READY# To Internal Units Chip Boundary A2485-01 Figure 6-3. Ready Logic When an internal cycle occurs, the LBA# signal becomes active in Phase 1 of the first T2 state. It then stays active until the rising edge of PH1 of the first T2, T2i or T2P state of the next bus cycle that requires external READY# to terminate the bus cycle.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Figure 6-4 shows internal and external bus cycles.
BUS INTERFACE UNIT 6.3 BUS CYCLES The processor executes five types of bus cycles: • • • • • Read Write Interrupt Halt/shutdown Refresh 6.3.1 Read Cycle Read cycles are of two types: • In a pipelined cycle, the address and status signals are output in the previous bus cycle, to allow longer memory access times. Pipelined cycles are described in “Pipelined Cycle” on page 6-19. • In a nonpipelined cycle, the address and status signals become valid during the first T-state of the cycle (T1).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 3. When a chip-select region is enabled for the current read cycle but internal READY# generation is disabled for that region, and the Chip-select Unit is programmed to insert wait-states, the READY# signal is ignored (not sampled) by the processor until the programmed number of wait-states are inserted into the cycle. 4.
BUS INTERFACE UNIT Idle Ti Cycle 1 Non-pipelined External (Read) T1 T2 Cycle 2 Non-pipelined External (Read) T1 T2 Idle T2 Ti CLK2 CLKOUT BHE#, BLE#, A25:1 M/IO#, D/C# Valid1 Valid2 REFRESH# W/R# WR# RD# ADS# NA# READY# End Cycle End Cycle LBA# BS8# LOCK# D15:0 Valid1 Valid2 In1 In2 A2487-03 Figure 6-5.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.3.2 Write Cycle Write cycles are of two types: • Pipelined. Pipelined write cycles are described in “Pipelined Cycle” on page 6-19. • Nonpipelined. Figure 6-6 shows two nonpipelined write cycles (one with and one without a wait state). The sequence of signals for a nonpipelined write cycle is as follows: 1. The processor initiates the cycle by driving the address bus and the status signals active and asserting ADS#.
BUS INTERFACE UNIT 4. The WR# signal can be deasserted in two ways. • Early Ready: WR# is deasserted at the rising edge of CLK2 in the middle of the T2 state, after any wait states programmed in the Chip-select Unit have expired. At the rising edge of PH2, READY# is sampled. If it is found active, WR# is synchronously deasserted in the middle of T2, driven inactive by the rising edge of the PH2 clock. The write cycle is then terminated at the end of the T2 state.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Idle Ti Cycle 1 Nonpipelined External (Write) [Late Ready] T1 T2 Cycle 2 Nonpipelined External (Write) [Early Ready] T1 T2 T2 Valid1 Valid2 Idle Ti CLK2 CLKOUT BHE#, BLE#, A25:1 M/IO#, D/C# REFRESH# W/R# WR# RD# ADS# NA# READY# End Cycle 1 End Cycle 2 LBA# BS8# LOCK# D15:0 Valid 1 Out 1 Valid 2 Out 2 A2488-02 Figure 6-6.
BUS INTERFACE UNIT 6.3.3 Pipelined Cycle The pipelining feature of the processor is normally used to achieve zero-wait-state memory subsystems using devices that are slower than those in a zero-wait-state non-pipelined system. Pipelining allows bus cycles to be overlapped, increasing the amount of time available for the memory or I/O device to respond. The next address (NA#) input controls pipelining.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL HOLD Asserted READY# Asserted • HOLD Asserted RE A HO DY LD # A As sse se rte r HOLD Negated • ted d • Request Pending HO L No D N Re eg q u a te es d LD t • As se rte d Th HO Reset Asserted d • HOLD Negated • No Asserte Requ est DY# REA NA# Negated T2 READY# Asserted • HOLD Negated • Request Pending READY# Negated • NA# Negated T2i READY# Asserted • HOLD Negated • No Request Bus States: T1—first clock of a non-pipelined bus cycle.
BUS INTERFACE UNIT Cycle 1 Pipelined (Write) [Late Ready] T1P T2P T2P Cycle 2 Non-pipelined (Read) T1P T2 Cycle 3 Pipelined (Write) [Late Ready] T1P T2i T2P T2P Cycle 4 Pipelined (Read) T1P T2 CLK2 CLKOUT BHE#, BLE#, A25:1, M/IO#, D/C# Valid1 Valid2 Valid3 Valid4 ADS# is asserted as soon as the CPU has another bus cycle to perform, which is not always immediately after NA# is asserted. W/R# WR# RD# ADS# Note ADS# is asserted in every T2P state.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL In cycle 3, NA# is sampled in the first T-state (T1P); the address and status have been valid for one previous T-state and this is a new bus cycle. NA# is sampled active and — because a bus cycle (cycle 4) is pending internally — the address, byte enables, and bus status signals for this pending bus cycle (cycle 4) are driven during the next T2P state.
BUS INTERFACE UNIT A complete discussion of the considerations for using pipelining can be found in the Intel386™ SX Processor datasheet (order number 240187) or the Intel386™ SX Microprocessor Hardware Reference Manual (order number 240332). 6.3.4 Interrupt Acknowledge Cycle An interrupt causes the processor to suspend execution of the current program and execute instructions from another program called an interrupt service routine. Interrupts are described in Chapter 9.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL NOTE Since the CAS lines are invalid in the Ti states between the two interrupt acknowledge cycles, cascading of external 82C59A devices requires latching the CAS lines. This ensures that the CAS lines remain valid during these Ti states to fulfill the requirements of the external 82C59A devices. 2.
BUS INTERFACE UNIT Previous Interrupt Cycle Acknowledge Cycle 1 (Internal) T2 T1 T2 Idle (Four bus states) Ti Ti Ti Ti Interrupt Acknowledge Cycle 2 (Internal) T1 T2 Idle Ti Ti CLK2 CLKOUT BHE# BLE#, A25:A3, A1 M/IO#, D/C#, W/R# A2 WR# RD# ADS# READY# LBA# LOCK# A2490-03 Figure 6-9.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.3.5 Halt/Shutdown Cycle The halt condition occurs in response to a HALT instruction. The shutdown condition occurs when the processor is processing a double fault and encounters a protection fault; the processor cannot recover and therefore, shuts down. Externally, a shutdown cycle differs from a halt cycle only in the resulting address bus outputs. The sequence of signals for a halt cycle is as follows: 1.
BUS INTERFACE UNIT Cycle 1 Nonpipelined (Write) [Late Ready] T1 T2 Idle Cycle 2 Nonpipelined (Halt) T1 T2 Ti Ti Ti Ti CLK2 CLKOUT BHE#, A1, M/IO#, W/R# Valid 1 CPU remains halted until INTR, SMI#, NMI, or RESET is asserted. A25:2, BLE#, D/C# Valid 1 CPU responds to HOLD input while in the HALT state. WR# RD# ADS# NA# READY# † LBA# LOCK# D15:0 Valid 1 Valid 2 Out Undefined Float † HALT cycle must be acknowledged by READY# asserted.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.3.6 Refresh Cycle The refresh control unit simplifies dynamic memory controller design by issuing dummy read cycles at specified intervals. (For more information, refer to Chapter 15, “REFRESH CONTROL UNIT.”) Figure 6-11 shows a basic refresh cycle. The sequence of signals for a refresh cycle is as follows: 1. 2. Like a read cycle, the refresh cycle is initiated by asserting ADS# and completed by asserting READY#.
BUS INTERFACE UNIT Idle Ti Cycle 1 Nonpipelined External (Read) T1 Cycle 2 Idle Idle Cycle 3 Nonpipelined External (Write) [Late Ready] Refresh T2 Ti T1 T2 T2 Ti Ti T1 T2 CLK2 CLKOUT BHE#, BLE# M/IO#, D/C# Valid 1 A25:1 Valid 1 Valid 3 Valid 2 Valid 3 REFRESH# W/R# WR# RD# ADS# NA# READY# LBA# LOCK# D15:0 Valid 1 Valid 2 In Float Out HOLD HLDA A2491-02 Figure 6-11.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Idle Ti HOLD Acknowledge Th Th Th Idle Ti T1 T2 HOLD Acknowledge Idle Cycle 1 Refresh Ti Ti Th Th CLK2 CLKOUT BHE#, BLE# M/IO#, D/C# Floating Floating REFRESH# A25:1 W/R# Floating Valid 1 Floating Floating Floating Floating Floating WR# RD# ADS# NA# READY# LBA# LOCK# Floating D15:0 HOLD HLDA Due to refresh pending. A2493-02 Figure 6-12.
BUS INTERFACE UNIT 6.3.7 BS8 Cycle The BS8 cycle allows external logic to dynamically switch between an 8-bit data bus size and a 16-bit data bus size, by using the BS8# signal. Figure 6-13 shows a word access to an 8-bit peripheral. To use the dynamic 8-bit bus sizing, an external memory or I/O should connect to the lower eight bits of the data bus (D7:0), use the BLE# as address bit 0, and assert BS8# (at the BS8# pin) in T2 of a memory or I/O access.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The BS8 cycle generates additional bus cycles for read and write cycles only. For interrupt and halt/shutdown cycles, the accesses are byte wide and the BS8# signal is ignored. For a refresh cycle, the byte enables are both disabled and the BS8# signal is ignored. NOTE If a BS8 cycle requires an additional bus cycle, the processor retains the current address for the second cycle.
BUS INTERFACE UNIT State Low Byte Write High Byte Write [Late Ready] [Late Ready] T1 T2 T1 T2 Low Byte Read High Byte Read T1 T1 T2 T2 Idle Cycles Ti Ti CLK2 CLKOUT A25:1 M/IO# D/C# Valid 2 Valid 1 BLE# BHE# W/R# WR# RD# ADS# NA# Must be high READY# BS8# LOCK# D15:8 D7:0 Valid 1 Valid 2 Data Out High Data Out Low Data Out High Data In Low Data In High A3375-01 Figure 6-13.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.4 BUS LOCK In a system in which more than one device (a bus master) may control the local bus, locked cycles are used to make sequential bus cycles indivisible. Otherwise, the cycles may be separated by a cycle from another bus master. Any bus cycles that must be performed back-to-back, without any intervening bus cycles by other bus masters, must be locked. The use of a semaphore is one example of this concept.
BUS INTERFACE UNIT Unlocked Bus Cycle Locked Bus Cycle Locked Bus Cycle Unlocked Bus Cycle CLKOUT Address Asserted BLE#, BHE#, A25:1 LOCK Deasserted LOCK# READY# A2489-02 Figure 6-14. LOCK# Signal During Address Pipelining 6.4.3 LOCK# Signal Duration The maximum duration of the LOCK# signal affects the maximum HOLD request latency because HOLD is recognized only after LOCK# goes inactive. The duration of LOCK# depends on the instruction being executed and the number of wait states per cycle.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.5.1 HOLD/HLDA Timing To gain control of the local bus, the requesting bus master drives the HOLD input active. This signal can be asynchronous to the processor’s CLK2 input.
BUS INTERFACE UNIT • NMI pin - The request is recognized and latched. It is serviced after HOLD is released. • SMI# pin - The request is recognized and latched. It is serviced after HOLD is released. 6.5.2 HOLD Signal Latency Because other bus masters may be used in time-critical applications, the amount of time the bus master must wait for bus access (HOLD latency) can be a critical design consideration.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.6 DESIGN CONSIDERATIONS • Upon reset, UCS# is configured as a 16-bit chip-select signal. If the Boot device is only an 8-bit device, then BS8# must be asserted whenever UCS# is active (until the UCS region can be reprogrammed to reflect an 8-bit region). One way of doing this is by connecting the UCS# pin directly to the BS8# pin, if there are no other devices that need to use the BS8# pin.
BUS INTERFACE UNIT 6.6.1.1 System Configuration The Intel387 SX Math Coprocessor can be interfaced to the Intel386 EX embedded processor as shown in Figure 6-15. 16 W/R# ADS# M/IO# A23 A2 W/R# ADS# NPS1# NPS2 CMD0# Clock Generator CLK2 CPUCLK2 RESET RESETIN D15:0 Synchronous Reset BUSY# PEREQ ERROR# READY# BUSY# CKM PEREQ STEN ERROR# READY# LBA# NUMCLK2 VCC D15:0 READYO# Intel386™ 80386EXEX Embedded Processor Intel387™ 80387SXSX Math Coprocessor A2852-02 Figure 6-15.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The interface has these characteristics: • The Intel387 SX Math Coprocessor shares the local bus of the Intel386 EX processor. • The Intel386 EX processor and Intel387 SX Math Coprocessor share the same reset signals. They also share the same clock input. • The corresponding BUSY#, ERROR#, and PEREQ pins are connected together. • The Status Enable (STEN) selects the math coprocessor. It causes the chip to recognize other chip select inputs.
BUS INTERFACE UNIT Also, bit 5 in the PINCFG register (Figure 5-15 on page 5-24) must be cleared, to connect the coprocessor-related signals of the core to the package pins. Below is an example of a simple routine that can be executed using the math-coprocessor: fninit fldpi fld1 fadd fist 6.6.2 ;; ;; ;; ;; ;; ;; word ptr [di] Initialize Math Coprocessor Load (Push on to the 387 stack) “Pi” Load (Push on to the 387 stack) “1” Add the two values, i.e.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.6.3 PSRAM Interface Pseudo SRAM (PSRAM) devices can be easily interfaced (Figure 6-17) to the Intel386 EX processor. PSRAM devices have an interface that is similar to SRAM devices (They are also pincompatible in many cases). The two major differences between PSRAM and SRAM devices are: • PSRAM devices require a CE# precharge (inactive) time between access cycles.
BUS INTERFACE UNIT 6.6.4 Paged DRAM Interface External logic is required to interface the Intel386 EX processor to DRAM devices, as shown in Figure 6-18. The PLD generates the RAS# and CAS# signals. If RAS#-Only Refresh is being performed (using the Refresh Control Unit of the processor), then during a Refresh Cycle, the PLD enables the Column Address Buffer and asserts the RAS# signal (shaded sections in the figure). Refer to Chapter 6, “BUS INTERFACE UNIT,” for more information.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.6.5 Non-Paged DRAM Interface This interface is similar to the Paged DRAM Interface, except that in this case, the lower address bits are routed to the Row Address Buffer and the higher address bits to the Column Address Buffer. This is done to simplify the RAS#-Only Refresh logic. The PLD in this case enables the Row Address Buffer and asserts the RAS# signal (shaded sections in the figure) during a Refresh Cycle.
7 SYSTEM MANAGEMENT MODE
CHAPTER 7 SYSTEM MANAGEMENT MODE The Intel386™ EX processor provides a mechanism for system management with a combination of hardware and CPU microcode enhancements. For low power systems, the primary function of SMM is to provide a transparent means for power management. For systems where power management is not critical, SMM may be used for other functions such as alternate operating systems, debuggers, hard disk drive backup, or virtual I/O.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • SMI# cannot interrupt currently executing SMM code. The processor latches the falling edge of a pending SMI# signal while the Intel386 EX processor is executing an existing SMI# (this allows one level of buffering). The nested SMI# is not recognized until after the execution of a resume instruction (RSM). • SMI# brings the processor out of idle or powerdown mode. 7.2.
SYSTEM MANAGEMENT MODE ports the relocation of SMRAM. When this bit is set (1), the processor supports SMRAM relocation. When this bit is cleared (0), then the processor does not support SMRAM relocation. Since this device doesn’t support SMRAM relocation, bit 17 of the SMM Revision Identifier is cleared. The SMRAM address space is fixed from 38000H to 3FFFFH. 7.3 SYSTEM MANAGEMENT MODE PROGRAMMING AND CONFIGURATION 7.3.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL is no 64 Kbyte limit. The value loaded into the selector register is shifted to the left four bits and moved into its corresponding descriptor base, then added to the effective address. The effective address can be generated indirectly, using a 32-bit register. However, only 16 bits of the Extended Instruction Pointer (EIP) register are pushed onto the stack during calls, exceptions and INTR services.
SYSTEM MANAGEMENT MODE of the CPU is saved to the SMM State Dump Area. After executing a RSM instruction, the CPU proceeds to the next application code instruction (see instruction #4 in Figure 7-1). SMM latency is measured from the falling edge of SMI# to the first ADS# where SMIACT# is active (see Figure 7-2).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CLK2 T1 T2 CLKOUT SMI# B D ADS# READY# C SMIACT# A Normal State State Save, SMM Handler, State Restore Normal State A = 1 CLK min, B = 20 CLK min, C = 16 CLK min, D = 4 CLK min A2512-02 Figure 7-2. SMIACT# Latency NOTE Even if bus cycles are pipelined, the minimum clock numbers are guaranteed.
SYSTEM MANAGEMENT MODE 7.3.2.1 SMI# Priority When more than one exception or interrupt is pending at an instruction boundary, the processor services them in a predictable order. The priority among classes of exception and interrupt sources is shown in Table 7-3. The processor first services a pending exception or interrupt from the class that has the highest priority, transferring execution to the first instruction of the handler.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 7.3.2.2 System Management Interrupt During HALT Cycle Since SMI# is an asynchronous signal, it may be generated at any time. A condition of interest arises when an SMI# occurs while the CPU is in a HALT state. To give the system designer maximum flexibility, the processor allows an SMI# to optionally exit the HALT state.
SYSTEM MANAGEMENT MODE 7.3.2.3 HALT Restart It is possible for SMI# to break into the HALT state. In some cases the application might want to return to the HALT state after RSM. The SMM architecture provides the option of restarting the HALT instruction after RSM. The word at address 03FF02H is the HALT restart slot. The processor sets bit 0 of this location when the processor is in the HALT state while the SMI# occurred.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Priority Arbitration CLK2 SMI# Sampled SMI# Tsu Thold RDY# Tsu = SMI# setup time, Thold = SMI# hold time A2511-02 Figure 7-5. SMI# Timing 7.3.2.5 I/O Restart Bit 16 of the SMM Revision Identifier is set (1) indicating that this device does support the I/O trap restart extension to the SMM base architecture.
SYSTEM MANAGEMENT MODE then any pending INTR and NMI is serviced after completion of RSM instruction execution. Only one INTR and one NMI can be pending. The SMM handler may choose to enable interrupts to take advantage of device drivers. Since interrupts were enabled while under control of the SMM handler, the signal SMIACT# continues to be asserted. If the system designer wants to take advantage of existing device drivers that leverage interrupts, the memory controller must take this into account.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SMI# Instr Instr #1 #2 Instr Instr #3 #4 INTR or NMI State SMM Enable HALT Halted Save Handler INTR & NMI State SMM State Handler Resume Interrupt Handler A2507-01 Figure 7-7. HALT During SMM Handler 7.3.3.3 Idle Mode and Powerdown Mode During SMM Both Idle Mode and Powerdown Mode may be used while in SMM. Entering and exiting either of these power management modes from SMM is identical to entering or exiting from normal mode.
SYSTEM MANAGEMENT MODE exactly as if they represented another address line. The following options are supported by the chip select unit: CASMM CMSMM Chip select active: 0 0 During normal mode only 1 0 During SMM only X 1 During normal mode or SMM To see how this extension of the CSU supports the SMRAM requirements, consider an embedded system which has 1 Mbyte of 16-bit wide EPROM in the region 03F00000H to 03FFFFFFH and 1 Mbyte of 16-bit wide RAM in the region 00000000H to 000FFFFFH.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 7.3.4.2 SMRAM State Dump Area The SMM State Save sequence asserts SMIACT#. This mechanism indicates to internal modules that the CPU has entered and is currently executing SMM. The resume (RSM) instruction is only valid when in SMM. SMRAM space is an area located in the memory address range 38000H– 3FFFFH. The SMRAM area cannot be relocated internally. SMRAM space is intended for access by the CPU only, and should be accessible only when SMM is enabled.
SYSTEM MANAGEMENT MODE The programmer should not modify the contents of this area in SMRAM space directly. SMRAM space is reserved for CPU access only and is intended to be used only when the processor is in SMM. 7.3.5 Resume Instruction (RSM) After an SMI# request is serviced, the RSM instruction must be executed to allow the CPU to return to an application transparently after servicing the SMI#.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 7.5 PROGRAMMING CONSIDERATIONS 7.5.1 System Management Mode Code Example The following code example contains these software routines. SerialWriteStr2 Located in SMRAM upon program execution, this routine loops endlessly while writing a character “X” out the serial port on the EV386EX board. SerialWriteStr Located in the main program in FLASH, this routine loops endlessly while writing a string out the serial port before entering SMM.
SYSTEM MANAGEMENT MODE ---------------------------------------------------------------------------*/ void SerialWriteStr2() /* Loops while writing a char out to the serial port */ { _asm { mov ax,0x3900 mov ss,ax mov sp,0x100 Forever: mov dx,0xf4fd TstStatus: in al,dx testal,0x20 je TstStatus // Code below is same as _SetEXRegByte(TransmitPortAddr,’X’) mov ax,’X’ mov dx,0xf4f8 out dx, al jmp Forever } } /*********************** Function SerialWriteStr ************************** Parameters: Unit Unit number
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL } /*************************** Function InitSIO ******************************* Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1. Mode Defines parity, number of data bits, number of stop bits... Reference Serial Line Control register for various options ModemCntrl Defines the operation of the modem control lines BaudRate Specifies baud rate.
SYSTEM MANAGEMENT MODE _SetEXRegByte(SIOPortBase + DLH, HIBYTE(BaudDivisor) ); _SetEXRegByte(SIOPortBase + DLL, LOBYTE(BaudDivisor) ); // Set Serial Line control register _SetEXRegByte(SIOPortBase + LCR, Mode); // Sets Mode and resets the // Divisor latch // Set modem control bits _SetEXRegByte(SIOPortBase + MCR, ModemCntrl); return E_OK; } /******************************* MAIN ***********************************/ Parameters: None Returns: None Assumptions: None Real/Protected Mode No changes required.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SetEXRegWordInline(CS2ADL,0x08700); SetEXRegWordInline(CS2ADH,0x3); SetEXRegWordInline(CS2MSKL,0x07C01); SetEXRegWordInline(CS2MSKH,0x00); _asm { mov ax,0x3800 mov es,ax // Enables SRAM as memory // Copy SMM_EXAM.
8 CLOCK AND POWER MANAGEMENT UNIT
CHAPTER 8 CLOCK AND POWER MANAGEMENT UNIT The clock generation circuitry provides uniform, nonoverlapping clock signals to the core and integrated peripherals. The power management features control the clock signals to provide power conservation options. This chapter is organized as follows: • • • • • Overview (see below) Controlling the PSCLK Frequency (page 8-7) Controlling Power Management Modes (page 8-8) Design Considerations (page 8-11) Programming Considerations (page 8-13) 8.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Three of the internal peripherals have selectable clock sources. • The asynchronous serial I/O (SIO) unit can use either the SERCLK signal or an external clock (connected to the COMCLK pin) as its clock source. • The synchronous serial I/O (SSIO) unit can use either the SERCLK signal or the PSCLK signal. • The timer/counters can use either the PSCLK signal or an external clock connected to the TMRCLKn input pin.
CLOCK AND POWER MANAGEMENT UNIT The signal from the RESET pin is also routed to the clock generation unit, which synchronizes the processor clock with the falling edge of the RESET signal and provides a synchronous internal RESET signal to the rest of the device. The RESET falling edge can occur in either PH1 or PH2. If RESET falls during PH1, the clock generation circuitry inserts a PH2, so that the next phase is PH1 (Figure 8-2). If it falls during PH2, the next phase is automatically PH1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL vice enters the programmed mode when the HALT cycle is terminated by a valid READY#. This READY# may be generated either internally or externally. A device reset, an NMI or SMI#, or any unmasked interrupt request from the interrupt control unit causes the device to exit the power management mode. After a reset, the CPU starts executing instructions at 3FFFFF0H and the device remains in normal operation.
CLOCK AND POWER MANAGEMENT UNIT Halt Instruction with Powerdown Flag Set e ke set or d I N M n t e rr u pt I to In r M ter r up I t Idle Mode SM I# SM I# SMI# or se R e ked as r N o Un R s ma Un m Powerdown Mode Halt Instruction with Idle Flag Set Normal Operation RSM with Powerdown Flag and Halt Restart Slot Set Reset or RSM Instruction with Halt Restart Slot Clear System Management Mode RSM Instruction with Idle Flag and Halt Restart Slot Set A2229-03 Figure 8-3.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 8.1.3 Clock and Power Management Registers and Signals Table 8-1 lists the registers and Table 8-2 list the signals associated with the clock and power management unit. Table 8-1. Clock and Power Management Registers Register Expanded Address CLKPRS 0F804H PWRCON 0F800H Description Clock Prescale: This register contains the programmed divisor value used to generate PSCLK from the internal clock.
CLOCK AND POWER MANAGEMENT UNIT 8.2 CONTROLLING THE PSCLK FREQUENCY The PSCLK signal can provide a 50% duty cycle prescaled clock to the timer/counter and SSIO units. This feature is useful for providing various frequencies, including a 1.19318 MHz output for a PC-compatible system timer, or speaker tone generator. Determine the required prescale value using the following formula, then write this value to the CLKPRS register (Figure 8-4).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 8.3 CONTROLLING POWER MANAGEMENT MODES Two power management modes are available: idle and powerdown. These modes are clock distribution functions controlled by the power control register (PWRCON), shown in Figure 8-5. Power Control Register PWRCON (read/write) Expanded Addr: ISA Addr: Reset State: F800H — 00H 7 0 — Bit Number — — — WDTRDY Bit Mnemonic HSREADY PC1 PC0 Function 7–4 — Reserved.
CLOCK AND POWER MANAGEMENT UNIT 8.3.1 Idle Mode Idle mode freezes the core clocks (PH1C low and PH2C) high, and leaves the peripheral clocks (PH1P and PH2P) toggling. To enter idle mode: 1. Program the PWRCON register (Figure 8-5). 2. Execute a HALT instruction. 3. The CPU enters idle mode when READY# terminates the halt bus cycle. NOTE CLKOUT continues to run while the CPU is in idle mode.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 8.3.2 Powerdown Mode Powerdown mode freezes both the core clocks and the peripheral clocks (PH1C and PH1P low, PH2C and PH2P high). The BIU cannot acknowledge DMA, refresh, and external hold requests in powerdown mode, since all the clocks are frozen. To enter powerdown mode, follow these steps: 1. Program the PWRCON register (Figure 8-5). 2. Execute a HALT instruction. 3.
CLOCK AND POWER MANAGEMENT UNIT PH1 PH2 ? ? PH2 PH1 PH2 PH1 CLK2 CLKOUT/PH1P/PH1C PH2P/PH2C PWRDOWN CLK2 CLKOUT/PH1P/PH1C PH2P/PH2C PWRDOWN A2469-02 Figure 8-7. Timing Diagram, Entering and Leaving Powerdown Mode 8.4 DESIGN CONSIDERATIONS This section outlines design considerations for the clock and power management unit. 8.4.1 Reset Considerations External circuitry must provide an input to the RESET pin.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Asynchronous RESET D Q D Q CLK2 Synchronous Reset Signal to chip and other system logic. A2465-02 Figure 8-8. Reset Synchronization Circuit 8.4.2 Power-up Considerations 8.4.2.1 Built-in Self Test The Intel386 EX processor supports the Intel386 SX processor built-in self-test (BIST) mode for testing core functions. To initiate the self test, follow these steps: 1. Hold the RESET pin high for a minimum of 80 CLK2 cycles. 2.
CLOCK AND POWER MANAGEMENT UNIT 8.4.3 Powerdown Mode and Idle Mode Considerations • The “wake-up” signals (INT, NMI, and SMI#) are level-sensitive inputs to the wake-up circuitry. The active state of any of these inputs prevents the device from entering powerdown or idle mode. • The refresh control unit cannot perform DRAM refreshes during powerdown. • Powerdown mode freezes PSCLK and SERCLK.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL None Syntax: int error; WORD psclk = 0x02; error = Set_Prescale_Value(psclk); Real/Protected Mode: No changes required.
CLOCK AND POWER MANAGEMENT UNIT No changes required.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /* clear lowest two bits of pwrcon */ pwrcon = pwrcon & 0xfc; /* Set mode to powerdown */ _SetEXRegByte(PWRCON, pwrcon | PWDWN); /* call HALT instruction to execute POWERDOWN mode */ _asm { HLT } }/* Enter_Powerdown_Mode */ /***************************************************************************** Mode_Setting_To_Active: Description: This function returns the 386EX to Active mode.
9 INTERRUPT CONTROL UNIT
CHAPTER 9 INTERRUPT CONTROL UNIT The Interrupt Control Unit (ICU) consists of two cascaded interrupt controllers, a master and a slave, that allow internal peripherals and external devices (through interrupt pins) to interrupt the core through its interrupt input. The interrupt control unit is functionally identical to two industry-standard 82C59As connected in cascade. The system supports a maximum of 15 simultaneous interrupt sources, which can be individually or globally disabled.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The slave 82C59A is cascaded from (or connected to) the master’s IR2 signal. Like the master, the slave uses a programmable priority structure. When the slave receives an interrupt request, it sends the request to the master (assuming the request is enabled and has sufficient priority). The master sees the slave request as a request on its IR2 line.
INTERRUPT CONTROL UNIT IR0 8259A Master IR1 IR2 INT INTR (to core) OUT0 (TCU) P3CFG.2 0 1 1 P3CFG.2 VSS To/From I/O Port 3 INTCFG.6 0 1 IR3 SIOINT1 OUT1(TCU) 0 1 IR4 0 MCR1.3 SIOINT1 1 1 INTCFG.6 0 1 INTCFG.5 SIOINT0 1 INT0 (P3.2)† 0 P3.1 P3CFG.1 0 INT8 TMROUT1 (P3.1) MCR0.3 SIOINT0 P3GFG.0 1 INTCFG.5 INT9 1 TMROUT0 0 P3.0 OUT0(TCU) (P3.0) 0 1 P3CFG.3 INT1 (P3.3) To/From I/O Port 3 0 P3CFG.4 1 INT2 (P3.4) To/From I/O Port 3 0 0 P3CFG.3 IR5 0 1 VSS 0 1 VSS 0 1 VSS P3CFG.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.2 ICU OPERATION The following sections describe the ICU operation. The ICU’s interrupt sources, interrupt priority structure, interrupt vectors, interrupt processing, and polling mode are discussed. 9.2.1 Interrupt Sources The ICU support a total of 18 interrupt sources (see Table 9-1) but only a maximum of 15 simultaneous sources. Eight of these sources are internal peripherals and ten are external device pins (INT9:0).
INTERRUPT CONTROL UNIT Table 9-1. 82C59A Master and Slave Interrupt Sources Master IR Line IR0 Source Connected by TMROUT0 (timer control unit) Hardwired VSS P3CFG.2=0 INT0 (device pin) P3CFG.2=1 IR2 Slave 82C59A Cascade Hardwired IR3 SIOINT1 (SIO unit) INTCFG.6=0 INT8 INTCFG.6=1 (device pin) P3CFG.1=1 SIOINT0 (SIO unit) INTCFG.5=0 INT9 INTCFG.5=1 (device pin) P3CFG.0=1 IR1 Slave IR Line Source Connected by VSS INTCFG.0=0 INT4 (device pin) INTCFG.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Interrupt processing begins with the assertion of an IR signal. During the ICU initialization process (described in “Register Definitions” on page 9-15), you can program the ICU to be either edge-triggered or level-triggered. See “Interrupt Detection” on page 9-29 for a description of the difference between level and edge triggered signals. 9.2.2 Interrupt Priority Each 82C59A contains eight interrupt request signals.
INTERRUPT CONTROL UNIT Default Highest Level IR0 Becomes Highest Level IR6 Automatic Automatic Rotation Rotation (Before) (After) Becomes Highest Highest IR4 IR5 Level Level Before Being IR5 IR6 Serviced IR1 IR7 IR2 IR0 IR6 IR7 IR3 IR1 IR7 IR0 IR4 IR2 IR0 IR1 IR5 IR3 IR1 IR4 IR2 IR5 IR3 IR6 Lowest Level Specific Rotation IR7 Specified Lowest Level Assigned Lowest Level After Being Serviced IR2 IR3 IR4 A2303-02 Figure 9-2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL processing of a lower-level slave interrupt. The special fully nested mode is generally used by the master in a cascaded system. Special mask In some applications, you may want to allow lower-level requests interrupt the processing of higher-level interrupts. The special mask mode supports these applications.
INTERRUPT CONTROL UNIT 9.2.4 Interrupt Process Each IR signal has a mask, a pending, and an in-service bit associated with it. • The mask bit disables the IR signal. The respective mask bits provide a way to individually disable the IR signals. You can globally disable all interrupts to the core using the CLI instruction. The mask bits reside in the OCW1. • The pending bit indicates that the IR signal is requesting interrupt service.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL NOTE Unlike the AEOI mode (this is a mode, and not a command like specific EOI or nonspecific EOI), which is enabled during initialization, the other methods are commands issued during interrupt processing, usually at the end of an interrupt’s service routine.
INTERRUPT CONTROL UNIT Master receives an interrupt request. (From a non-slave source.) Master sets the request's pending bit. Is request enabled? Is special mask mode enabled? Yes No Yes Yes End Is master operating in special-fully nested mode? No Is the in-service bit for this request set? No (operating in fully nested mode) Yes No Is request equal or higher than any set in-service bits? No No Is request higher level than any set in-service bits? Yes Yes Master sends request to CPU.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Slave receives an interrupt request. Slave sets the request's pending bit. Is request enabled? Is special mask mode enabled? Yes No Yes Yes End (operating in fully nested mode) No Is the in-service bit for this request set? No Is request higher than any set in-service bits? No Yes Slave sends request to master. Note: See the "Interrupt Process - Master Request from Slave Source" figure for the continuation of this flow chart.
INTERRUPT CONTROL UNIT Master receives IR2 interrupt request. Master sets its IR2 pending bit. Is request enabled? Is special mask mode enabled? Yes No Yes Yes End No Is master operating in special-fully nested mode? No (operating in fully nested mode) Yes Is the IR2 in-service bit set? No Is request equal or higher than any set in-service bits? No No Is request higher level than any set in-service bits? Yes Yes Master sends request to CPU. CPU initiates interrupt acknowledge cycle.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The interrupt’s priority structure determines which EOI command should be used. Use the specific EOI command for the special mask mode. In this mode, a lower-level interrupt can interrupt the processing of a higher-level interrupt. The specific EOI command is necessary because it allows you to specifically clear the lower level in-service bit.
INTERRUPT CONTROL UNIT configuring more than six external 82C59As. Since the polling mode doesn’t require that the additional 82C59As be cascaded from the master, the number of interrupt request sources for a polled system is limited only by the number of 82C59As that the system can address. Polling and standard interrupt processing can be used within the same program. Systems that use polling as the only method of device servicing must still fully initialize the 82C59A modules.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 9-2. ICU Registers (Sheet 1 of 2) Register P3CFG Expanded Address 0F824H PC/AT* Address — (read/write) INTCFG 0F832H — 0F020H 0F0A0H 0020H 00A0H Initialization Command Word 1: 0F021H 0F0A1H 0021H 00A1H Initialization Command Word 2: 0F021H 0021H Initialization Command Word 3: (write only) ICW3 (master) (write only) ICW3 (slave) 0F0A1H 00A1H Contains the base interrupt vector number for the 82C59A.
INTERRUPT CONTROL UNIT Table 9-2. ICU Registers (Sheet 2 of 2) Register IRR (master) IRR (slave) Expanded Address PC/AT* Address Function 0F020H 0F0A0H 0020H 00A0H Interrupt Request: 0F020H 0F0A0H 0020H 00A0H In-service: POLL (master) 0F020H 0F021H 0020H 0021H Poll Status Byte: POLL (slave) 0F0A0H 0F0A1H 00A0H 00A1H Indicates pending interrupt requests. (read only) ISR (master) ISR (slave) (read only) (read only) Indicates the interrupt requests that are currently being serviced.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.1 Port 3 Configuration Register (P3CFG) Use the P3CFG register to connect the interrupt request signals (INT3:0) to the package pins. These signals are multiplexed with port 3 signals, P3.5–2. Connecting a port 3 signal to the package pin also connects VSS to the corresponding master’s IR signal, disabling the signal.
INTERRUPT CONTROL UNIT 9.3.2 Interrupt Configuration Register (INTCFG) Use the INTCFG register to connect the INT9:4 interrupt request pins to the master’s and the slave’s IR signals and to enable the master’s external cascade signals. When enabled, the cascade signals appear on address lines A18:16 during interrupt acknowledge cycles. Every external slave monitors these lines to determine whether it is the slave being addressed.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.3 Initialization Command Word 1 (ICW1) Initialization begins with writing ICW1. Use ICW1 to select the interrupt request triggering type (level or edge). The following actions occur within an 82C59A module when its ICW1 is written: • The interrupt mask register is cleared, enabling all interrupt request signals. • The IR7 signal is assigned the lowest interrupt level (default). • Special mask mode is disabled.
INTERRUPT CONTROL UNIT 9.3.4 Initialization Command Word 2 (ICW2) Use the ICW2 register to define the base interrupt vector for the 82C59A. Valid vector numbers for maskable interrupts range from 32 to 255. Because the base vector number must reside on an 8-byte boundary, the valid base vector numbers are 32 + n × 8 where 0 ≤ n ≤ 27. Write the base interrupt vector’s five most-significant bits to ICW2’s five most-significant bits.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.5 Initialization Command Word 3 (ICW3) The ICW3 register contains information about the master/slave connections. For this reason, the functions of the master’s ICW3 and the slave’s ICW3 differ. ICW3 (at 0F021H or 0021H) is the master’s cascade configuration register (Figure 9-11). The master has an internal slave cascaded from its IR2 signal. You can cascade additional slaves from the master’s IR7, IR6, IR5, IR4, IR3 and IR1 signals.
INTERRUPT CONTROL UNIT ICW3 (at 0F0A1H or 00A1H) is the internal slave ID register (Figure 9-11). Use this register to indicate that the slave is cascaded from the master’s IR2 signal. This gives the internal slave an ID of 2. Each slave device uses the IDs to determine whether it is the slave being addressed. During a slave access, the slave’s ID is driven on the master’s CAS2:0 signals. If these signals are enabled (bit 7 of INTCFG is 1), they appear on the A18:16 address lines.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.6 Initialization Command Word 4 (ICW4) Use ICW4 to select the special-fully nested mode or the fully nested mode and to enable the automatic EOI mode. Initialization Command Word 4 ICW4 (master and slave) (write only) Expanded Addr: ISA Addr: Reset State: master F021H 0021H XXH slave F0A1H 00A1H XXH 7 0 0 Bit Number 0 0 SFNM Bit Mnemonic 0 0 AEOI 1 Function 7–5 — Write zero to these bits to guarantee device operation.
INTERRUPT CONTROL UNIT 9.3.7 Operation Command Word 1 (OCW1) OCW1 is the interrupt mask register. Setting a bit in the interrupt mask register disables (masks) interrupts from the corresponding IR signal. For example, setting the master’s OCW1 M3 bit disables interrupts from the master IR3 signal. Clearing a bit in the interrupt mask register enables interrupts from the corresponding IR signal.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.8 Operation Command Word 2 (OCW2) Use OCW2 to change the priority structure and issue EOI commands.
INTERRUPT CONTROL UNIT 9.3.9 Operation Command Word 3 (OCW3) Use OCW3 to enable the special mask mode, issue a poll command, and provide access to the interrupt in-service and request registers (ISR, IRR).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.10 Interrupt Request Register (IRR) This 8-bit, read-only register contains the levels requesting an interrupt to be acknowledged. It is accessed using OCW3 (see Figure 9-15). The highest request level is reset from the IRR when an interrupt is acknowledged. Bits 7:0 of this register are the pending bits, respectively, of interrupt requests IR7:0. 9.3.
INTERRUPT CONTROL UNIT 9.4 DESIGN CONSIDERATIONS The following sections discuss some design considerations. 9.4.1 Interrupt Acknowledge Cycle When the core receives an interrupt request from the master, it completes the instruction in progress and any succeeding locked instructions, then initiates an interrupt acknowledge cycle. The interrupt acknowledge cycle generates an internal interrupt acknowledge (INTA#) signal that consists of two locked pulses (Figure 9-17).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Level triggered The 82C59A recognizes a high level on an IR line as an interrupt request. A device must maintain the high level until after the falling edge of the first INTA# pulse. Unlike an edge-triggered IR signal, a leveltriggered IR signal continues to generate interrupts as long as it is asserted.
INTERRUPT CONTROL UNIT Intel386™ EX Processor PLD READY# READY# M/IO# W/R# D/C# ADS# LBA# CLKOUT CLK2 INTA# INTA# and READY# State Machine CAS0 External CAS Decode CAS1 CAS2 External 82C59As CAS0 Latch CAS1 CAS2 A0 INTx INTy CSx# INT INTA# RD# WR# D7:0 CAS0 CAS1 CAS2 BLE# A0 CSx# INT CSy# CSy# RD# RD# WR# WR# D7:0 D7:0 INTA# A2857-01 Figure 9-19.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.5 PROGRAMMING CONSIDERATIONS Consider the following when programming the ICU. • When an 82C59A receives an interrupt request, it sets the request’s pending bit (regardless of whether the IR signal is masked or not). The pending bit remains set until the interrupt is serviced. • When the LS bit in ICW1 is set to edge-triggered during initialization, all the interrupt pending bits will be cleared.
INTERRUPT CONTROL UNIT BYTE _CascadeBits_ = 0x4; /***************************************************************************** InitICU Description: Initialization for both the master and slave Interrupt Control Units (ICU). tine only initializes the internal interrupt controllers, external ICUs must be initialized separately. These should be initialized before interrupts are enabled(i.e., enable()).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Real/Protected Mode No changes required.
INTERRUPT CONTROL UNIT /***************************************************************************** InitICUSlave Description: Initialization only the internal slave Interrupt Control Units (ICU). This routine only initializes the internal interrupt controller, external ICUs must be initialized separately. Parameters: SlaveMode SlaveBase SlavePins Mode of operation for Slave ICU Specifies the base interrupt vector number for the Slave interrupts.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL _IRQ_SlaveBase_ = SlaveBase & 0xf8; _SetEXRegByte(ICW1S, 0x11 | SlaveMode); // Set slave triggering _SetEXRegByte(ICW2S, _IRQ_SlaveBase_); // Set slave base interrupt // type, least 3-bit must be 0 _SetEXRegByte(ICW3S, 0x2); // Set slave ID _SetEXRegByte(ICW4S, 0x1); // Set bit 0 to guarantee // operation cfg_pins = _GetEXRegByte(INTCFG); cfg_pins |= SlavePins; _SetEXRegByte(INTCFG, SlavePins); // Set Slave external interrupt // pins return E_OK; }/* InitI
INTERRUPT CONTROL UNIT #define IR7 0x80 Disable8259Interrupt(IR0 | IR1 | IR3 | IR4 | IR5 | IR6 | IR7, IR1 | IR2 | IR3 | IR4 |IR5 | IR6); Real/Protected Mode No changes required.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /* ICU IRQ Mask Values*/ #define IR0 0x1 #define IR1 0x2 #define IR2 0x4 #define IR3 0x8 #define IR4 0x10 #define IR5 0x20 #define IR6 0x40 #define IR7 0x80 Enable8259Interrupts(IR2, IR0 | IR7); //Enable MasterIR2 for cascading //Enable INT4 and WDTOUT on Slave Real/Protected Mode No changes required.
INTERRUPT CONTROL UNIT supports INTERRUPT_ISR (parameter is ignored). Protected mode supports both. Returns:Error Code E_INVALID_VECTOR E_BADVECTOR E_OK -- An IRQ of greater than 15 was passed -- IRQ is used for cascading to a slave interrupt controller -- Initialized OK, No error. Assumptions: Compiler supports far and interrupt keywords ICU must be configured before this function is call for it to operate properly _IRQ_SlaveBase_,_IRQ_MstrBase_,_CascadeBits_ are set before function is called.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL return E_OK; }/* SetIRQVector */ /***************************************************************************** SetInterruptVector: Description: Loads the interrupt vector table with the address of the interrupt routine. The vector table entry number is determined by the vector number. Parameters: InterProc ISR_Type Address of interrupt function, will be loaded into the interrupt table. Specifies if the interrupt function.
INTERRUPT CONTROL UNIT Poll_Command: Description: This routine issues a poll command which reads the poll status byte of the ICU. Parameters: Master_or_Slave Specifies which interrupt controller is polled Returns: Current value of poll status byte Assumptions: None Syntax: in poll_status; poll_status = Poll_Command(); Real/Protected Mode: No changes required.
10 TIMER/COUNTER UNIT
CHAPTER 10 TIMER/COUNTER UNIT The Timer/counter Unit (TCU) has the same basic functionality as the industry-standard 82C54 counter/timer. It contains three independent 16-bit down counters, which can be driven by a prescaled value of the processor clock or an external clock. The counters contain two count formats (binary and BCD) and six different operating modes, two of which are periodic. Both hardware and software triggered modes exist, providing for internal or external control.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Therefore, the OUTn signals can drive external devices, generate interrupt requests, initiate DMA transactions or combinations of the three. Each counter operates independently. Six different counting modes are available and two count formats: binary (16 bits) or BCD (4 decades). Each operating mode allows you to program the counter with an initial count and to change this value “on the fly.
TIMER/COUNTER UNIT 10.1.1 TCU Signals and Registers Table 10-1 and Table 10-2 lists the signals and registers associated with the TCU. Table 10-1. TCU Signals Signal PSCLK Device Pin or Internal Signal Internal signal Description Prescaled Clock: This is one of the two possible connections for the counter’s CLKINn signal. PSCLK is an internal signal that is a prescaled value of the processor internal clock.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Table 10-2. TCU Associated Registers Register P3CFG PINCFG Expanded Address PC/AT* Address 0F824H 0F826H — 0F834H — Timer Configuration: Enables the counter’s CLKINn input signal, selects the CLKINn connection (PSCLK or TMRCLKn) for each counter, and either connects TMRGATEn or VCC to each counter’s GATE n input signal, or sets GATE n high or low through register bits.
TIMER/COUNTER UNIT 10.2 TCU OPERATION Each counter can operate in any one of six operating modes. These modes are described in sections 10.2.1 through 10.2.6. In all modes, the counters decrement on the falling edge of CLKINn. In modes 0, 1, 4, and 5, the counters roll over to the highest count, either 0FFFFH for binary counting or 9999 for BCD counting, and continue counting down. However, the state of the OUTn is only affected by the first run through the counter and does not change on subsequent runs.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Table 10-3. Operations Caused by GATEn Operating Modes Low or Falling Rising High 0 Disables counting — Enables counting 1 — 1) Initiates counting — 2) Resets OUTn after next CLKINn 2 1) Disables counting Initiates counting Enables counting Initiates counting Enables counting 2) Sets OUTn immediately high 3 1) Disables counting 2) Sets OUTn immediately high 4 Disables counting — Enables counting 5 — Initiates counting — 10.2.
TIMER/COUNTER UNIT Control Word = 10H Count = 4 Writes to Counter n CLKINn GATEn OUTn Count ? ? ? ? 0004 0003 0002 0001 0000 FFFF FFFE A2311-01 Figure 10-2. Mode 0 – Basic Operation Figure 10-3 shows suspending the counting sequence. A low level on GATEn causes the counter to suspend counting (both the state of OUTn and the count remain unchanged). A high level on GATEn resumes counting.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Figure 10-4 shows writing a new count before the current count reaches zero. The counter loads the new count on the CLKINn pulse after you write it, then decrements this new count on each succeeding CLKINn pulse. OUTn remains low until the new count reaches zero. Control Word = 10H Count = 3 Count = 2 Writes to Counter n CLKINn GATEn OUTn Count ? ? ? ? 0003 0002 0001 0002 0001 0000 FFFF A2395-02 Figure 10-4. Mode 0 – Writing a New Count 10.2.
TIMER/COUNTER UNIT Control Word = 12H Count = 3 Writes to Counter n CLKINn GATEn OUTn Count ? ? ? ? ? 0003 0002 0001 0000 FFFF 0003 0002 A2312-02 Figure 10-5. Mode 1 – Basic Operation Figure 10-6 shows retriggering the one-shot. On the CLKINn pulse following the retrigger, the counter reloads the count. The control logic then decrements the count on each succeeding CLKINn pulse; OUTn remains low until the count reaches zero.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Figure 10-7 shows writing a new count. The counter waits for a gate-trigger to load the new count. The counter loads the new count on the CLKINn pulse following the trigger, then decrements the count on each succeeding CLKINn pulse. OUTn remains low until the count reaches zero. Control Word = 12H Count =2 Count = 4 Writes to Counter n CLKINn GATEn OUTn Count ? ? ? ? ? 0002 0001 0000 FFFF FFFE 0004 0003 A2397-02 Figure 10-7.
TIMER/COUNTER UNIT Control Word= 14H Count = 3 Writes to Counter n CLKINn GATEn OUTn Count ? ? ? ? 0003 0002 0001 0003 0002 0001 0003 A2313-01 Figure 10-8. Mode 2 – Basic Operation Figure 10-9 shows suspending the counting sequence. A low level on GATEn causes the counter to suspend counting. The count remains unchanged and OUTn is immediately driven (or stays) high (If the GATEn goes low when OUTn is low, then OUTn is immediately driven high).
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Figure 10-10 shows writing a new count. The counter loads the new count after the counter reaches one. When the counter receives a gate-trigger after a new count was written to it, the counter loads the new count on the next CLKINn pulse. This allows GATEn to synchronize the counters. Control Word = 14H Count = 4 Count = 5 Writes to Counter n CLKINn GATEn OUTn Ccount ? ? ? ? 0004 0003 0002 0001 0005 0004 0003 A2399-01 Figure 10-10.
TIMER/COUNTER UNIT Control Word = 16H Count = 4 Writes to Counter n CLKINn GATEn OUTn Count ? ? ? ? 0004 0002 0004 0002 0004 0002 0004 0002 0004 0002 A2314-01 Figure 10-11. Mode 3 – Basic Operation (Even Count) Odd count basic operation: 1. After a control word write, OUTn is driven high. 2. On the CLKINn pulse following a gate-trigger or when the count rolls over, count minus one is loaded. 3. On each succeeding CLKINn pulse, the count is decremented by two. 4.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Control Word = 16H Count = 5 Writes to Counter n CLKINn GATEn OUTn Count ? ? ? ? 0004 0002 0000 0004 0002 0004 0002 0000 0004 0002 A2400-01 Figure 10-12. Mode 3 – Basic Operation (Odd Count) NOTE For an even count of N, OUTn remains high for N/2 counts and low for N/2 counts (provided GATEn remains high). For an odd count of N, OUTn remains high for (N + 1)/2 counts and low for (N – 1)/2 counts (provided GATEn remains high).
TIMER/COUNTER UNIT Figure 10-14 and Figure 10-15 shows writing a new count. If the counter receives a gate-trigger after writing a new count but before the end of the current half-cycle, the count is loaded on the next CLKINn pulse and counting continues from the new count (Figure 10-14). Otherwise, the new count is loaded at the end of the current half-cycle (Figure 10-15).
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.2.5 Mode 4 – Software-triggered Strobe Initializing a counter for mode 4 drives the counter’s OUTn signal high and initiates counting. A count is loaded on the CLKINn pulse following a count write. When the counter reaches zero, OUTn strobes low for one clock pulse. The counter rolls over and continues counting, but does not strobe low when it reaches zero again. The counter strobes low only the first time it reaches zero after a count write.
TIMER/COUNTER UNIT Figure 10-17 shows suspending the counting sequence. A low level on GATEn causes the counter to suspend counting (both the state of OUTn and the count remain unchanged). A high level on GATEn resumes counting. Control Word = 18H Count = 3 Writes to Counter n CLKINn GATEn OUTn Count ? ? ? ? 0003 0003 0003 0002 0001 0000 FFFF A2402-01 Figure 10-17. Mode 4 – Disabling the Count Figure 10-18 shows writing a new count.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.2.6 Mode 5 – Hardware-triggered Strobe Initializing a counter for mode 5 sets the counter’s OUTn signal, starting the counting sequence. A gate-trigger loads the programmed count. When the counter reaches zero, OUTn strobes low for one clock pulse. The counter then rolls over and continues counting, but OUTn does not strobe low when the count reaches zero. The OUTn strobes low only the first time it reaches zero after a count is loaded.
TIMER/COUNTER UNIT Figure 10-20 shows retriggering the strobe with a gate-trigger. On the CLKINn pulse following the retrigger, the counter reloads the count. The control logic then decrements the count on each succeeding CLKINn pulse. OUTn remains high until the count reaches zero, then strobes low for one CLKINn pulse. Control Word = 1AH Writes to Counter n Count = 3 CLKINn GATEn OUTn Count ? ? ? ? ? ? 0003 0002 0003 0002 0001 0000 FFFF FFFE A2404-01 Figure 10-20.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.3 REGISTER DEFINITIONS The following sections describe how to configure a counter’s input and output signals, initialize a counter for a specific operating mode and count format, write count values to a counter, and read a counter’s status and count. 10.3.1 Configuring the Input and Output Signals Each counter is driven by a clock pulse on its CLKINn input.
TIMER/COUNTER UNIT . Timer Configuration TMRCFG (read/write) Expanded Addr: ISA Addr: Reset State: F834H — 00H 7 TMRDIS Bit Number 7 0 SWGTEN GT2CON CK2CON GT1CON Bit Mnemonic TMRDIS CK1CON GT0CON CK0CON Function Timer Disable: 0 = Enables the CLKINn signals. 1 = Disables the CLKIN n signals. 6 SWGTEN Software GATEn Enable 0 = Connects GATE n to either the VCC pin or the TMRGATEn pin. 1 = Enables GT2CON, GT1CON, and GT0CON to control the connections to GATE2, GATE1 and GATE0 respectively.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL The peripheral pin selection registers (P3CFG and PINCFG) determine whether each counter’s OUTn signal is connected to its TMROUTn pin. See Figure 10-1 for the TCU signal connections. For details on the P3CFG and PINCFG registers see Figure 10-23 and Figure 10-24. The counter output signals are automatically connected to the interrupt control unit.
TIMER/COUNTER UNIT Use PINCFG bit 5 to connect TMROUT2, TMRCLK2, and TMRGATE2 to package pins. Pin Configuration PINCFG (read/write) Expanded Addr: ISA Addr: Reset State: F826H — 00H 7 0 — Bit Number PM6 PM5 Bit Mnemonic 7 — 6 PM6 PM4 PM3 PM2 PM1 PM0 Function Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit. Pin Mode: 0 = Selects CS6# at the package pin. 1 = Selects REFRESH# at the package pin.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.3.2 Initializing the Counters The timer control register (TMRCON) has three formats: control word, counter-latch, and readback. When writing to TMRCON, certain bit settings determine which format is accessed. Use the TMRCON’s control word format (Figure 10-25) to specify a counter’s count format and operating mode. Writing the control word forces OUTn to go to an initial state that depends on the selected operating mode.
TIMER/COUNTER UNIT Timer Control (Control Word Format) TMRCON Expanded Addr: ISA Addr: Reset State: F043H 0043H XXH 7 0 SC1 SC0 Bit Number 7–6 RW1 RW0 Bit Mnemonic SC1:0 M2 M1 M0 CNTFMT Function Select Counter: Use these bits to specify a particular counter. The selections you make for bits 5–0 define this counter’s operation. 00 = counter 0 01 = counter 1 10 = counter 2 11 is not an option for TMRCON’s control word format.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.3.3 Writing the Counters Use the write format of a counter’s Timer n register (TMRn) to specify a counter’s count. The count must conform to the write selection specified in the control word (least-significant byte only, most-significant byte only, or least-significant byte followed by the most-significant byte). You can write a new count to a counter without affecting the counter’s programmed operating mode.
TIMER/COUNTER UNIT 10.3.4 Reading the Counter To read the counter you can perform a simple read operation or send a latch command to the counter. TMRCON contains two formats that allow you to send latch commands to individual counters: the counter-latch and read-back format. The counter-latch command latches the count of a specific counter. The read-back command latches the count and/or status of one or more specified counters. 10.3.4.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Timer Control (Counter-latch Format) TMRCON Expanded Addr: ISA Addr: Reset State: F043H 0043H XXH 7 0 SC1 SC0 Bit Number 7–6 0 0 Bit Mnemonic SC1:0 0 0 0 0 Function Select Counter: These bits specify the counter that receives the counter-latch command. 00 = counter 0 01 = counter 1 10 = counter 2 11 is not an option for TMRCON’s counter-latch format. Selecting 11 accesses TMRCON’s read-back format, which is shown in Figure 10-29.
TIMER/COUNTER UNIT You can interleave reads and writes of the same counter; for example, if the counter is programmed for the two-byte read/write selection, the following sequence is valid. 1. Read least-significant byte. 2. Write new least-significant byte. 3. Read most-significant byte. 4. Write new most-significant byte.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.3.4.3 Read-back Command Use the read-back format of TMRCON (Figure 10-29) to latch the count and/or status of one or more counters. Latch a counter’s status to check its programmed operating mode, count format, and read/write selection and to determine whether the latest count written to it has been loaded.
TIMER/COUNTER UNIT The read-back command can latch the count and status of multiple counters. This single command is functionally equivalent to several counter-latch commands, one for each counter latched. Each counter's latched count and status is held until it is read or until you reconfigure the counter. A counter’s latched count or status is automatically unlatched when read, but other counters’ latched values remain latched until they are read.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Timer n (Status Format) TMRn (n = 0–2) Expanded Addr: ISA Addr: Reset State: F040H, F041H F042H 0040H, 0041H 0042H XXH 7 OUTPUT Bit Number 7 0 NULCNT RW1 RW0 Bit Mnemonic OUTPUT M2 M1 M0 CNTFMT Function Output Status: This bit indicates the current state of the counter’s output signal. 0 = OUTn is low 1 = OUTn is high 6 NULCNT Count Status: This bit indicates whether the latest count written to the counter has been loaded.
TIMER/COUNTER UNIT When a counter receives multiple read-back commands, it ignores all but the first command; the count/status that the core reads is the count/status latched from the first read-back command (see Table 10-6). Table 10-6. Results of Multiple Read-back Commands Without Reads Command Sequence Read-back Command 1 Latch counter 0’s count and status. Counter 0’s count and status latched. 2 Latch counter 1’s status. Counter 1’s status latched. 3 Latch counter 2 and 1’s status.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL • With the readback command: — If both the status and counter values are latched, the user can read the value of the Read/Write selection bits from the status register to know what bytes of the counter value are being latched in the TMRn register. — If only the counter value is latched, you must know the Read/Write selection before the counter value can be read correctly.
TIMER/COUNTER UNIT Returns:Error Codes E_INVALID_DEVICE E_OK -- Unit number specifies a non-existing device -- Initialized OK, No error.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL if(!Enable) TmpByte |= 0x80; // Set Timer Disable Bit TmpByte |= (Inputs << (Unit*2)); _SetEXRegByte(TMRCFG,TmpByte); // Set CKnCON and GTnCON bits /* Set Timer Control Register */ TmpByte = Unit << 6; // Set counter select TmpByte |= (0x30 | Mode); // Set R/W low then high byte and Mode bits _SetEXRegByte(TMRCON,TmpByte); /* Set Initial Counter Value */ TmpByte = HIBYTE(InitCount); _SetEXRegByte(TmrCntPort, LOBYTE(InitCount)); _SetEXRegByte(TmrCntPort, Tmp
TIMER/COUNTER UNIT #define DISABLE 0 SetUp_ReadBack(DISABLE, DISABLE, ENABLE, ENABLE, ENABLE); Real/Protected Mode: No changes required *****************************************************************************/ void SetUp_ReadBack( BYTE Timer0, BYTE Timer1, BYTE Timer2, BYTE GetStatus, BYTE GetCount ) { BYTE rb_control = 0; rb_control |= 0xc0; // Set TMRCON to read-back command if (GetStatus != 0) rb_control &= 0xef; if (GetCount != 0) rb_control &= 0xdf; if (Timer0 != 0) rb_control |= 0x02; if (Ti
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Returns: Counter Value of specified timer Assumptions: This function assumes that the R/W format is configured to be LSB first, then MSB Syntax: WORD Counter_Value; Counter_Value = CounterLatch(TMR_1); Real/Protected Mode: No changes required *****************************************************************************/ WORD CounterLatch( BYTE Timer ) { BYTE control_word = 0; BYTE CounterL, CounterH; WORD Counter; control_word = Timer << 6; control_word &= 0xc0
TIMER/COUNTER UNIT /***************************************************************************** ReadCounter: Description: This function performs a simple read operation on the specified timer. However, because the counter value is not latched, the timer must be disabled, read, and then re-enabled.
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL case TMR_2: CountL = _GetEXRegByte(TMR2); CountH = _GetEXRegByte(TMR2); break; } Count = (((WORD)CountH << 8) + CountL); EnableTimer(); return(Count); }/* ReadCounter */ /***************************************************************************** TimerISR: Description: Interrupt Service Routine for Timer-generated interrupts. Parameters: None Returns: None Assumptions: None Syntax: Not called by user.
TIMER/COUNTER UNIT /***************************************************************************** Example of how to write a new initial counter value to a timer This value can be rewritten at any time without affecting the Counter’s programmed mode. Before writing an initial count value, the Control Word must be configured for the proper R/W and Count formats. -->This example assumes that Timer1 is in the R/W format of LSB first, then MSB, and that the Count format is binary.
11 ASYNCHRONOUS SERIAL I/O UNIT
CHAPTER 11 ASYNCHRONOUS SERIAL I/O UNIT The asynchronous serial I/O (SIO) unit provides a means for the system to communicate with external peripheral devices and modems. The SIO unit performs serial-to-parallel conversions on data characters received from a peripheral device or modem and parallel-to-serial conversions on data characters received from the CPU. The SIO unit consists of two independent SIO channels, each of which is compatible with National Semiconductor’s NS16C450.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SIO1 SIOCFG.1 1 BCLKIN 1 SERCLK Receive Data To/From I/O Port 3 0 To ICU To DMA To DMA Transmit Data SIOCFG.7 1 PINCFG.2 1 0 PINCFG.3 From DMA 0 To/From DMA 1 0 1 Request to Send From SSIO Data Set Ready COMCLK (P3.7)† RXD1 (DRQ1) To DMA SIOINT1 RBFDMA1 TXEDMA1 Clear to Send P3CFG.7 0 0 TXD1 (DACK1#) CTS1# (EOP#) PINCFG.
ASYNCHRONOUS SERIAL I/O UNIT 11.1.1 SIO Signals Table 11-1 lists the SIOn signals. Table 11-1. SIO Signals Signal Baud-rate Generator Clock Source Device Pin or Internal Signal Description Internal signal SERCLK: Device pin (input) This internal signal is the processor’s input clock, CLK2, divided by four. COMCLK: An external source connected to this pin can clock the SIOn baud-rate generator.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 11-1. SIO Signals Signal TXEDMAn Device Pin or Internal Signal Description Internal Signal Transmitter Empty: When this signal is high, the Transmitter Holding Register is empty (transmit data has been loaded into the Transmit Shift Register). RBFDMAn Internal Signal Receiver Full: When high, this signal indicates that the Receive Buffer has been loaded with data from the Receive Shift Register. 11.
ASYNCHRONOUS SERIAL I/O UNIT The baud-rate generator’s output frequency is determined by BCLKIN and a divisor as follows. BCLKIN frequency baud-rate generator output frequency = ---------------------------------------------------- , div isor baud rate generator output frequency bit rate = --------------------------------------------------------------------------------------------------16 The minimum divisor value is 1, giving a maximum baud rate of BCLKIN.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.2.2 SIOn Transmitter The data frame for transmissions is programmable. It consists of a start bit, 5 to 8 data characters, an optional parity bit, and 1 to 2 stop bits. The transmitter can produce even, odd, forced, or no parity. The transmitter can also produce break conditions.
ASYNCHRONOUS SERIAL I/O UNIT Baud-rate Clock S y s t e m SIOn Transmit Shift Register TXDn (pin mux) SIOn Transmit Buffer Transmit Buffer Empty (To ICU and DMA) B u s A2326-01 Figure 11-3. SIOn Transmitter The transmitter contains a transmitter empty (TE) flag and a transmit buffer empty (TBE) flag. At reset, TBE and TE are set, indicating that the transmit buffer and shift register are empty. Writing data to the transmit buffer clears TBE and TE.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Select the BCLKIN source and the transmitter input baud rate. Select the data frame. (Word length, number of stop bits, and type of parity.) Enable interrupts and/or DMA. Is transmit buffer empty? No Yes Write data to transmit buffer register. (ISR or DMA cycle) Yes More Data to Transmit ? No Transmitter transfers data to shift register and sets transmit buffer empty flag, causing an interrupt or DMA request.
ASYNCHRONOUS SERIAL I/O UNIT 11.2.3 SIOn Receiver The data frame for receptions is programmable, and is identical to the data frame for transmissions. It consists of a start bit, 5 to 8 data characters, an optional parity bit, and 1 to 2 stop bits. The receiver can be programmed for even, odd, forced, or no parity. When the receiver detects a parity condition other than what it was programmed for, it sets a parity error flag.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The receiver contains a receive buffer full (RBF) flag and flags for each of the error conditions described above. At reset, RBF and each of the error flags (PE, FE, OE, and BI) are clear, indicating that the receive buffer is empty, and no error has occurred. When a character is received the receiver checks for parity, framing or break errors, and sets the appropriate bits, if necessary.
ASYNCHRONOUS SERIAL I/O UNIT Select the BCLKIN source and the receiver input baud rate. Select the data frame. (Word length, number of stop bits, and type of parity.) Enable interrupts and/or DMA. Receiver shifts data into shift register from the RXDn pin. Was a parity error detected? No Was a framing error detected? Yes Yes Receiver sets the parity error flag. Service error interrupt (if enabled) Yes No Receiver sets the framing error flag.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.2.4 Modem Control The modem control logic provides interfacing for four input signals and two output signals used for handshaking and status indication between the SIOn and a modem or data set.
ASYNCHRONOUS SERIAL I/O UNIT 11.2.6 SIO Interrupt and DMA Sources 11.2.6.1 SIO Interrupt Sources Each SIO channel has four status signals: receiver line status, receiver buffer full, transmit buffer empty, and modem status. An overrun error, parity error, framing error, or break condition can activate the receiver line status signal. When the receiver transfers data from its shift register to its buffer, it activates the receive buffer full signal.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.2.7 External UART Support Many PC compatible applications may need to support COM3 and COM4 serial ports. Since the integrated serial ports are mapped to I/O addresses that support only COM1 and COM2, an interface to support an external serial I/O unit has been included. The master ICU interrupt inputs IR3 and IR4 may be brought out to package pins as INT8 (muxed with P3.1/TMROUT1) and INT9 (muxed with P3.0/TMROUT0), respectively.
ASYNCHRONOUS SERIAL I/O UNIT 11.3 REGISTER DEFINITIONS Table 11-5 lists the registers associated with the SIO unit and the following sections contain bit descriptions for each register. Table 11-5.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 11-5.
ASYNCHRONOUS SERIAL I/O UNIT 11.3.1 Pin and Port Configuration Registers (PINCFG and PnCFG [n = 1–3]) Use PINCFG bits 2:0 to connect the SIO1 signals to package pins. Pin Configuration PINCFG (read/write) Expanded Addr: ISA Addr: Reset State: F826H — 00H 7 0 — Bit Number PM6 PM5 Bit Mnemonic 7 — 6 PM6 PM4 PM3 PM2 PM1 PM0 Function Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit. Pin Mode: 0 = Selects CS6# at the package pin.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Use P1CFG bits 4:0 to connect SIO0 signals to package pins. Port 1 Configuration P1CFG (read/write) Expanded Addr: ISA Addr: Reset State: F820H — 00H 7 0 PM7 Bit Number 7 PM6 PM5 Bit Mnemonic PM7 PM4 PM3 PM2 PM1 Function Pin Mode: 0 = Selects P1.7 at the package pin. 1 = Selects HLDA at the package pin. 6 PM6 Pin Mode: 0 = Selects P1.6 at the package pin. 1 = Selects HOLD at the package pin. 5 PM5 Pin Mode: 0 = Selects P1.
ASYNCHRONOUS SERIAL I/O UNIT Use P2CFG bits 7–5 to connect SIO0 signals to package pins. Port 2 Configuration P2CFG (read/write) Expanded Addr: ISA Addr: Reset State: F822H — 00H 7 0 PM7 Bit Number 7 PM6 PM5 Bit Mnemonic PM7 PM4 PM3 PM2 PM1 PM0 Function Pin Mode: 0 = Selects P2.7 at the package pin. 1 = Selects CTS0# at the package pin. 6 PM6 Pin Mode: 0 = Selects P2.6 at the package pin. 1 = Selects TXD0 at the package pin. 5 PM5 Pin Mode: 0 = Selects P2.5 at the package pin.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Use P3CFG bit 7 to connect the COMCLK pin to the package pin. Port 3 Configuration P3CFG (read/write) Expanded Addr: ISA Addr: Reset State: F824H — 00H 7 0 PM7 Bit Number 7 PM6 PM5 Bit Mnemonic PM7 PM4 PM3 PM2 PM1 Function Pin Mode: 0 = Selects P3.7 at the package pin. 1 = Selects COMCLK at the package pin. 6 PM6 Pin Mode: 0 = Selects P3.6 at the package pin. 1 = Selects PWRDOWN at the package pin. 5 PM5 Pin Mode: 0 = Selects P3.
ASYNCHRONOUS SERIAL I/O UNIT 11.3.2 SIO and SSIO Configuration Register (SIOCFG) Use SIOCFG to select the baud-rate generator clock source for the SIO channels and to have a channel’s modem input signals connected internally rather than to package pins. Selecting the internal modem signal connection option connects RTS# to CTS#, DTR# to DSR# and DCD#, and VCC to RI#. The modem signal connections for this internal option are shown in Figure 11-20.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.3.3 Divisor Latch Registers (DLLn and DLHn) Use these registers to program the baud-rate generator’s output frequency. The baud-rate generator’s output determines the transmitter and receiver bit times.
ASYNCHRONOUS SERIAL I/O UNIT 11.3.4 Transmit Buffer Register (TBRn) Write the data words to be transmitted to TBRn. Use the interrupt control or DMA units or poll the serial line status register (LSRn) to determine whether the transmit buffer is empty.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.3.5 Receive Buffer Register (RBRn) Read RBRn to obtain the last data word received. Use the interrupt control or DMA units or poll the serial line status register (LSRn) to determine whether the receive buffer is full.
ASYNCHRONOUS SERIAL I/O UNIT 11.3.6 Serial Line Control Register (LCRn) Use LCRn to provide access to the multiplexed registers, send a break condition, and determine the data frame for receptions and transmissions.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.3.7 Serial Line Status Register (LSRn) Use LSRn to check the status of the transmitter and receiver. Serial Line Status LSR0, LSR1 (read only) Expanded Addr: ISA Addr: Reset State: LSR0 F4FDH 03FDH 60H LSR1 F8FDH 02FDH 60H 7 0 — Bit Number TE TBE BI Bit Mnemonic FE PE OE RBF Function 7 — Reserved. This bit is undefined.
ASYNCHRONOUS SERIAL I/O UNIT 11.3.8 Interrupt Enable Register (IERn) Use IERn to connect the SIOn status signals to the interrupt control unit. All four status signals can be connected to the interrupt control unit. Interrupt Enable IER0, IER1 (read/write) IER0 Expanded Addr: F4F9H ISA Addr: 03F9H Reset State: 00H IER1 F8F9H 02F9H 00H 7 0 — — Bit Number — Bit Mnemonic 7–4 — 3 MS — MS RLS TBE RBF Function Reserved; for compatibility with future devices, write zeros to these bits.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.3.9 Interrupt ID Register (IIRn) Use the IIRn to determine whether an interrupt is pending and, if so, which status signal generated the interrupt request. Interrupt ID IIR0, IIR1 (read only) Expanded Addr: ISA Addr: Reset State: IIR0 F4FAH 03FAH 01H IIR1 F8FAH 02FAH 01H 7 0 — Bit Number — — — — Bit Mnemonic 7–3 — 2 IS2:1 IS2 IS1 IP# Function Reserved. These bits are undefined.
ASYNCHRONOUS SERIAL I/O UNIT 11.3.10 Modem Control Register (MCRn) Use MCRn to put the SIOn into a diagnostic test mode. In this mode, the modem input signals are disconnected from the package pins and controlled by the lower four MCRn bits and the modem output signals are forced to their inactive states (Figure 11-19). Additionally, the MCRn signals are also forced into the MSR register bits. MCRn.1 CTS# MCRn.0 DSR# MCRn.3 DCD# MCRn.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Modem Control MCR0, MCR1 (read/write) Expanded Addr: ISA Addr: Reset State: MCR0 F4FCH 03FCH 00H MCR1 F8FCH 02FCH 00H 7 0 — Bit Number — — LOOP OUT2 Bit Mnemonic OUT1 RTS DTR Function 7–5 — Reserved; for compatibility with future devices, write zeros to these bits. 4 LOOP Loop Back Test Mode: 0 = Normal mode 1 = Setting this bit puts the SIOn into diagnostic (or loop back test) mode.
ASYNCHRONOUS SERIAL I/O UNIT 11.3.11 Modem Status Register (MSR n) Read MSRn to determine the status of the modem control input signals. The upper four bits reflect the current state of the modem input signals and the lower four bits indicate whether the inputs (except for RI#) have changed state since the last time this register was read. These lower four bits are reset to zero when the CPU reads the Modem Status register.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.3.12 Scratch Pad Register (SCRn) SCRn is available for use as a scratch pad. Writing and reading this register has no effect on SIOn operation. Scratch Pad SCR0, SCR1 (read/write) Expanded Addr: ISA Addr: Reset State: SCR0 F4FFH 03FFH XXH SCR1 F8FFH 02FFH XXH 7 0 SP7 Bit Number 7–0 SP6 SP5 SP4 Bit Mnemonic SP7:0 SP3 SP2 SP1 SP0 Function Writing and reading this register has no effect on SIOn operation. Figure 11-23.
ASYNCHRONOUS SERIAL I/O UNIT 11.4.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL options ModemCntrl BaudRate ClockRate Defines the operation of the modem control lines Specifies baud rate. The baud divisor value is calculated based on clocking source and clock frequency. The clocking frequency is set by calling the InitializeLibrary function.
ASYNCHRONOUS SERIAL I/O UNIT return E_INVALID_DEVICE; /* Set Port base based on serial port used */ SIOPortBase = (Unit ? SIO1_BASE : SIO0_BASE); /* Initialized Serial Port registers */ /* Calculate the baud divisor value, based on baud clocking */ BaudDivisor = (WORD)(BaudClkIn / (16*BaudRate)); /* Turn on access to baud divisor register */ _SetEXRegByte(SIOPortBase + LCR, 0x80); /* Set the baud rate divisor register, High byte first */ _SetEXRegByte(SIOPortBase + DLH, HIBYTE(BaudDivisor) ); _SetEXRegByte
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #define SIO_0 0 #define LENGTH 32 char String_Read[LENGTH]; int error; error = SerialReadStr (SIO_0, String_Read, LENGTH); Real/Protected Mode No changes required.
ASYNCHRONOUS SERIAL I/O UNIT until a character has been received from the serial port. Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1. Returns: BYTE Read from serial port, if zero an error occurred. Assumptions: REMAPCFG register has Expanded I/O space access enabled (ESE bit set). The processor Port pin are initialized separately. Syntax: #define SIO_0 0 BYTE character; character = SerialReadChar (SIO_0); Real/Protected Mode No changes required.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SerialWriteChar: Description: Is a Polled serial port write function that waits forever or until a character has been written to the serial port. Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1. ch Character value to be written out Returns: None Assumptions: REMAPCFG register has Expanded I/O space access enabled (ESE bit set). The processor Port pin are initialized separately.
ASYNCHRONOUS SERIAL I/O UNIT Description: Is a Polled serial port write function that waits forever or until all characters have been written to the serial port. The NUL character (‘\0’) is used to indicate end of string. Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1. str Address of a zero terminated string to be transmitted Returns: None Assumptions: REMAPCFG register has Expanded I/O space access enabled (ESE bit set).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /***************************************************************************** SerialWriteMem: Description: Is a Polled serial port write function that waits forever or until count characters have been written to the serial port. Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1.
ASYNCHRONOUS SERIAL I/O UNIT } } /* SerialWriteMem */ /***************************************************************************** Serial0_ISR: Description: Template Interrupt Service Routine for Serial Port0 interrupts. This function identifies the cause of the interrupt and branches to the corresponding action. Parameters: None (Not called by user) Returns: None Assumptions: None Syntax: Not a user function. Real/Protected Mode: No changes required.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL if ((msr0 & 0x04) && (msr0 & 0x40)) { /* ring indicator */ } if ((msr0 & 0x02) && (msr0 & 0x20)) { /* data set ready bit has been set */ } if ((msr0 & 0x01) && (msr0&0x10)) { /* clear to send signal has been set */ } break; case 1: Service_TBE(); /* Routine for Interrupt driven Serial Writes */ break; case 2: /* RBF signal */ Service_RBF(); /* Routine specific to RBF generated interrupts */ break; case 3: /* receive line status signal */ lsr0 = _GetEXRegBy
ASYNCHRONOUS SERIAL I/O UNIT /***************************************************************************** Service_RBF: Description: Service routine for interrupts generated by RBF signal. This routine is used for Interrupt-Driven Serial Reads. It echoes the typed character to the screen, stopping when it receives an ESC character. Parameters: None Returns: None Assumptions: None Syntax: Not called by user Real/Protected Mode: No changes required.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Description: Is an interrupt driven serial port write function. The NUL character (‘\0’) is used to indicate end of string. Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1. str Address of a zero terminated string to be transmitted Returns: None Assumptions: REMAPCFG register has Expanded I/O space access enabled (ESE bit set). The processor Port pin are initialized separately.
ASYNCHRONOUS SERIAL I/O UNIT None Assumptions: None Syntax: Not called by user. Real/Protected Mode: No changes required.
12 DMA CONTROLLER
CHAPTER 12 DMA CONTROLLER The DMA controller improves system performance by allowing external or internal peripherals to directly transfer information to or from the system. The DMA controller can transfer data between any combination of memory and I/O, with any combination of data path widths (8 or 16 bits). It contains two identical channels. The DMA controller has features that are unavailable on an 8237A, but it can be configured to operate in an 8237A-compatible mode.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DMACFG.2:0 DMA 3 DREQ0 0 1 2 3 4 5 6 7 RBFDMA0 (SIO0) TXEDMA1 (SIO1) SSTBE (SSIO) OUT1 (TCU) RBFDMA1 (SIO1) TXEDMA0 (SIO0) SSRBF (SSIO) To SIO1 DMACFG.3 0 DMAACK0# From CSU DRQ0 (DCD1#)† PINCFG.4 1 DACK0# (CS5#) DMACFG.6:4 3 DREQ1 0 1 2 3 4 5 6 7 RBFDMA1 (SIO1 ) TXEDMA0 (SIO0) SSRBF (SSIO) OUT2 (TCU) RBFDMA0 (SIO0) TXEDMA1 (SIO1) SSTBE (SSIO) To SIO1 DRQ1 (RXD1) DMACFG.7 0 DMAACK1# DMAINT From SIO1 To ICU PINCFG.2 1 0 PINCFG.
DMA CONTROLLER 12.1.1 DMA Terminology This section provides a definition of some of the terms used in this chapter to describe the DMA controller. DMA Process A DMA process is the execution of a programmed DMA task from beginning to end. Each DMA process requires initial programming by the Intel386 EX processor. Buffer A contiguous block of data. Buffer Transfer The action required by the DMA to transfer an entire buffer.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.1.2 DMA Signals Table 12-1 describes the DMA signals. Table 12-1.
DMA CONTROLLER 12.2 DMA OPERATION The following sections describe the operation of the DMA. See “Register Definitions” on page 12-28 for details on implementing DMA Controller options. 12.2.1 DMA Transfers The DMA transfers data between a requester and a target. The data can be transferred from the requester to target or vice versa. The target addresses and requester addresses can be located in either memory or I/O space, and data transfers can be on a byte or word basis.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL data bus, depending on the transfer direction. Since the requester is selected via the DACKn# signal the requester address is not meaningful in a fly-by mode transfer. Support logic (either external or built in to the I/O device) must be designed to monitor the DACKn# signal and accordingly generate the correct control signals to the I/O device, since all processor signals are used to access memory.
DMA CONTROLLER DMACFG register), but the Requester address registers would be programmed with one of the memory addresses. It doesn’t really matter which memory is the Requester and which is the Target, as long as the transfer direction is set to provide the correct Source and Destination. 12.2.2.4 Ready Generation For DMA Cycles DMA cycles are identical to any other type of memory or I/O cycles in terms of how they are completed.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Figures 12-2 and 12-3 are simple diagrams of how the Temporary Register is filled and emptied for a Read DMA cycle and a Write DMA cycle. Filling the Temporary Register DREQn #1 DREQn #2 DREQn #3 Emptying the Temporary Register DREQn #4 Four separate requests each with a read of the requester. Each byte is stored in the Temporary Register.
DMA CONTROLLER 12.2.3 Starting DMA Transfers Internal I/O, external I/O, or memory can request DMA service. The internal I/O requesters (the asynchronous serial I/O, synchronous serial I/O, and timer control units) are internally connected to the DMA request inputs. You must connect an external I/O source to the DMA DRQn; when you are using fly-by mode, you must also connect an external I/O source to the DACKn# signals. In addition, memory mapped I/O peripherals may use DRQn/DACKn#.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL control request, the bus arbiter services these requests by issuing an internal hold signal requesting control of the bus from the core. The core returns an internal hold acknowledge signal to the arbiter when bus ownership is granted. The arbiter then issues an acknowledge signal to the requesting device. Refresh requests always have the highest priority, while the priority structure of the other three requests is configurable.
DMA CONTROLLER Terminating a buffer transfer by deasserting DREQn can also be done either synchronously or asynchronously. The effect is identical to that of synchronous or asynchronous sampling of EOP#. When DREQn is used to terminate a DMA transfer in asynchronous mode, DREQn must be sampled inactive one CLKOUT before READY#. In synchronous mode it must be sampled inactive at the same time as READY#.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.2.6 Buffer-transfer Modes After a buffer transfer is completed or terminated, a channel can either become idle (require reprogramming) or reprogram itself and begin another buffer transfer after it is initiated by a hardware or software request. The DMA’s three buffer-transfer modes (single, autoinitialize, and chaining) determine whether a channel becomes idle or is reprogrammed after it completes or terminates a buffer transfer. 12.2.6.
DMA CONTROLLER The DMAINT signal is active immediately after the Chaining Process has been entered, as the channel then perceives the Base Registers to be empty and in need of reloading. It is important to have the interrupt service routine in place at the time the Chaining Process is entered. The interrupt request is removed when the most significant byte of the Base Target Address is loaded.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL transfer is suspended and the channel waits for the request input to be reactivated before it continues. 12.2.7.1 Single Data-transfer Mode In single data-transfer mode, a DMA request causes the channel to gain bus control. The channel transfers data (a byte or a word), decrements the buffer byte count (by 1 for byte transfers and 2 for word transfers), then relinquishes bus control.
DMA CONTROLLER After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQn active? No Yes DMA gains bus control. DMA transfers one byte or word of data and decrements the byte count. DMA channel relinquishes bus control. Byte count = FFFFFFH or EOP# No active? Yes Buffer transfer is complete, so channel becomes idle. A2331-02 Figure 12-8.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQn active? No Yes DMA gains bus control. DMA transfers one byte or word of data and decrements the byte count. DMA channel relinquishes bus control. No Byte count = FFFFFFH or EOP# active? Yes DMA channel is reprogrammed with the original addresses and byte count. A2332-02 Figure 12-9.
DMA CONTROLLER After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQn active? No Yes DMA gains bus control, transfers one byte or word of data, decrements byte count, and then relinquishes bus control. Is there a new process to set up? Yes Write new requester and target addresses and a new byte count. No Byte count = FFFFFFH or EOP# No active? Yes DMA is programmed with the new addresses and byte count.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.2.7.2 Block Data-transfer Mode In block data-transfer mode, a channel request initiates a buffer transfer. The channel gains bus control, then transfers the entire buffer of data. The DRQn signal only needs to be held active until DACKn# is active. NOTE Block mode, unlike the single mode, only gives up control of the bus for DRAM refresh cycles.
DMA CONTROLLER After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQn active? No Yes DMA gains bus control. DMA transfers one byte or word of data and decrements the byte count. Byte count = FFFFFFH or EOP# No active? Yes DMA channel relinquishes bus control. Buffer transfer is complete, so channel becomes idle. A2334-02 Figure 12-11.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL After initiallization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQn active? No Yes DMA gains bus control. DMA transfers one byte or word of data and decrements the byte count No Byte count = FFFFFFH or EOP# active? Yes DMA channel relinquishes bus control. DMA channel is reprogrammed with the original addresses and byte count. A2333-02 Figure 12-12.
DMA CONTROLLER 12.2.7.3 Demand Data-transfer Mode In demand data-transfer mode, a channel request initiates a buffer transfer. The channel gains bus control and begins the buffer transfer. As long as the request signal (DRQn) remains active, the channel continues to perform data transfers. When the DRQn signal goes inactive, the channel completes its current bus cycle and relinquishes bus control, suspending the buffer transfer.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQn active? No Yes DMA gains bus control. DMA transfers one byte or word of data and decrements the byte count. Yes DMA channel relinquishes bus control. No DREQn active? Byte count = FFFFFFH or EOP# No active? Yes DMA channel relinquishes bus control. Buffer transfer is complete, so channel becomes idle. A2338-02 Figure 12-14.
DMA CONTROLLER After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQn active? No Yes DMA gains bus control. DMA transfers one byte or word of data and decrements the byte count. Yes DMA channel relinquishes bus control. No DREQn active? Byte count = FFFFFFH or EOP# No active? Yes DMA channel relinquishes bus control. DMA channel is reprogrammed with the original addresses and byte count. A2339-02 Figure 12-15.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL After initialization, the DAM channel is programmed with the requester and target addresses and a byte count. DREQn active? No Write new requester and target addresses and a new byte count. Is there a new process to set up? Yes No Yes DMA gains bus control. DMA transfers one byte or word of data and decrements the byte count. Yes DMA channel relinquishes bus control.
DMA CONTROLLER 12.2.8 Cascade Mode Cascade mode allows an external 8237A or another DMA-type device to gain bus control. A cascaded device requests bus control by holding a channel’s request input (DRQn) active. Once granted bus control, the cascaded device remains bus master until it relinquishes bus control by deactivating DRQn. If a refresh request occurs while a cascaded device has bus control, the cascaded device must deassert its request or the refresh cycle will be missed.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL After initialization, the DMA channel is programmed. DRQn active? No Yes Cascaded device gains bus control. No Refresh cycle is performed. Cascaded device deasserts DRQn, relinquishing bus control. Yes Refresh request? Yes DRQn active? No Cascaded device relinquishes bus control. Cascade cycle complete. A2337-02 Figure 12-17. Cascade Mode 12.2.
DMA CONTROLLER The four interrupt source signals (two per channel) are internally connected (ORed) to the interrupt request output (DMAINT). When an interrupt from DMAINT is detected, you can determine which signal caused the request by reading the DMA interrupt status register. 12.2.10 8237A Compatibility Although the DMA is an enhancement over the 8237A, you can configure it to operate in an 8237A-compatible mode. A list of the features common to the DMA and 8237A and a list of DMA enhancements follow.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3 REGISTER DEFINITIONS Table 12-3 lists the registers associated with the DMA unit, and the following sections contain bit descriptions for each register. Table 12-3.
DMA CONTROLLER Table 12-3. DMA Registers (Sheet 2 of 3) Register Expanded Address DMASTS (read only) F008H DMACMD2 (write only) F01AH DMAMOD1 (write only) F00BH DMAMOD2 (write only) F01BH DMASRR (read/write) F009H DMAMSK (write only) F00AH DMAGRPMSK (read/write) F00FH DMABSR (write only) F018H PC/AT* Address 0008H Description DMA Status: Indicates whether a hardware request is pending on channel 0 and 1. Indicates whether channel 0’s or channel 1’s byte count has expired.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 12-3. DMA Registers (Sheet 3 of 3) Register Expanded Address DMACHR (write only) F019H DMAIEN (read/write) F01CH DMAIS (read only) F019H DMAOVFE (read/write) F01DH 12-30 PC/AT* Address — Description DMA Chaining: Enables chaining buffer-transfer mode for a specified channel. — DMA Interrupt Enable: Connects the channel transfer complete status signals to the interrupt request output (DMAINT).
DMA CONTROLLER 12.3.1 Pin Configuration Register (PINCFG) Use PINCFG to connect DACK0#, EOP#, and DACK1# to package pins. Pin Configuration PINCFG (read/write) Expanded Addr: ISA Addr: Reset State: F826H — 00H 7 0 — Bit Number PM6 PM5 Bit Mnemonic 7 — 6 PM6 PM4 PM3 PM2 PM1 PM0 Function Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit. Pin Mode: 0 = Selects CS6# at the package pin. 1 = Selects REFRESH# at the package pin.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.2 DMA Configuration Register (DMACFG) Use DMACFG to select one of the hardware sources for each channel and to mask the DMA acknowledge (DMAACKn#) signals when using internal requesters.
DMA CONTROLLER 12.3.3 Channel Registers To program a DMA channel’s requester and target addresses and its byte count, write to the DMA channel registers. Some of the channel registers require the use of a byte pointer (BP) flip-flop to control the access to the upper and lower bytes. After you write or read a register that requires a byte pointer specification, the DMA toggles the byte pointer. For example, writing to DMA0TAR0 with BP=0 causes the DMA to set BP.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL NOTE The value you write to the byte count register must be one less than the number of bytes to be transferred. To transfer one byte, write zero to the byte count register (byte count = number of bytes – 1). To transfer one word, write one (byte) to the byte count register (byte count = [number of words X 2] – 1). 12.3.
DMA CONTROLLER 12.3.5 Command 1 Register (DMACMD1) Use DMACMD1 to enable both channels and to select the rotating method for changing the bus control priority structure. DMA Command 1 DMACMD1 (write only) Expanded Addr: ISA Addr: Reset State: F008H 0008H 00H 7 0 — Bit Number — — PRE — Bit Mnemonic 7–5 — 4 PRE CE — — Function Reserved; for compatibility with future devices, write zeros to these bits. Priority Rotation Enable: 0 = Priority is fixed based on value in DMACMD2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.6 Status Register (DMASTS) Use DMASTS to check the status of the channels individually. The DMA sets bits in this register to indicate that a channel has a hardware request pending or that a channel’s byte count has expired. DMA Status DMASTS (read only) Expanded Addr: ISA Addr: Reset State: F008H 0008H 00H 7 0 — Bit Number — R1 R0 Bit Mnemonic 7–6 — 5 R1 — — TC1 TC0 Function Reserved. These bits are undefined.
DMA CONTROLLER 12.3.7 Command 2 Register (DMACMD2) Use DMACMD2 to select the DREQn and EOP# sampling: asynchronous or synchronous. Bus timing diagrams that show the differences between asynchronous and synchronous sampling are shown in Figure 12-5 on page 12-10 and Figure 12-13 on page 12-21. Also, use DMACMD2 to assign a particular bus request to the lowest priority level for fixed priority mode.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.8 Mode 1 Register (DMAMOD1) Use DMAMOD1 to select a particular channel’s data-transfer mode and transfer direction and to enable the channel’s auto-initialize buffer-transfer mode. You can configure the DMA to modify the target address during a buffer transfer by clearing DMAMOD2.2, then use DMAMOD1.5 to specify how the channel modifies the address.
DMA CONTROLLER DMA Mode 1 DMAMOD1 (write only) Expanded Addr: ISA Addr: Reset State: F00BH 000BH 00H 7 0 DTM1 DTM0 Bit Number 7–6 TI AI TD1 Bit Mnemonic DTM1:0 TD0 0 CS Function Data-transfer Mode: 00 = Demand 01 = Single 10 = Block 11 = Cascade 5 TI Target Increment/Decrement: 0 = Causes the target address to be incremented after each data transfer in a buffer transfer.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.9 Mode 2 Register (DMAMOD2) Use DMAMOD2 to select the data transfer bus cycle option, specify whether the requester and target are in memory or I/O, and determine whether the DMA modifies the target and requester addresses. If you set up the DMA to modify the requester address, use DMAMOD2 to determine whether the DMA increments or decrements the requester address during a buffer transfer.
DMA CONTROLLER DMA Mode 2 DMAMOD2 (write only) Expanded Addr: ISA Addr: Reset State: F01BH — 00H 7 0 BCO RD Bit Number 7 TD RH RI Bit Mnemonic BCO TH 0 CS Function Bus Cycle Option: 0 = Selects the fly-by data transfer bus cycle option for the channel specified by bit 0. 1 = Selects the two-cycle data transfer bus cycle option for the channel specified by bit 0. 6 RD Requester Device Type: 0 = Clear this bit when the requester for the channel specified by bit 0 is in memory space.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.10 Software Request Register (DMASRR) Write DMASRR to issue software DMA service requests. Software requests are subject to bus control priority arbitration with all other software and hardware requests. A software request activates the internal channel request signal. This signal remains active until the channel completes its buffer transfer (either by an expired byte count or an EOP# input).
DMA CONTROLLER Read DMASRR to see whether a software request for a particular channel is pending. Each request bit is cleared upon Terminal Count or external EOP#. When in auto-initialize mode, both bits are cleared when a Terminal Count or external EOP# occurs. DMA Software Request (read format) DMASRR Expanded Addr: ISA Addr: Reset State: F009H 0009H 00H 7 0 — — Bit Number — — Bit Mnemonic 7–2 — 1 SR1 — — SR1 SR0 Function Reserved.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.11 Channel Mask and Group Mask Registers (DMAMSK and DMAGRPMSK) Use the DMAMSK and DMAGRPMSK registers to disable (mask) or enable channel hardware requests. DMAMSK allows you to disable or enable hardware requests for only one channel at a time, while DMAGRPMSK allows you to disable or enable hardware requests for both channels at once.
DMA CONTROLLER DMA Group Channel Mask DMAGRPMSK (read/write) Expanded Addr: ISA Addr: Reset State: F00FH 000FH 03H 7 0 — Bit Number — — — Bit Mnemonic 7–2 — 1 HRM1 — — HRM1 HRM0 Function Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. Hardware Request Mask 1: 0 = Channel 1’s hardware requests are not masked. 1 = Masks (disables) channel 1’s hardware requests. When this bit is set, channel 1 can still receive software requests.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.12 Bus Size Register (DMABSR) Use DMABSR to determine the requester and target data bus widths (8 or 16 bits). DMA Bus Size DMABSR (write only) Expanded Addr: ISA Addr: Reset State: F018H — X1X10000B 7 0 — Bit Number RBS — TBS Bit Mnemonic — — 0 CS Function 7 — Reserved; for compatibility with future devices, write zero to this bit.
DMA CONTROLLER 12.3.13 Chaining Register (DMACHR) Use DMACHR to enable or disable the chaining buffer-transfer mode for a selected channel. The following steps describe how to set up a channel to perform chaining buffer transfers. 1. Set up the chaining interrupt (DMAINT) service routine. 2. Configure the channel for the single buffer-transfer mode. 3. Program the mode registers. 4. Program the target address, requester address, and byte count registers. 5.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.14 Interrupt Enable Register (DMAIEN) Use DMAIEN to individually connect channel 0’s and 1’s transfer complete signal to the DMAINT interrupt request output. DMA Interrupt Enable DMAIEN (read/write) Expanded Addr: ISA Addr: Reset State: F01CH — 00H 7 0 — Bit Number — — — Bit Mnemonic 7–2 — 1 TC1 — — TC1 TC0 Function Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits.
DMA CONTROLLER 12.3.15 Interrupt Status Register (DMAIS) DMAIS indicates which source activated the DMA interrupt request signal (channel 0 transfer complete, channel 1 transfer complete, channel 0 chaining, or channel 1 chaining). DMA Interrupt Status DMAIS (read only) Expanded Addr: ISA Addr: Reset State: F019H — 00H 7 0 — Bit Number — TC1 TC0 Bit Mnemonic 7–6 — 5 TC1 — — CI1 CI0 Function Reserved. These bits are undefined.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.16 Software Commands The DMA contains four software commands: clear byte pointer, clear DMA, clear mask register, and clear transfer complete signal. Each software command has an I/O address associated with it (see Table 12-4). To issue a software command, write to its I/O address; the data written doesn’t matter —writing to the location is all that is necessary. Table 12-4.
DMA CONTROLLER with BP=0 causes the DMA to set BP. The clear byte pointer software command (DMACLRBP) allows you to force BP to a known state (0) before writing to the registers. • The target and requester addresses are incremented, decremented, or left unchanged and the byte count is decremented after each data transfer within a buffer transfer. Reading a register returns the current (or modified) value rather than the original programmed values.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL InitDMA1ForSSIXmitterToMem Initializes DMA channel1 for transfers between the SIO transmitter port and memory DMAInterrupt Interrupt Service Routine for DMA generated interrupts See Appendix C for included header files. #include #include #include #include “80386ex.h” “ev386ex.h” “dma.h”
DMA CONTROLLER /* given channel*/ } /***************************************************************************** DisableDMAHWRequests: Description: Disables channel hardware requests for the given DMA channel. The channel, however, can still receive software requests.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Description: Sets the requester to an I/O port address, wIO, for the DMA channel specified by nChannel. Parameters: nChannel wIO --channel for which to set Requester I/O port address --I/O address Returns: None Assumptions: None Syntax: SetDMAReqIOAddr(DMA_Channel1, TBR0); //Sets Req.
DMA CONTROLLER Description: Sets the target memory address for the DMA channel specified by nChannel. Parameters: nChannel ptMemory --channel for which to set target address --pointer to target memory location Returns: None Assumptions: Processor is in real mode. Syntax: static char lpsz[]=”Hello World”; SetDMATargMemAddr(DMA_Channel1, lpsz); Real/Protected Mode: The address calculation from ptMemory assumes the processor is in real mode.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #else /*Else in compact, large, or huge memory model*/ wSegment = _FP_SEG(ptMemory); /*...grab the segment from the pointer*/ wOffset = _FP_OFF(ptMemory); /*...
DMA CONTROLLER *****************************************************************************/ int SetDMAXferCount(int nChannel, DWORD lCount) { WORD addrDMAByc0_1; WORD addrDMAByc2; /*Check input*/ if ( (nChannel != DMA_Channel0) && (nChannel != DMA_Channel1) ) return ERR_BADINPUT; /*Set registers to correct channel*/ addrDMAByc0_1 = (nChannel == DMA_Channel0 ? DMA0BYC0_1 : DMA1BYC0_1); addrDMAByc2 = (nChannel == DMA_Channel0 ? DMA0BYC2 : DMA1BYC2); _SetEXRegByte(DMACLRBP, 0x0); /* Clear the byte pointer
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Syntax: InitDMA(); //Initialize DMA peripheral Real/Protected Mode: No changes required *****************************************************************************/ void InitDMA(void) { _SetEXRegByte(DMACLR, 0x0); _SetEXRegByte(DMACMD1, 0x0); _SetEXRegByte(DMACMD2, 0x8); /*Resets DMA peripheral*/ /*DMACMD1[7:5]=0: reserved*/ /*DMACMD1[4]=0: disable priority rotation*/ /* enable*/ /*DMACMD1[2]=0: enable channel’s 0 and 1*/ /*DMACMD1[1:0]=0: reserved*/
DMA CONTROLLER .
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL _SetEXRegByte(DMABSR, 0x51); /*DMABSR[7]=0: reserved*/ /*DMABSR[6]=1: sets req.’s bus size to 8-bit*/ /*DMABSR[5]=0: reserved*/ /*DMABSR[4]=1: sets tar.
DMA CONTROLLER None Syntax: regDMAIE = _GetEXRegByte(DMAIEN) | 0x2; //Enable tc interrupt for // channel 0 _SetEXRegByte(DMAIEN, regDMAIE); //Set interrupt routine SetIRQVector(DMAInterrupt, 12, INTERRUPT_ISR); Enable8259Interrupt(0, IR4); //Enable slave IR4, DMA interrupt NonSpecificEOI(); //Clear all interrupts Real/Protected Mode: No changes required *****************************************************************************/ void interrupt far DMAInterrupt(void) { WORD regDMAIS; regDMAIS = _GetEXRe
13 SYNCHRONOUS SERIAL I/O UNIT
CHAPTER 13 SYNCHRONOUS SERIAL I/O UNIT The synchronous serial I/O (SSIO) unit provides 16-bit bidirectional serial communications. The transmit and receive channels can operate independently (that is, with different clocks) to provide full-duplex communications. Either channel can originate the clocking signal or receive an externally generated clocking signal.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Clock Source (PSCLK or SERCLK) SSTBE (to DMA controller) SSIOCON.5 (TIE) SSIOINT (to Slave interrupt controller IR1) SSIOCON.1 (RIE) S y s t e m B u s Baud-rate Generator STXCLK Transmitter SSIOTX (pin mux) Receiver SSRBF (to DMA controller) SRXCLK (pin mux) SSIORX A2434-02 Figure 13-1. Transmitter and Receiver in Master Mode Clock Source (PSCLK or SERCLK) SSTBE (to DMA controller) SSIOCON.
SYNCHRONOUS SERIAL I/O UNIT Clock Source (PSCLK or SERCLK) Baud-rate Generator STXCLK SSTBE (to DMA controller) SSIOCON.5 (TIE) SSIOINT (to Slave interrupt controller IR1) SSIOCON.1 (RIE) S y s t e m B u s Transmitter SSIOTX (pin mux) Receiver SRXCLK (pin mux) SSIORX SSRBF (to DMA controller) A2436-02 Figure 13-3. Transmitter in Slave Mode, Receiver in Master Mode STXCLK SSTBE (to DMA controller) SSIOCON.5 (TIE) SSIOINT (to Slave interrupt controller IR1) SSIOCON.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.1.1 SSIO Signals Table 13-1 lists the SSIO signals. Table 13-1. SSIO Signals Signal STXCLK Device Pin or Internal Signal Device pin (input or output) Description Serial Transmit Clock: This pin functions as either an output or an input, depending on whether the transmitter is operating in master or slave mode. In master mode, STXCLK functions as an output.
SYNCHRONOUS SERIAL I/O UNIT 13.2 SSIO OPERATION The following sections describe the operation of the baud-rate generator, transmitter, and receiver. 13.2.1 Baud-rate Generator Either the prescaled clock or the serial clock (PSCLK or SERCLK) can drive the baud-rate generator (Figure 13-5). The SIO and SSIO configuration register (SIOCFG) selects one of these sources. SIOCFG.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The baud-rate generator contains a seven-bit down counter. A programmable baud-rate value (BV) is the reload value for the counter. The counter counts down from BV to zero, toggles the baud-rate generator output, then reloads the BV and counts down again. The baud-rate generator’s output is a function of BV and BCLKIN as follows.
SYNCHRONOUS SERIAL I/O UNIT 13.2.2.1 Transmit Mode using Enable Bit The transmitter contains a transmit holding buffer empty (THBE) flag and a transmit underrun error (TUE) flag. At reset, THBE is set, indicating that the buffer is empty. Writing data to the buffer clears THBE. When the transmitter transfers data from the buffer to the shift register, THBE is set.
T Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL EN = 0 TEN = 1 THBE = 1 HOLD Initialize SSIO Data Written Into SSIOTBUF Clears THBE THBE = 1 TEN = 1 THBE = 0 Data In Buffer Moved To Shift Register THBE Set TUE Set TUE = 1 A3399-01 Figure 13-7. SSIO Transmitter with Autotransmit Mode Disabled The SSIO Unit can be operated either by using a polling method or through interrupts. • Figure 13-8 shows a basic flowchart for using the polling method to transmit data through the SSIO.
SYNCHRONOUS SERIAL I/O UNIT Initialize SSIO Write Data to Buffer (SSIOTBUF) No AUTOTXM=1 ? Yes Enable Transmitter TEN=1 THBE=1 ? No Yes AUTOTXM=1 ? Yes No Delay To Allow Transmitter To Shift First Bit Out Disable Transmitter TEN=0 Yes TUE=1 ? No Error Routine A3394-01 Figure 13-8.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SSIO Transmitter Causes Interrupt Disable Interrupts While Transmitting Data THBE=1 ? No Error Routine Yes Write Data to Buffer (SSIOTBUF) Enable Transmitter TEN=1 Delay To Allow Transmitter To Shift First Bit Out Disable Transmitter TEN=0 Enable Interrupts Exit Interrupt Service Routine A3398-01 Figure 13-9.
SYNCHRONOUS SERIAL I/O UNIT If the transmitter is disabled while a data value in the shift register is being shifted out, it continues running until the last bit is shifted out. Then the shift register stops and the data and clock pins (SSIOTX and STXCLK) are three-stated; the contents of the buffer register are not loaded into the shift register. If the transmitter is disabled then re-enabled before the current value has been shifted out, it continues as if it were never disabled.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.2.2.2 Autotransmit Mode Set the AUTOTXM bit (SSIOCON2.2) and the TXMM bit (SSIOCON2.1) to enable Autotransmit mode. When the AUTOTXM bit is set, the word is automatically transferred to the shift register and the THBE bit is set. In this mode the TEN bit is ignored. Once the data is transferred to the shift register, the word is shifted out. If no new data has been written into the buffer, the transmitter stops.
SYNCHRONOUS SERIAL I/O UNIT The SSIO Unit can be operated either by using a polling method or through interrupts. • Figure 13-12 shows a basic flowchart for using the polling method to receive data through the SSIO. • Figure 13-13 shows a basic flowchart for the Interrupt Service Routine necessary when using interrupts to receive data through the SSIO. If interrupts are used, follow the below sequence for initialization: 1. Initialize the SSIO. 2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SSIO Receiver Causes Interrupt Disable Interrupts While Receiving Data Read Data From Buffer (SSIORBUF) ROE=0 ? No Error Routine Yes Enable Interrupts Exit Interrupt Service Routine A3397-01 Figure 13-13.
SYNCHRONOUS SERIAL I/O UNIT If the receiver is disabled while a data value is being shifted into the shift register, it continues running until the last bit is shifted in. Then the shift register is loaded into the buffer register, the shift register stops and the clock pin (SRXCLK) is three-stated if in the master mode. If the receiver is disabled then enabled before the current word has been shifted in, it continues as if it were never disabled.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.3 REGISTER DEFINITIONS Table 13-3 list the registers associated with the SSIO and the following sections contain bit descriptions for each register. Table 13-3.
SYNCHRONOUS SERIAL I/O UNIT 13.3.1 Pin Configuration Register (PINCFG) The serial receive clock (SRXCLK) and transmit serial data (SSIOTX) pins are multiplexed with other functions. Use PINCFG bits 0 and 1 to select the pin functions. Pin Configuration PINCFG (read/write) Expanded Addr: ISA Addr: Reset State: F826H — 00H 7 0 — Bit Number PM6 PM5 Bit Mnemonic 7 — 6 PM6 PM4 PM3 PM2 PM1 PM0 Function Reserved.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.3.2 SIO and SSIO Configuration Register (SIOCFG) Use SIOCFG bit 2 to connect either PSCLK or SERCLK to the baud-rate generator’s input (BCLKIN). SIO and SSIO Configuration SIOCFG (read/write) Expanded Addr: ISA Addr: Reset State: F836H — 00H 7 0 S1M Bit Number 7 S0M Bit Mnemonic S1M — — — SSBSRC S1BSRC S0BSRC Function SIO1 Modem Signal Connections: 0 = Connects the SIO1 modem input signals to the package pins.
SYNCHRONOUS SERIAL I/O UNIT 13.3.3 Prescale Clock Register (CLKPRS) Use CLKPRS to program the PSCLK frequency. Clock Prescale Register CLKPRS (read/write) Expanded Addr: ISA Addr: Reset State: F804H — 0000H 15 8 — — — — — — — PS8 7 0 PS7 Bit Number PS6 PS5 PS4 Bit Mnemonic PS3 PS2 PS1 PS0 Function 15–9 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.3.4 SSIO Baud-rate Control Register (SSIOBAUD) Use SSIOBAUD to enable the baud-rate generator and determine the baud-rate generator’s seven-bit down counter’s reload value (BV). SSIO Baud-rate Control SSIOBAUD (read/write) Expanded Addr: ISA Addr: Reset State: F484H — 00H 7 0 BEN Bit Number 7 BV6 BV5 BV4 BV3 Bit Mnemonic BEN BV2 BV1 BV0 Function Baud-rate Generator Enable: Setting this bit enables the baud-rate generator.
SYNCHRONOUS SERIAL I/O UNIT 13.3.5 SSIO Baud-rate Count Down Register (SSIOCTR) Read SSIOCTR to determine the status of the baud-rate generator. The down counter is reloaded when CV6:0 reaches zero or when a new value is written to SSIOBAUD. Baud-rate Count Down SSIOCTR (read only) Expanded Addr: ISA Addr: Reset State: F48AH — 00H 7 0 BSTAT Bit Number 7 CV6 CV5 CV4 CV3 Bit Mnemonic BSTAT CV2 CV1 CV0 Function Baud-rate Generator Status: 0 = The baud-rate generator is disabled.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SSIO Control 1 SSIOCON1 (read/write) Expanded Addr: ISA Addr: Reset State: F486H — C0H 7 0 TUE Bit Number 7 THBE TIE TEN ROE Bit Mnemonic TUE RHBF RIE REN Function Transmit Underrun Error: The transmitter sets this bit to indicate a transmit underrun error in the TEN transfer mode. Clear this bit to clear the error flag. If a one is written to TUE, it is ignored and TUE retains its previous value.
SYNCHRONOUS SERIAL I/O UNIT 13.3.7 SSIO Control 2 Register (SSIOCON2) Use the control bits TXMM and RXMM in SSIOCON2 to put the transmitter or receiver in master or slave mode. The AUTOTXM bit is used to determine if the TEN bit controls the transmitting of the data. SSIO Control 2 SSIOCON2 (read/write) Expanded Addr: ISA Addr: Reset State: F488H — 00H 7 0 — Bit Number — — — Bit Mnemonic 7–3 — 2 AUTOTXM — AUTOTXM TXMM RXMM Function Reserved.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.3.8 SSIO Transmit Holding Buffer (SSIOTBUF) Write the data words to be transmitted to SSIOTBUF. Use the interrupt controller, DMA unit or polling (read SSIOCON1) to determine when to write to the transmit buffer.
SYNCHRONOUS SERIAL I/O UNIT 13.3.9 SSIO Receive Holding Buffer (SSIORBUF) Read SSIORBUF to obtain the last data word received. Use the interrupt controller, DMA unit or polling (read SSIOCON1) to determine when to read the receive buffer.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.5 PROGRAMMING CONSIDERATIONS • When operating the transmitter in Master mode, and not in Autotransmit mode, you must ensure that the last character to be transmitted is in the process of being shifted out before disabling the transmitter. If the transmitter is disabled before the character has begun shifting, the character remains in the shift register and is shifted out when the transmitter is re-enabled.
SYNCHRONOUS SERIAL I/O UNIT Initialization routine for Synchronous Serial I/O Port. Parameters: Mode MasterTxRx BaudValue PreScale Enables receiver and transmitter; Enables TBE and RHBF interrupts Defines whether Tx and/or Rx are in Master Mode Enables Baud-rate generator and sets Baud-rate Value 9-bit Clock prescale value Returns: None Assumptions: PINCFG & SIOCFG should be configured before this is called. Prescale is only used if SIOCFG.2 is clear.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /* Init Baud Rate Generator */ _SetEXRegByte(SSIOBAUD,BaudValue); } _SetEXRegByte(SSIOCON1,Mode); _SetEXRegByte(SSIOCON2,MasterTxRx); }/* InitSSIO */ /***************************************************************************** SSerialReadWord: Description: Is a Polled serial port read function that will wait forever or until a character has been received from the serial port.
SYNCHRONOUS SERIAL I/O UNIT /* Disable Receiver */ _SetEXRegByte(SSIOCON1, SSControl); } else { // Slave Receiver, Receiver MUST already be Enabled /* Wait until Receive Holding Buffer is Full */ while(!(_GetEXRegByte(SSIOCON1) & SSIO_RHBF) ); } return (WORD)_GetEXRegWord(SSIORBUF); }/* SSerialReadWord */ /***************************************************************************** SSerialWriteWord: Description: Is a Polled serial port write function that will wait forever or until a character has been
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /* Get Control Register Ready to disable */ SSControl &= (~SSIO_TX_ENAB); // Clear the bit /* Set Buffer to Character */ _SetEXRegWord(SSIOTBUF,Ch); /* Enable Transmitter */ _SetEXRegByte(SSIOCON1, SSControl | SSIO_TX_ENAB); /* Wait until Transmit Holding Buffer is empty */ while( !(_GetEXRegByte(SSIOCON1) & SSIO_THBE) ); for(i=0;i < 4000; i++) { // Delay so transmit begins before disable _asm { nop } } /* Disable Transmitter */ _SetEXRegByte(SSIOCON1, SSC
SYNCHRONOUS SERIAL I/O UNIT Slave to clear the in-service bit. It is also assumed that the Master is not operating in AEOI, SFNM, or SMM. If the Master were in SMM or SFNM, a Specific EOI would have to be used. On the other hand, if the Master were operating in AEOI mode, no EOI signal would have to be sent. Syntax: Not called by user Real/Protected Mode: No changes required.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL None Syntax: Not called by user Real/Protected Mode: No changes required.
SYNCHRONOUS SERIAL I/O UNIT _SetEXRegWord(SSIOTBUF, value); value++; } else { /* Disable Transmitter and Transmitter interrupts */ for(i=0;i < 4000; i++) { // Delay so transmit begins before disable _asm { nop } } _SetEXRegByte(SSIOCON1,_GetEXRegByte(SSIOCON1) & 0xcf); // Clear TEN, TIE } } /* Service_THBE */ /***************************************************************************** Example Code showing SSIO transfer in which the transmitter is interrupt-driven and the receiver is polled: InitSSIO(SSI
14 CHIP-SELECT UNIT
CHAPTER 14 CHIP-SELECT UNIT The Chip-select Unit (CSU) of the processor can be used to eliminate external address and buscycle decoders in your system. The chip-selects generated by this unit can simplify external “glue logic” by providing signals that can be connected directly to the chip-enable inputs of external memory and I/O devices.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 14.2 CSU UPON RESET Upon reset of the processor, only the UCS channel is enabled and all other chip-selects are disabled. UCS is enabled for the entire memory space of the processor.
CHIP-SELECT UNIT 15-bit Channel Address bit x Address bit x Chip-select Channel Output bit x 15-bit Channel Mask A2533-01 Figure 14-1. Channel Address Comparison Logic The lower address bits are excluded from address comparisons (only 15 bits are compared). For memory addresses which have 26-bit addresses, the minimum channel address block size is 2 Kbytes; for I/O addresses with 16-bit addresses, the minimum channel address block size is 2 bytes.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 15-bit Channel Mask 15 Block Size 1 1 X X X X X X X X X X X X X X 0 2 = 2 Kbyte X X X X X X X X X X X X X 0 1 2 = 4 Kbyte X X X X X X X X X X X X 0 1 1 2 = 8 Kbyte 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 = 32768 Kbyte 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 = 65536 Kbyte 2 3 15 16 A2534-01 Figure 14-2.
CHIP-SELECT UNIT Example 1 This example establishes a single 32-Kbyte address block starting at 1340000H (a 32-Kbyte boundary). In this example, the 15-bit channel address is the starting address of the channel’s active address block (because there are no 1’s in the channel mask where there are 1’s in the channel address) .
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Example 2 This example establishes four 4-Kbyte address blocks starting at 0000000H, 0002000H, 0004000H, and 0006000H (4-Kbyte boundaries). 15 1 15-bit Channel Address 000000000000000 15-bit Channel Mask 000000000001101 25 Channel Active Address 0 00000000000XX0X XXXXXXXXXXX Because the least-significant 0 in the channel’s mask is in bit position 2, this channel’s active address block size is 22 = 4 Kbytes.
CHIP-SELECT UNIT Example 3 This example establishes four 2-Kbyte address blocks starting at 2413000H, 2433000H, 2613000H, and 2633000H. 15 15-bit Channel Address 100100000100110 15-bit Channel Mask 000010001000000 1 25 Channel Active Address 1001X000X100110 0 XXXXXXXXXXX Because the least-significant 0 in the channel’s mask is in bit position 1, this channel’s active address block size is 21 = 2 Kbytes.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Maximum Memory Address 2633800H Active 26337FFH 2633000H 2613FFFH 2613800H Active 26137FFH 2613000H 2433FFFH 2433800H Active 24337FFH 2433000H 2432FFFH 2413800H Active 24137FFH 2413000H 14-8
CHIP-SELECT UNIT Example 4 This example establishes two 16-Kbyte address blocks starting at 0E08000H and 0E28000H (16Kbyte boundaries). 15 15-bit Channel Address 15-bit Channel Mask 1 001110001010000 000000001000111 25 Channel Active Address 0 00111000X010XXX XXXXXXXXXXX Because the least-significant 0 in the channel mask is in bit position 4, this channel’s active address block size is 24 = 16 Kbytes.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 14.3.2 System Management Mode Support The processor supports four operating modes: system management mode (SMM), protected, real and virtual-86 mode. In order for a system to operate correctly in SMM, it must meet several requirements. The CSU provides support for some of these requirements. To use SMM, you must set aside a partition of memory, called SMRAM, for the SMM driver.
CHIP-SELECT UNIT 14.3.3 Bus Cycle Length Control Each chip-select channel controls how bus cycles to its address block terminate. Each channel can generate up to 31 wait states and then unconditionally terminate or wait for an external bus ready signal to terminate. If the channel is programmed for wait states and to sample external READY#, the external READY# is ignored until the programmed number of wait states has been inserted into the cycle.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Is any channel dependent on external ready? Yes Wait for smallest number of all overlapping regions' wait state values. No Wait for largest number of all overlapping regions' wait state values. Wait State READY# asserted? No Yes Complete bus cycle. A2392-02 Figure 14-3.
CHIP-SELECT UNIT 14.4 REGISTER DEFINITIONS Table 14-1 and Table 14-2 list the signals and registers associated with the chip-select unit. There are seven general-purpose chip-select channels (CSn) and one upper chip-select channel (UCS). Upon reset, the UCS is enabled with the entire 64 Mbyte memory address space as its address block. The UCS can be used to select a memory device at the top of the memory address space so that the processor can fetch the first instruction from address 3FFFFF0H after reset.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 14-2. CSU Registers Register PINCFG Expanded Address 0F826H (read/write) P2CFG Description Pin Configuration: Connects the CS6:5# signals to package pins. 0F822H (read/write) Port 2 Configuration: Connects the CS4:0# signals to package pins.
CHIP-SELECT UNIT 14.4.1 Pin Configuration Register (PINCFG) Use PINCFG bits 6 and 4 to connect the CS6# and CS5# signals to package pins. Pin Configuration PINCFG (read/write) Expanded Addr: ISA Addr: Reset State: F826H — 00H 7 0 — Bit Number PM6 PM5 Bit Mnemonic 7 — 6 PM6 PM4 PM3 PM2 PM1 PM0 Function Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit. Pin Mode: 0 = Selects CS6# at the package pin. 1 = Selects REFRESH# at the package pin.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 14.4.2 Port 2 Configuration Register (P2CFG) Use P2CFG bits 4–0 to connect the CS4:0# signals to package pins. Port 2 Configuration P2CFG (read/write) Expanded Addr: ISA Addr: Reset State: F822H — 00H 7 0 PM7 Bit Number 7 PM6 PM5 Bit Mnemonic PM7 PM4 PM3 PM2 PM1 Function Pin Mode: 0 = Selects P2.7 at the package pin. 1 = Selects CTS0# at the package pin. 6 PM6 Pin Mode: 0 = Selects P2.6 at the package pin.
CHIP-SELECT UNIT 14.4.3 Chip-select Address Registers The Address Register of each chip-select channel defines the address block that the channel responds to during an access. The value in this register is compared to A25:11 of the processor bus during a memory access and to A15:1 during an I/O access. A bus cycle whose address matches the non-masked (see “Chip-select Mask Registers” on page 14-19) bits of the Address Register causes the respective chip-select channel to have an address match.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Expanded Addr: Chip-select Low Address CSnADL (n = 0–6), UCSADL (read/write) ISA Addr: Reset State: F400H, F408H F410H, F418H F420H, F428H F430H, F438H — 0000H (CSnADL) FF6FH (UCSADL) 15 8 CA5 CA4 CA3 CA2 CA1 CASMM BS16 MEM 7 0 RDY Bit Number 15–11 — — WS4 Bit Mnemonic CA5:1 WS3 WS2 WS1 WS0 Function Chip-select Address Value Lower Bits: Defines the lower 5 bits of the channel’s 15-bit address.
CHIP-SELECT UNIT 14.4.4 Chip-select Mask Registers The Mask Register of each chip-select region is used to prevent bits from being compared with the starting address, thus masking them from the comparison. This masking allows you to specify the size of the region being defined. The mask should be set such that it masks the lower address bits being compared, up to the size that you would like the block to be. Write a channel’s 15-bit mask to the chip-select mask registers.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Chip-select Low Mask CSnMSKL (n = 0–6), UCSMSKL (read/write) Expanded Addr: ISA Addr: Reset State: F404H, F40CH F414H, F41CH F424H, F42CH F434H, F43CH — 0000H (CS nMSKL) FFFFH (UCSMSKL) 15 8 CM5 CM4 CM3 CM2 CM1 CMSMM — — — — — — — — — CSEN 7 0 Bit Number 15–11 Bit Mnemonic CM5:1 Function Chip-select Mask Value Lower Bits: Defines the lower 5 bits of the channel’s 15-bit mask.
CHIP-SELECT UNIT 14.5 DESIGN CONSIDERATIONS When designing with the CSU, consider the following: • Upon reset, UCS# is configured as a 16-bit chip-select signal. If the Boot device is only an 8-bit device, then BS8# must be asserted whenever UCS# is active (until the UCS channel can be reprogrammed to reflect an 8-bit region). One way of doing this is by connecting the UCS# pin directly to the BS8# pin, if there are no other devices that need to use the BS8# pin.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 14.6 PROGRAMMING CONSIDERATIONS When programming the CSU, consider the following: • When programming a chip-select channel, always program the Low Mask Register last. This ensures that all other bits are properly programmed before the region is enabled. When reprogramming the channel, always disable the channel before changing anything else.
CHIP-SELECT UNIT Assumptions: REMAPCFG register has Expanded I/O space access enabled (ESE bit set).
15 REFRESH CONTROL UNIT
CHAPTER 15 REFRESH CONTROL UNIT The Refresh Control Unit (RCU) simplifies the interface between the processor and a dynamic random access memory (DRAM) device by providing a way to generate periodic refresh requests and refresh addresses. These refresh requests and addresses can then be used by an external DRAM controller to generate the appropriate DRAM signals and addresses needed to perform refresh operations.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The RAS#-only method requires that the DRAM controller activate its RAS# signal when the RCU activates its REFRESH# signal. This causes the controller to drive the refresh address generated by the RCU onto the DRAM address inputs, refreshing the specified DRAM row. With this method, the controller need not assert the CAS# signal whenever the REFRESH# signal is active.
REFRESH CONTROL UNIT Interval Timer Unit Refresh Clock Interval Register 10-bit Interval Counter Processor Clock (CLK2/2) Timeout Control Unit Refresh Control Register S y s t e m B u s REFRESH# (pin mux) Refresh Request Refresh Acknowledge Address Generation Unit A25:14 Refresh Base Address Register 13-bit Address Counter A13:1 Refresh Address Register A2341-01 Figure 15-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 15.2.1 RCU Signals Table 15-1 describes the signals associated with the RCU. Table 15-1.
REFRESH CONTROL UNIT The 13-bit address counter is a combination of a binary counter and a 7-bit linear-feedback shift register. The binary counter produces address bits A13:8 and the linear-feedback shift register produces address bits A7:1. The shift register nonsequentially produces all 128 (27) possible combinations. Each time the lower seven bits cycle through all 128 combinations, the binary counter increments the upper 6 bits.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 15.4 REGISTER DEFINITIONS Table 15-2 provides an overview of the registers associated with the RCU. The following sections provide specific programming information for each register. Table 15-2.
REFRESH CONTROL UNIT 15.4.1 Refresh Clock Interval Register (RFSCIR) Use RFSCIR to program the interval timer unit’s 10-bit down counter. The refresh counter value is a function of DRAM specifications and processor frequency as follows: DRAM refresh period (µs) × processor clock (MHz) counter value = ----------------------------------------------------------------------------------------------------------------------------------------- , X where X = 128 or the # of DRAM rows, whichever is greater.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 15.4.2 Refresh Control Register (RFSCON) Use RFSCON to enable and disable the refresh control unit and to check the current interval counter value. Refresh Control RFSCON (read/write) Expanded Addr: ISA Addr: Reset State: F4A4H — 0000H 15 8 REN — — — — — CV9 CV8 CV7 CV6 CV5 CV4 CV3 CV2 CV1 CV0 7 0 Bit Number 15 Bit Mnemonic REN Function Refresh Control Unit Enable: This bit enables or disables the refresh control unit.
REFRESH CONTROL UNIT 15.4.3 Refresh Base Address Register (RFSBAD) Use RFSBAD to set up the memory region that needs refreshing. The value written to this register forms the upper bits (A25:14) of the refresh address. The RFSBAD register can be used in conjunction with the Chip Select Unit (CSU) to generate a chip-select for the DRAM region during refresh cycles.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 15.4.4 Refresh Address Register (RFSADD) RFSADD contains the bits A13:1 of the refresh address. The lowest address bit is not used because most DRAM devices contain word-wide memory arrays; for all refresh operations, the lowest address bit remains set.
REFRESH CONTROL UNIT 15.5 DESIGN CONSIDERATIONS Consider the following when programming the RCU. • The system address bus does not contain an address A0 signal; instead, it uses the BLE# and the BHE# pins to generate the lowest address bit. During all refresh operations, BLE# and BHE# are driven high. This needs to be noted especially when interfacing to an 8-bit wide Pseudo Static RAM (PSRAM) device. The lowest address bit generated by the refresh address counter is A1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • If the counter value stored in the Refresh Clock Interval Register (RFSCIR) is <8 and the RCU is enabled, the RCU always has bus control and other devices will never gain access to the bus. This is because refresh requests have the highest priority in the bus arbitration scheme and you are requesting the bus too often. • There are two common methods of refreshing DRAM: RAS#-only and CAS#-beforeRAS#.
REFRESH CONTROL UNIT Upper Address Row Address Buffer Row Address OE_ROW# Intel386™ EX Embedded Processor REFRESH# BHE# CSn# BLE# Address RAS# PLD CAS# Paged DRAM OE_COL# Lower Address Column Address Buffer Column Address Note: A single mux can be used in place of the row and column address buffers. A3264-02 Figure 15-7.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Lower Address Row Address Row Address Buffer OE_ROW# Intel386™ EX Embedded Processor REFRESH# BHE# CSn# BLE# Address RAS# PLD CAS# Non-paged DRAM OE_COL# Upper Address Column Address Buffer Column Address Note: A single mux can be used in place of the row and column address buffers. A3265-02 Figure 15-8. RAS# Only Refresh Logic: Non-Paged Mode 15.6 PROGRAMMING CONSIDERATIONS REFRESH# and CS6# share a package pin.
REFRESH CONTROL UNIT Parameters: Counter_Value Value of the refresh interval Returns: Error Codes: E_BADVECTOR E_OK User input an invalid parameter Executed correctly Assumptions: None Syntax: #define REFRESH_INTERVAL 0x186 //Counter value for DRAM with // 1024 rows and a refresh period // of 16 msec (25 MHz Processor Clock) int error_code; error_code = InitRCU(REFRESH_INTERVAL); Real/Protected Mode: No changes required *****************************************************************************/ ext
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Parameters: None Returns: Refresh Interval Counter Value Assumptions: NONE Syntax: WORD CounterValue; CounterValue = Get_RCUCounterValue(); Real/Protected Mode: No changes required ******************************************************************************/ extern WORD Get_RCUCounterValue(void) { WORD Counter_Value; Counter_Value = _GetEXRegWord(RFSCON) & 0x3ff; // Counter value contained // in bits RFSCON9:0 return(Counter_Value); }/* Get_RCUCounterVal
16 INPUT/OUTPUT PORTS
CHAPTER 16 INPUT/OUTPUT PORTS Input/Output (I/O) ports allow you to transfer information between the processor and the surrounding system circuitry. I/O ports are typically used to read system status, monitor system operation, output device status, configure system options, and generate control signals. The Intel386™ EX processor’s I/O port pins are multiplexed with peripheral pin functions.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL I n t e r n a l PnCFG.x Internal Peripherals 1 0 Pn.x PnDIR.x B u s PnLTC.x PnPIN.x A2393-01 Figure 16-1. I/O Port Block Diagram 16.1.1 Port Functionality The function of a bi-directional port pin is controlled by the state of the Port Control Latch (PnLTC). This is shown in Figure 16-2.
INPUT/OUTPUT PORTS From Internal Peripheral Read Port Data latch 0 PnLTC Q 1 D S Q# CK Write Port Data Latch Pin Read Port Pin State PnPIN SYNC To Internal Peripheral 0 PnDIR Internal Data Bus (F-Bus) VCC or VSS† 1 Q S D CK Q# Write Port Direction 0 1 S Read Port Direction From Internal Peripheral Direction Control PnCFG Q D Q# Write Port Control CK Read Port Control † Depends on peripheral's inactive state A3266-01 Figure 16-2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The output of the Pin Configuration latch (PnCFG) selects whether the I/O port or peripheral is connected to the pin. When the port is programmed to act as a peripheral pin, both the data for the pin and the directional control signal for the pin come from the associated integrated peripheral. When a bi-directional port pin is programmed as an I/O port, all port parameters are under software control.
INPUT/OUTPUT PORTS Table 16-1. Pin Multiplexing Port Pin Peripheral Function Direction (2) Internal Peripheral DCD0# I SIO0 RTS0# O SIO0 wk 1 DTR0# O SIO0 wk 1 DSR0# I SIO0 RI0# I SIO0 LOCK# O BIU HOLD I BIU HLDA O BIU wk 1 CS0# O CSU wk 1 CS1# O CSU P2.2 wk 1 CS2# O CSU P2.3 wk 1 CS3# O CSU Reset Status(1) Signal P1.0 wk 1 P1.1 wk 1 P1.2 P1.3 P1.4 wk 1 P1.5 wk 1 P1.6 wk 0 P1.7 wk 0 P2.0 P2.1 Pin P2.4 wk 1 CS4# O CSU P2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 16.2 REGISTER DEFINITIONS Each port has three control registers and a status register associated with it (Table 16-2). The control registers (PnCFG, PnDIR, and PnLTC) can be both read and written. The status register (PnPIN) can only be read. All four registers reside in I/O address space. Table 16-2.
INPUT/OUTPUT PORTS 16.2.1 Pin Configuration You select the operating mode of each pin by writing to the associated bit in the PnCFG registers (Figure 16-3 gives an abbreviated version of these registers; for the complete register descriptions, see Appendix D). Setting a bit selects peripheral mode; clearing a bit selects I/O mode. Internal peripherals control pins configured for peripheral mode, while the PnDIR (Figure 16-4) and PnLTC (Figure 16-5) registers control pins configured for I/O mode.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Port DIrection PnDIR (n=1–3) (read/write) Expanded Addr: ISA Addr: Reset State: F864H, F86CH, F874H — FFH 7 0 PD7 Bit Number 7–0 PD6 PD5 PD4 PD3 Bit Mnemonic PD7:0 PD2 PD1 PD0 Function Pin Direction: 0 = Configures the pin as a complementary output. 1 = Configures the pin as an open-drain output or high-impedance input. Figure 16-4.
INPUT/OUTPUT PORTS Port Pin State PnPIN (n=1–3) (read only) Expanded Addr: ISA Addr: Reset State: F860H, F868H, F870H — XXH 7 0 PS7 Bit Number 7–0 PS6 PS5 Bit Mnemonic PS7:0 PS4 PS3 PS2 PS1 PS0 Function Pin State: Reading a PS bit returns the logic state present on the associated port pin. Figure 16-6.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 16.2.2 Initialization Sequence After a device reset, a weak pull-up or pull-down resistor holds each pin high or low until user software writes to the PnCFG register. The pins are configured as inputs in I/O port mode. To ensure that the pins are initialized correctly and that the weak resistors are turned off, follow this suggested initialization sequence.
INPUT/OUTPUT PORTS 16.4 PROGRAMMING CONSIDERATIONS 16.4.1 I/O Ports Code Example The following code example contains a software routine that initializes the I/O port pins. See Appendix C for the included header files. #include #include “80386ex.h” #include “ev386ex.h” /******************************************************************************* Init_IOPorts: Description: This function initializes the direction and mode of the I/O port pins.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #define #define #define #define #define #define CS2 CS3 CS4 RXD0 TXD0 CTS0 0x4 0x8 0X10 0x20 0X40 0X80 // Port #define #define #define #define #define #define #define #define 3 configuration defines TMROUT0 0x1 TMROUT1 0x2 INT0 0x4 INT1 0x8 INT2 0x10 INT3 0x20 PWRDWN 0x40 COMCLK 0x80 // Port #define #define #define #define #define #define #define #define #define Direction defines P0_IN 0x1 P1_IN 0x2 P2_IN 0x4 P3_IN 0x8 P4_IN 0x10 P5_IN 0x20 P6_IN 0x4
INPUT/OUTPUT PORTS { /* Select pin values _SetEXRegByte(P1LTC, _SetEXRegByte(P2LTC, _SetEXRegByte(P3LTC, */ PortLtc1); PortLtc2); PortLtc3); /* Select pin directions */ _SetEXRegByte(P1DIR, PortDir1); _SetEXRegByte(P2DIR, PortDir2); _SetEXRegByte(P3DIR, PortDir3); /* Turn off weak resistors and select either I/O or peripheral mode */ _SetEXRegByte(P1CFG, Port1); _SetEXRegByte(P2CFG, Port2); _SetEXRegByte(P3CFG, Port3); } /* Init_IOPorts */ 16-13
17 WATCHDOG TIMER UNIT
CHAPTER 17 WATCHDOG TIMER UNIT The watchdog timer (WDT) unit can function as a general-purpose timer, a software watchdog timer, or a bus monitor, or it can be disabled. This chapter is organized as follows: • • • • • • Overview (see below) Watchdog Timer Unit Operation (page 17-3) Disabling the WDT (page 17-6) Register Definitions (page 17-7) Design Considerations (page 17-12) Programming Considerations (page 17-12) 17.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL READY#). In bus monitor mode, the ADS# signal from the bus interface unit (BIU) reloads the down-counter and the READY# signal stops it. The READY# signal can be generated either externally or internally, using the WDTRDY bit in the PWRCON register (Figure 17-5). If this bit is deasserted, then an external READY# is required to terminate the cycle when the WDT times out (WDTOUT is asserted) in Bus Monitor mode.
WATCHDOG TIMER UNIT 17.1.1 WDT Signals Table 17-1 describes the signals associated with the WDT. Table 17-1. WDT Signals Signal ADS# Device Pin or Internal Signal Device pin Description Address Status (from the bus interface unit): Indicates that the processor is driving a valid bus-cycle definition and address onto its pins. Bus monitor mode reloads and starts the down-counter each time ADS# is asserted.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The reload registers hold a user-defined value that reloads the down-counter when one of the following reload events occurs: • In watchdog mode, when system software executes a specific instruction sequence (called a lockout sequence) to the WDTCLR location • In bus monitor mode, when the bus interface unit asserts ADS# • In all modes, when the down-counter reaches zero Software can read the status register to determine the mode of the WDT, and can read
WATCHDOG TIMER UNIT 17.2.3 Software Watchdog Mode In software watchdog mode, system software must periodically reload the down-counter with a reload value or the timer expires and asserts WDTOUT. The reload value depends on the design of the system software. In general, determining the proper reload value requires software analysis and some experimentation. After reset, the WDT defaults to general-purpose timer mode. Unless you intervene, the WDT times out after 4 million (222) processor clock cycles.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • To change the reload value, write the new values to the WDTRLDH and WDTRLDL registers, as described in steps 1 and 2 above. • To disable or enable bus monitor mode, write to the bus monitor bit (BUSMON): — 0 = disabled — 1 = enabled 17.
WATCHDOG TIMER UNIT 17.4 REGISTER DEFINITIONS This section describes the registers associated with the WDT, and explains how these registers can be used to enable and use each WDT mode. Table 17-2 describes the registers associated with the WDT. Table 17-2. WDT Registers Register WDTCLR Address 0F4C8H Description Watchdog Timer Clear: Write the lockout sequence to this location. Circuitry at this address decodes the lockout sequence to enable watchdog mode, reload the counter, or both.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL WDT Counter Value (High) WDTCNTH (read only) Expanded Addr: ISA Addr: Reset State: F4C4H — 003FH 15 8 WC31 WC30 WC29 WC28 WC27 WC26 WC25 WC24 WC23 WC22 WC21 WC20 WC19 WC18 WC17 WC16 7 0 WDT Counter Value (Low) WDTCNTL (read only) Expanded Addr: ISA Addr: Reset State: F4C6H — FFFFH 15 8 WC15 WC14 WC13 WC12 WC11 WC10 WC9 WC8 WC7 WC6 WC5 WC4 WC3 WC2 WC1 WC0 7 0 Bit Number High 15–0 Low 15–0 Bit Mnemonic Function
WATCHDOG TIMER UNIT WDT Status WDTSTATUS (read/write) Expanded Addr: F4CAH ISA Addr: — Reset State: 00H 7 0 WDTEN Bit Number 7 — — — — Bit Mnemonic WDTEN — BUSMON CLKDIS Function Watchdog Mode Enabled: This read-only bit indicates whether watchdog mode is enabled. Only a lockout sequence can set this bit and only a device reset can clear it. 0 = Watchdog mode disabled 1 = Watchdog mode enabled 6–2 — Reserved.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL WDT Reload Value (High) WDTRLDH (read/write) Expanded Addr: ISA Addr: Reset State: F4C0H — 003FH 15 8 WR31 WR30 WR29 WR28 WR27 WR26 WR25 WR24 WR23 WR22 WR21 WR20 WR19 WR18 WR17 WR16 7 0 WDT Reload Value (Low) WDTRLDL (read/write) Expanded Addr: ISA Addr: Reset State: F4C2H — FFFFH 15 8 WR15 WR14 WR13 WR12 WR11 WR10 WR9 WR8 WR7 WR6 WR5 WR4 WR3 WR2 WR1 WR0 7 0 Bit Number High 15–0 Low 15–0 Bit Mnemonic Function
WATCHDOG TIMER UNIT Power Control Register PWRCON (read/write) Expanded Addr: ISA Addr: Reset State: F800H — 00H 7 0 — Bit Number — — — WDTRDY Bit Mnemonic HSREADY PC1 PC0 Function 7–4 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. 3 WDTRDY Watch Dog Timer Ready: 0 = An external READY must be generated to terminate the cycle when the WDT times out in Bus Monitor Mode.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 17.5 DESIGN CONSIDERATIONS This section outlines design considerations for the watchdog timer unit. Depending on the system configuration, a WDT timeout can cause a maskable interrupt, a nonmaskable interrupt, or a system reset. Maskable interrupt The WDT timeout signal is internally inverted and connected to the interrupt control unit’s slave IR7 line.
WATCHDOG TIMER UNIT See Appendix C for included header files. #include #include #include #include “80386ex.h” “ev386ex.h” /***************************************************************************** ReLoadDownCounter: Description: This function initiates a lockout sequence which results in the setting of the WDTEN bit in the status register. By setting WDTEN, the software watchdog mode is enabled.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Parameters: None Returns: 16-bit down-counter value Assumptions: None Syntax: WORD counter_value; counter_value = GetWDT_Count(); Real/Protected Mode: No changes required.
WATCHDOG TIMER UNIT WDT_BusMonitor(Enable); Real/Protected Mode: No changes required.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL routine in Interrupt Vector Table */ Enable8259Interrupt(IR2,IR7); /* Enable slave interrupt to master(IR2), Enable slave IR2 */ _enable(); /* Enable Interrupts */ } /* EnableWDTInterrupt */ /***************************************************************************** wdtISR: Description: Interrupt Service Routine for Watchdog Timer Parameters: None Returns: None Assumptions: None Syntax: Not called by user; Interrupt Control Unit executes this routine
18 JTAG TEST-LOGIC UNIT
CHAPTER 18 JTAG TEST-LOGIC UNIT The JTAG test-logic unit enables you to test both the device logic and the interconnections between the device and the board (system) it is plugged into. The term JTAG refers to the Joint Test Action Group, the IEEE technical subcommittee that developed the testability standard published as Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture† and its supplement, Standard 1149.1a-1993.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • Place all device output pins into their inactive drive (high-impedance) state, allowing external hardware to drive connections that the processor normally drives The test-logic unit (Figure 18-1) is fully compliant with IEEE Standard 1149.1. It consists of the test access port (TAP), the test access port controller, the instruction register (IR), and three data registers (IDCODE, BYPASS, and BOUND).
JTAG TEST-LOGIC UNIT 18.2 TEST-LOGIC UNIT OPERATION 18.2.1 Test Access Port (TAP) The test access port consists of five dedicated pins (four inputs and one output). It is through these pins that all communication with the test-logic unit takes place. This unit has its own clock (TCK) and reset (TRST#) pins, so it is independent of the rest of the device. The test-logic unit can read or write its registers even if the rest of the device is in reset or powerdown.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 18.2.2 Test Access Port (TAP) Controller The TAP controller is a finite-state machine that is capable of 16 states (Figure 18-2).
JTAG TEST-LOGIC UNIT Table 18-2. TAP Controller State Descriptions (Sheet 2 of 2) State Description Next State (on TCK Rising Edge) TMS = 0 TMS = 1 Capture-IR Test-Logic-Reset Loads the SAMPLE/PRELOAD instruction instruction (0001) into the instruction register. Shift-IR Exit1-IR Shift-IR Shifts the SAMPLE/PRELOAD instruction one stage toward TDO while shifting the new instruction in from TDI on each rising edge of TCK.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 1 Test - Logic - Reset 0 0 Run - Test/ Idle 1 Select DR - Scan 1 Select IR - Scan 0 1 0 1 Capture DR Capture IR 0 0 Shift IR 1 1 1 Exit1 DR 1 Exit1 IR 0 0 0 0 Pause DR Pause IR 1 1 0 Exit2 DR 1 0 0 Shift DR 0 1 Exit2 IR 1 1 Update DR Update IR 0 1 0 A2356-01 Figure 18-2.
JTAG TEST-LOGIC UNIT 18.2.3 Instruction Register (IR) An instruction opcode is clocked serially through the TDI pin into the four-bit instruction register (Figure 18-3). The instruction determines which data register is affected. Table 18-4 lists the instructions with their binary opcodes, descriptions, and associated registers. Instruction Register IR Reset State (Using TRST#): 02H 3 0 INST3 Bit Number 3–0 Bit Mnemonic INST3:0 INST2 INST1 INST0 Function Instruction opcode.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 18.2.4 Data Registers The test-logic unit uses three data registers: bypass, identification code, and boundary-scan. The instruction determines which data register is used. The single-bit bypass register (BYPASS) provides a minimal-length serial path between TDI and TDO. During board-level testing, you can use this path for any devices that are not currently under test. This speeds access to the data registers for the devices that are being tested.
JTAG TEST-LOGIC UNIT The boundary-scan register (BOUND) holds data to be applied to the pins or data observed at the pins. Each bit corresponds to a specific pin (Table 18-5). Table 18-5. Boundary-scan Register Bit Assignments Bit Pin Bit Pin Bit 0 M/IO# 1 D/C# Pin Bit Pin 25 A15 26 A16/CAS0 50 TMROUT2 75 P2.2 51 TMRGATE2 76 P2.3 2 W/R# 27 A17/CAS1 52 INT4/TMRCLK0 77 P2.4 3 READY# 28 A18/CAS2 53 INT5/TMRGATE0 78 DACK0# 4 BS8# 29 A19 54 INT6/TMRCLK1 79 P2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 18.3 TESTING This section explains how to use the test-logic unit to test the device and the board interconnections. For any test, you must load an instruction and perform an instruction-scan cycle, then supply the correct sequence of ones and zeros to move the TAP controller through the required states to perform the test. 18.3.1 Identifying the Device The IDCODE instruction allows you to determine the contents of a device’s IDCODE register.
JTAG TEST-LOGIC UNIT Typically, you would use the SAMPLE/PRELOAD instruction to load data onto the boundaryscan register’s latched parallel outputs before loading the EXTEST instruction. You load the EXTEST instruction by manipulating TDI to supply the binary opcode (0000). The Update-DR state drives the preloaded data onto the pins for the first test. Stimuli for the remaining tests are shifted in while the results for the completed tests are shifted out. 18.3.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 18.4 TIMING INFORMATION The test-logic unit’s input/output timing is as specified in IEEE 1149.1. Figure 18-5 shows the pin timing associated with loading the instruction register and Figure 18-6 shows the timing for loading a given data register.
JTAG TEST-LOGIC UNIT TCK TMS Test - Logic - Reset Select - IR - Scan Select - DR - Scan Run - Test / Idle Exit1 - DR Update - DR Shift - DR Exit2 - DR Pause - DR Exit1 - DR Shift - DR Capture - DR Run - Test / Idle Select - DR - Scan Controller State TDI Data Input to IR IR Shift-Register IDCode Parallel Output of IR Instruction Data Input to TDR TDR Shift-Register Parallel Output of TDR Test Data Register Instruction Register TDO Enable New Data Old Data Inactive Active Inac
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 18.5 DESIGN CONSIDERATIONS This section outlines considerations for the test-logic unit. • The JTAG Test-Logic Unit must be reset upon power-up using the TRST# pin. (To do this, invert the RESET signal and send this inverted RESET to the TRST# pin). If this is not done, the processor may power-up with the JTAG test-logic unit in control of the device pins, and the system does not initialize properly.
A SIGNAL DESCRIPTIONS
APPENDIX A SIGNAL DESCRIPTIONS This appendix provides reference information for the pins and signals of the device, including the states of certain pins during reset, idle, powerdown, and hold. The information is presented in four tables: • • • • Table A-1 defines the abbreviations used in Table A-2 to describe the signals. Table A-2 describes each signal. Table A-3 defines the abbreviations used in Table A-4 to describe the pin states.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table A-2 is an alphabetical list of the signals available at the device pins. The Multiplexed With column lists other signals that share a pin with the signal listed in the Signal column. Table A-2. Description of Signals Available at the Device Pins (Sheet 1 of 6) Signal Type A25:19 A18:16 A15:1 O ADS# O Name and Description Address Bus: Outputs physical memory or port I/O addresses.
SIGNAL DESCRIPTIONS Table A-2. Description of Signals Available at the Device Pins (Sheet 2 of 6) Signal Type CTS1# CTS0# I D15:0 I/O Name and Description Clear to Send: Indicates that the modem or data set is ready to exchange data with the SIO channel. Data Bus: Multiplexed With (Alternate Function) EOP# P2.7 — Inputs data during memory read, I/O read, and interrupt acknowledge cycles; outputs data during memory write and I/O write cycles.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table A-2. Description of Signals Available at the Device Pins (Sheet 3 of 6) Signal HOLD Type I Name and Description Hold Request: Multiplexed With (Alternate Function) P1.6 An external bus master asserts HOLD to request control of the local bus. The processor finishes the current nonlocked bus transfer, releases the bus signals, and asserts HLDA.
SIGNAL DESCRIPTIONS Table A-2. Description of Signals Available at the Device Pins (Sheet 4 of 6) Signal Type P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 I/O P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 I/O PWRDOWN O Name and Description Port 2: General-purpose, bidirectional I/O port. Port 3: General-purpose, bidirectional I/O port. Powerdown Output: Multiplexed With (Alternate Function) CTS0# TXD0 RXD0 CS4# CS3# CS2# CS1# CS0# COMCLK PWRDOWN INT3 INT2 INT1 INT0 TMROUT1/INT8 TMROUT0/INT9 P3.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table A-2. Description of Signals Available at the Device Pins (Sheet 5 of 6) Signal SMI# Type ST Name and Description System Management Interrupt: Multiplexed With (Alternate Function) — Causes the device to enter System Management Mode. SMI# is the highest priority external interrupt. SMIACT# O System Management Interrupt Active: — Indicates that the processor is in System Management Mode.
SIGNAL DESCRIPTIONS Table A-2. Description of Signals Available at the Device Pins (Sheet 6 of 6) Signal TMS Type I Name and Description Test Mode Select: Multiplexed With (Alternate Function) — Controls the sequence of the test-logic unit’s TAP controller states. Sampled on the rising edge of TCK. TRST# ST Test Reset: — Resets the test-logic unit’s TAP controller. Asynchronously clears the data registers and initializes the instruction register to 0010 (the IDCODE instruction opcode).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table A-3 defines the abbreviations used in Table A-4 to describe the pin states. Table A-3.
SIGNAL DESCRIPTIONS Table A-4 lists the states of output and bidirectional pins after reset and during idle mode, powerdown, and hold. Table A-4.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table A-4. Pin States After Reset and During Idle, Powerdown, and Hold (Sheet 2 of 2) STXCLK I/O WH Q X or Q(1) Q TDO O Z or Q(2) Z or Q(2) Z or Q(2) Z or Q(2) TMROUT2 O WH Q X or Q(1) Q Q(1) Q TMROUT1:0 O WL Q X or TXD1 O 1 Q X or Q(1) Q TXD0 O WL Q X or Q(1) Q UCS# O 0 Q X 1 WDTOUT O 0 Q X Q W/R# O 0 1 1 Z WR# O 1 1 1 1 NOTES: 1. X if clock source is internal; Q if clock source is external. 2.
B COMPATIBILITY WITH THE PC/AT* ARCHITECTURE
APPENDIX B COMPATIBILITY WITH THE PC/AT* ARCHITECTURE The Intel386™ EX embedded processor is NOT 100% PC/AT* compatible. Due to compatibility issues, not all PC software executes on the Intel386 EX processor. In addition, not all ISA/PC104 cards operate in an Intel386 EX processor system. It is the responsibility of the designer to determine if a specific PC/AT software or hardware package operates on an Intel386 EX processor system.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL To eliminate these problems with an 8237A DMA controller, the Intel386 EX processor integrates a DMA controller unit that differs from the 8237A DMA in these ways: • It provides two channels, each capable of either byte or word transfers. • Each channel can transfer data between any combination of memory and I/O. The Bus Interface Unit supports both external fly-by and two-cycle operation.
COMPATIBILITY WITH THE PC/AT* ARCHITECTURE HLDA Processor AEN MASTER# (From PC/AT* Bus) A2504-01 Figure B-1. Derivation of AEN Signal in a Typical PC/AT System For systems based on Intel386 EX processor, the AEN signal could be derived as shown in Figure B-2. Notice that since the DMA acknowledge signals are used instead of a generic HLDA, there is no need to incorporate the REFRESH# signal in the logic. DACK0# Processor DACK AEN DACK1# MASTER# (From PC/AT* Bus) A2503-01 Figure B-2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL the Intel386 EX embedded processor) demonstrates the design of a Synchronous Expansion Bus that is very similar to the ISA bus. The Intel386 EX processor is not capable of providing a 100% compatible ISA bus due to its lack of DMA channels and interrupt inputs. B.1.
COMPATIBILITY WITH THE PC/AT* ARCHITECTURE B.1.7 Port B The Port B register found on the PC/AT is not supported on the Intel386 EX processor. It can be implemented externally with a PLD. The EXPLR1 (Explorer Evaluation board) supports this Port B. B.2 B.2.1 SOFTWARE CONSIDERATIONS FOR A PC/AT SYSTEM ARCHITECTURE Embedded Basic Input Output System (BIOS) The BIOS provides low-level drivers to interface to the hardware.
C EXAMPLE CODE HEADER FILES
APPENDIX C EXAMPLE CODE HEADER FILES This appendix contains the header files called by the code examples that are included in several chapters of this manual. Section C.1 contains the register definitions for each code routine. Section C.2 contains the variable definitions. C.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #define OCW2SDOS #define OCW3MDOS #define OCW3SDOS 0x00A0 0x0020 0x00A0 /* CONFIGURATION Registers */ #define DMACFG 0xF830 #define INTCFG 0xF832 #define TMRCFG 0xF834 #define SIOCFG 0xF836 #define P1CFG 0xF820 #define P2CFG 0xF822 #define P3CFG 0xF824 #define PINCFG 0xF826 /* WATCHDOG TIMER Registers */ #define WDTRLDH 0xF4C0 #define WDTRLDL 0xF4C2 #define WDTCNTH 0xF4C4 #define WDTCNTL 0xF4C6 #define WDTCLR 0xF4C8 #define WDTSTATUS 0xF4CA /* TIMER CONT
EXAMPLE CODE HEADER FILES #define IIR0 0xF4FA #define LCR0 0xF4FB #define MCR0 0xF4FC #define LSR0 0xF4FD #define MSR0 0xF4FE #define SCR0 0xF4FF /* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */ #define RBR0DOS 0x03F8 #define THR0DOS 0x03F8 #define TBR0DOS 0x03F8 #define DLL0DOS 0x03F8 #define IER0DOS 0x03F9 #define DLH0DOS 0x03F9 #define IIR0DOS 0x03FA #define LCR0DOS 0x03FB #define MCR0DOS 0x03FC #define LSR0DOS 0x03FD #define MSR0DOS 0x03FE #define SCR0DOS 0x03FF /* ASYNCHRONOUS SERIAL CHANNEL 1
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #define SSIOCON2 #define SSIOCTR 0xF488 0xF48A /* CHIP #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define Registers */ 0xF400 0xF402 0xF404 0xF406 0xF408 0xF40A 0xF40C 0xF40E 0xF410 0xF412 0xF414 0xF416 0xF418 0xF41A 0xF41C 0xF41E 0xF420 0xF422 0xF424
EXAMPLE CODE HEADER FILES #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define DMACMD1 DMASTS DMASRR DMAMSK DMAMOD1 DMACLRBP DMACLR DMACLRMSK DMAGRPMSK DMA0REQL DMA0REQH DMA1REQL DMA1REQH DMABSR DMACHR DMAIS DMACMD2 DMAMOD2 DMAIEN DMAOVFE DMACLRTC DMA1TARPL DMA1TARPH DMA0TARPH DMA0TARPL DMA0BYCH DMA1BYCH 0xF008 0xF008 0xF009 0xF00A 0xF00B 0xF00
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL C.
EXAMPLE CODE HEADER FILES #define MPIN_INT0 0x4 #define MPIN_INT1 0x8 #define MPIN_INT2 0x10 #define MPIN_INT3 0x20 /* ICU Master External Cascade IRs */ #define MCAS_IR1 0x2 #define MCAS_IR2 0x4 #define MCAS_IR5 0x20 #define MCAS_IR6 0x40 #define MCAS_IR7 0x80 /* ICU Slave Pins */ #define SPIN_INT4 0x1 #define SPIN_INT5 0x2 #define SPIN_INT6 0x4 #define SPIN_INT7 0x8 /* ICU IRQ Mask Values*/ #define IR0 0x1 #define IR1 0x2 #define IR2 0x4 #define IR3 0x8 #define IR4 0x10 #define IR5 0x20 #define IR6 0x40
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /************ Asynchronous Serial I/O Port defines ***********/ #define SIO_0 0 #define SIO_1 1 #define SIO0_IRQ #define SIO1_IRQ 4 3 #define #define #define #define 0x0 0x1 0x2 0x3 SIO_5DATA SIO_6DATA SIO_7DATA SIO_8DATA #define SIO_1STOPBIT #define SIO_2STOPBIT 0x0 0x4 #define #define #define #define #define 0x0 0x8 0x18 0x28 0x38 SIO_NOPARITY SIO_ODDPARITY SIO_EVNPARITY SIO_FRC0PARITY SIO_FRC1PARITY #define SIO_SETBREAK 0x40 #define #define
EXAMPLE CODE HEADER FILES #define SIO_TX_EMPTY 0x40 /* Offsets from beginning of SIO port addresses */ #define RBR 0 #define TBR 0 #define DLL 0 #define IER 1 #define DLH 1 #define IIR 2 #define LCR 3 #define MCR 4 #define LSR 5 #define MSR 6 #define SCR 7 #define SIO0_BASE 0xF4F8 #define SIO1_BASE 0xF8F8 /* Define Function Macros */ #define GetSIO0Status() _GetEXRegByte(LSR0) #define GetSIO1Status() _GetEXRegByte(LSR1) #define GetSIO0InterruptID() _GetEXRegByte(IIR0) #define GetSIO1InterruptID() _GetEXR
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL typedef enum { DMA_Channel0 = 0, DMA_Channel1 = 1 } DMAChannelEnum; typedef enum { ERR_NONE = 0, ERR_BADINPUT = -1 } ERREnum; /* DMA Function Definitions */ int SetDMAReqIOAddr(int nChannel, WORD wIO); int SetDMATargMemAddr(int nChannel, void *ptMemory); int SetDMAXferCount(int nChannel, DWORD lCount); int EnableDMAHWRequests(int nChannel); int DisableDMAHWRequests(int nChannel); void InitDMA(void); void InitDMA1ForSerialXmitter(void); /*************** Po
EXAMPLE CODE HEADER FILES #define #define #define #define #define #define #define #define P1_IN P2_IN P3_IN P4_IN P5_IN P6_IN P7_IN Px_OUT 0x2 0x4 0x8 0x10 0x20 0x40 0x80 0 /* Pin configuration defines */ #define RTS1 0x1 #define SSIOTX 0 #define DTR1 0x2 #define SRXCLK 0 #define TXD1 0x4 #define DACK1 0 #define CTS1 0x8 #define EOP 0 #define CS5 0x10 #define DACK0 0 #define TIMER2 0x20 #define COPROC 0 #define REFRESH 0x40 #define CS6 0 /* Port I/O Function Definitions */ extern void Init_IOPorts (BYTE
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #define TMR_GATE_EXTRN #define TMR_OUT_ENABLE #define TMR_OUT_DISABLE 0x2 0x1 0 #define TMR_ENABLE #define TMR_DISABLE 1 0 /* Timer Macros Definitions */ #define DisableTimer() \ _SetEXRegByte( TMRCFG, (_GetEXRegByte(TMRCFG) | 0x80)) #define EnableTimer() \ _SetEXRegByte( TMRCFG, (_GetEXRegByte(TMRCFG) & 0x7f)) /* Timer Function Definitions */ extern int InitTimer (int Unit, WORD Mode, BYTE Inputs, BYTE Output, WORD InitCount, int Enable); extern void
EXAMPLE CODE HEADER FILES BYTE PreScale); extern WORD SSerialReadWord(BYTE MasterSlave); extern void SSerialWriteWord(WORD Ch,BYTE MasterSlave); void interrupt far SSIO_ISR(void); extern void Service_RHBF(void); extern void Service_THBE(void); /********************* Watch Dog Timer ***********************/ #define SetWatchDogReload(ReloadHi,ReloadLow) \ _SetEXRegWord(WDTRLDL,ReloadLow);_SetEXRegWord(WDTRLDH,ReloadHi); #define WatchDogClockDisable()\ _SetEXRegByte(WDTSTATUS, _GetEXRegByte(WDTSTATUS) | BIT0
D SYSTEM REGISTER QUICK REFERENCE
APPENDIX D SYSTEM REGISTER QUICK REFERENCE D.1 PERIPHERAL REGISTER ADDRESSES Table D-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table D-1.
SYSTEM REGISTER QUICK REFERENCE Table D-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table D-1.
SYSTEM REGISTER QUICK REFERENCE Table D-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table D-1.
SYSTEM REGISTER QUICK REFERENCE D.2 CLKPRS Clock Prescale Register CLKPRS (read/write) Expanded Addr: ISA Addr: Reset State: F804H — 0000H 15 8 — — — — — — — PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 7 0 Bit Number Bit Mnemonic Function 15–9 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. 8–0 PS8:0 Prescale Value: These bits determine the divisor that is used to generate PSCLK.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CSnADH (UCSADH) D.3 Chip-select High Address CSnADH (n = 0–6), UCSADH (read/write) Expanded Addr: ISA Addr: Reset State: F402H, F40AH F412H, F41AH F422H, F42AH F432H, F43AH — 0000H (CS nADH) FFFFH (UCSADH) 15 8 — — — — — — CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 7 0 Bit Number Bit Mnemonic Function 15–10 — Reserved; for compatibility with future devices, write zeros to these bits.
SYSTEM REGISTER QUICK REFERENCE CSnADL (UCSADL) D.4 Chip-select Low Address CSnADL (n = 0–6), UCSADL (read/write) Expanded Addr: ISA Addr: Reset State: F400H, F408H F410H, F418H F420H, F428H F430H, F438H — 0000H (CSnADL) FF6FH (UCSADL) 15 8 CA5 CA4 CA3 CA2 CA1 CASMM BS16 MEM RDY — — WS4 WS3 WS2 WS1 WS0 7 0 Bit Number 15–11 Bit Mnemonic CA5:1 Function Chip-select Address Value Lower Bits: Defines the lower 5 bits of the channel’s 15-bit address.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CSnMSKH (UCSMSKH) D.5 Chip-select High Mask CSnMSKH (n = 0–6), UCSMSKH (read/write) Expanded Addr: ISA Addr: Reset State: F406H, F40EH F416H, F41EH F426H, F42EH F436H, F43EH — 0000H (CS nMSKH) FFFFH (UCSMSKH) 15 8 — — — — — — CM15 CM14 CM13 CM12 CM11 CM10 CM9 CM8 CM7 CM6 7 0 Bit Number Bit Mnemonic Function 15–10 — Reserved; for compatibility with future devices, write zeros to these bits.
SYSTEM REGISTER QUICK REFERENCE CSnMSKL (UCSMSKL) D.6 Chip-select Low Mask CSnMSKL (n = 0–6), UCSMSKL (read/write) Expanded Addr: ISA Addr: Reset State: F404H, F40CH F414H, F41CH F424H, F42CH F434H, F43CH — 0000H (CS nMSKL) FFFFH (UCSMSKL) 15 8 CM5 CM4 CM3 CM2 CM1 CMSMM — — — — — — — — — CSEN 7 0 Bit Number 15–11 Bit Mnemonic CM5:1 Function Chip-select Mask Value Lower Bits: Defines the lower 5 bits of the channel’s 15-bit mask.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DLLn AND DLHn D.
SYSTEM REGISTER QUICK REFERENCE D.8 DMABSR DMA Bus Size DMABSR (write only) Expanded Addr: ISA Addr: Reset State: F018H — X1X10000B 7 0 — Bit Number RBS — TBS Bit Mnemonic — — 0 CS Function 7 — Reserved; for compatibility with future devices, write zero to this bit. 6 RBS Requester Bus Size: Specifies the requester’s data bus width for the channel specified by bit 0. 0 = 16-bit bus 1 = 8-bit bus 5 — Reserved; for compatibility with future devices, write zero to this bit.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.9 DMACFG DMA Configuration DMACFG (read/write) Expanded Addr: ISA Addr: Reset State: F830H — 00H 7 0 D1MSK Bit Number 7 D1REQ2 D1REQ1 D1REQ0 D0MSK Bit Mnemonic D1MSK D0REQ2 D0REQ1 D0REQ0 Function DMA Acknowledge 1 Mask: 0 = DMA channel 1’s acknowledge (DMAACK1#) signal is not masked. 1 = Masks DMA channel 1’s acknowledge (DMAACK1#) signal. Useful when channel 1’s request (DREQ1) input is connected to an internal peripheral.
SYSTEM REGISTER QUICK REFERENCE D.10 DMACHR DMA Chaining DMACHR (write only) Expanded Addr: ISA Addr: Reset State: F019H — 00H 7 0 — — Bit Number — — Bit Mnemonic 7–3 — 2 CE — CE 0 CS Function Reserved; for compatibility with future devices, write zeros to these bits. Chaining Enable: 0 = Disables the chaining buffer-transfer mode for the channel specified by bit 0. 1 = Enables the chaining buffer-transfer mode for the channel specified by bit 0.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.11 DMACMD1 DMA Command 1 DMACMD1 (write only) Expanded Addr: ISA Addr: Reset State: F008H 0008H 00H 7 0 — Bit Number — — PRE — Bit Mnemonic 7–5 — 4 PRE CE — — Function Reserved; for compatibility with future devices, write zeros to these bits. Priority Rotation Enable: 0 = Priority is fixed based on value in DMACMD2. 1 = Enables the rotation method for changing the bus control priority structure.
SYSTEM REGISTER QUICK REFERENCE D.12 DMACMD2 DMA Command 2 DMACMD2 (write only) Expanded Addr: ISA Addr: Reset State: F01AH — 08H 7 0 — Bit Number — — — Bit Mnemonic PL1 PL0 ES DS Function 7–4 — Reserved; for compatibility with future devices, write zeros to these bits. 3–2 PL1:0 Low Priority Level Set: Use these bits to assign a particular bus request to the lowest priority level in fixed priority mode.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.13 DMAGRPMSK DMA Group Channel Mask DMAGRPMSK (read/write) Expanded Addr: ISA Addr: Reset State: F00FH 000FH 03H 7 0 — Bit Number — — — Bit Mnemonic 7–2 — 1 HRM1 — — HRM1 HRM0 Function Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. Hardware Request Mask 1: 0 = Channel 1’s hardware requests are not masked. 1 = Masks (disables) channel 1’s hardware requests.
SYSTEM REGISTER QUICK REFERENCE D.14 DMAIEN DMA Interrupt Enable DMAIEN (read/write) Expanded Addr: ISA Addr: Reset State: F01CH — 00H 7 0 — Bit Number — — — Bit Mnemonic 7–2 — 1 TC1 — — TC1 TC0 Function Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. Transfer Complete 1: 0 = Disables Transfer Complete interrupts. 1 = Connects channel 1’s transfer complete signal to the interrupt control unit’s DMAINT input.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.15 DMAIS DMA Interrupt Status DMAIS (read only) Expanded Addr: ISA Addr: Reset State: F019H — 00H 7 0 — Bit Number — TC1 TC0 Bit Mnemonic 7–6 — 5 TC1 — — CI1 CI0 Function Reserved. These bits are undefined. Transfer Complete 1: When set, this bit indicates that channel 1 has completed a buffer transfer (either its byte count expired or it received an EOP# input). This bit is set only if bit 1 of the interrupt enable register is set.
SYSTEM REGISTER QUICK REFERENCE D.16 DMAMOD1 DMA Mode 1 DMAMOD1 (write only) Expanded Addr: ISA Addr: Reset State: F00BH 000BH 00H 7 0 DTM1 DTM0 Bit Number 7–6 TI AI TD1 Bit Mnemonic DTM1:0 TD0 0 CS Function Data-transfer Mode: 00 = Demand 01 = Single 10 = Block 11 = Cascade 5 TI Target Increment/Decrement: 0 = Causes the target address to be incremented after each data transfer in a buffer transfer.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.17 DMAMOD2 DMA Mode 2 DMAMOD2 (write only) Expanded Addr: ISA Addr: Reset State: F01BH — 00H 7 0 BCO RD Bit Number 7 TD RH RI Bit Mnemonic BCO TH 0 CS Function Bus Cycle Option: 0 = Selects the fly-by data transfer bus cycle option for the channel specified by bit 0. 1 = Selects the two-cycle data transfer bus cycle option for the channel specified by bit 0.
SYSTEM REGISTER QUICK REFERENCE D.18 DMAMSK DMA Individual Channel Mask DMAMSK (write only) Expanded Addr: ISA Addr: Reset State: F00AH 000AH 04H 7 0 — — Bit Number — — Bit Mnemonic 7–3 — 2 HRM — HRM 0 CS Function Reserved; for compatibility with future devices, write zeros to these bits. Hardware Request Mask: 0 = Unmasks (enables) hardware requests for the channel specified by bit 0. 1 = Masks (disables) hardware requests for the channel specified by bit 0.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.
SYSTEM REGISTER QUICK REFERENCE D.20 DMAOVFE DMA Overflow Enable DMAOVFE (read/write) Expanded Addr: ISA Addr: Reset State: F01DH — 0AH 7 0 — Bit Number — Bit Mnemonic 7–4 — 3 ROV1 — — ROV1 TOV1 ROV0 TOV0 Function Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.21 DMASRR DMA Software Request (read format) DMASRR Expanded Addr: ISA Addr: Reset State: F009H 0009H 00H 7 0 — — Bit Number — — — Bit Mnemonic 7–2 — 1 SR1 — SR1 SR0 Function Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. Software Request 1: When set, this bit indicates that channel 1 has a software request pending.
SYSTEM REGISTER QUICK REFERENCE D.22 DMASTS DMA Status DMASTS (read only) Expanded Addr: ISA Addr: Reset State: F008H 0008H 00H 7 0 — — Bit Number R1 R0 Bit Mnemonic 7–6 — 5 R1 — — TC1 TC0 Function Reserved. These bits are undefined. Request 1: When set, this bit indicates that channel 1 has a hardware request pending. When the request is removed, this bit is cleared. 4 R0 Request 0: When set, this bit indicates that channel 0 has a hardware request pending.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.23 ICW1 (MASTER AND SLAVE) Initialization Command Word 1 ICW1 (master and slave) (write only) master Expanded Addr: F020H ISA Addr: 0020H Reset State: XXH slave F0A0H 00A0H XXH 7 0 0 0 Bit Number 0 RSEL1 Bit Mnemonic LS 0 0 1 Function 7–5 — Clear these bits to guarantee device operation. 4 RSEL1 Register Select 1 (Also see OCW2 and OCW3): ICW1, OCW2, and OCW3 are accessed through the same addresses.
SYSTEM REGISTER QUICK REFERENCE D.24 ICW2 (MASTER AND SLAVE) Initialization Command Word 2 ICW2 (master and slave) (write only) Expanded Addr: ISA Addr: Reset State: master F021H 0021H XXH slave F0A1H 00A1H XXH 7 0 T7 Bit Number 7–3 T6 T5 T4 T3 Bit Mnemonic T7:3 0 0 0 Function Base Interrupt Type: Write the base interrupt vector’s five most-significant bits to these bits. 2–0 T2:0 Clear these bits to guarantee device operation. D.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.26 ICW3 (SLAVE) Initialization Command Word 3 ICW3 (slave) (write only) Expanded Addr: ISA Addr: Reset State: F0A1H 00A1H XXH 7 0 0 Bit Number 0 0 0 0 Bit Mnemonic 0 1 0 Function 7–2 — Clear these bits to guarantee device operation. 1 — Set this bit to guarantee device operation. 0 — Clear this bit to guarantee device operation. D.
SYSTEM REGISTER QUICK REFERENCE D.28 IDCODE Identification Code Register IDCODE Reset State: 2027 0013H (3V) 2827 0013H (5V) 31 24 0 0 1 0 0 (3V) 1 (5V) 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 23 16 15 8 7 0 Bit Number Bit Mnemonic 31–28 V3:0 Function Device version number. 27–12 PN15:0 Device part number. 11–1 MFR10:0 Manufacturer identification (compressed JEDEC106-A code). 0 IDP Identification Present. Always true for this device.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.29 IERn Interrupt Enable IER0, IER1 (read/write) IER0 Expanded Addr: F4F9H ISA Addr: 03F9H Reset State: 00H IER1 F8F9H 02F9H 00H 7 0 — — Bit Number Bit Mnemonic 7–4 — 3 MS — — MS RLS TBE RBF Function Reserved; for compatibility with future devices, write zeros to these bits. Modem Status Interrupt Enable: 0 = Modem input signal changes do not cause interrupts.
SYSTEM REGISTER QUICK REFERENCE D.30 IIRn Interrupt ID IIR0, IIR1 (read only) Expanded Addr: ISA Addr: Reset State: IIR0 F4FAH 03FAH 01H IIR1 F8FAH 02FAH 01H 7 0 — Bit Number — — — Bit Mnemonic 7–3 — 2 IS2:1 — IS2 IS1 IP# Function Reserved. These bits are undefined. Interrupt Source: If an interrupt is pending (bit 0 = 0), these bits specify which status signal caused the pending interrupt.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.31 INTCFG Interrupt Configuration INTCFG (read/write) Expanded Addr: ISA Addr: Reset State: F832H — 00H 7 0 CE Bit Number 7 IR3 IR4 SWAP IR6 Bit Mnemonic CE IR5/IR4 IR1 IR0 Function Cascade Enable: 0 = Disables the cascade signals CAS2:0 from appearing on the A18:16 address lines during interrupt acknowledge cycles. 1 = Enables the cascade signals CAS2:0, providing access to external slave 82C59A devices.
SYSTEM REGISTER QUICK REFERENCE D.32 IR Instruction Register IR Reset State (Using TRST#): 02H 3 0 INST3 Bit Number 3–0 Bit Mnemonic INST3:0 INST2 INST1 INST0 Function Instruction opcode. At reset (using TRST#, or after 5 TCK cycles with TMS held low), this field is loaded with 0010, the opcode for the IDCODE instruction. Instructions are shifted into this field serially through the TDI pin. (Table 18-4 lists the valid instruction opcodes.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.33 LCRn Serial Line Control LCR0, LCR1 (read/write) Expanded Addr: ISA Addr: Reset State: LCR0 F4FBH 03FBH 00H LCR1 F8FBH 02FBH 00H 7 0 DLAB Bit Number 7 SB SP EPS PEN Bit Mnemonic DLAB STB WLS1 WLS0 Function Divisor Latch Access Bit: This bit determines which of the multiplexed registers is accessed. 0 = Allows access to the receiver and transmit buffer registers (RBRn and TBRn) and the interrupt enable register (IERn).
SYSTEM REGISTER QUICK REFERENCE D.34 LSRn Serial Line Status LSR0, LSR1 (read only) Expanded Addr: ISA Addr: Reset State: LSR0 F4FDH 03FDH 60H LSR1 F8FDH 02FDH 60H 7 0 — Bit Number TE TBE BI Bit Mnemonic FE PE OE RBF Function 7 — Reserved. This bit is undefined. 6 TE Transmitter Empty: The transmitter sets this bit to indicate that the transmit shift register and transmit buffer register are both empty. Writing to the transmit buffer register clears this bit.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.35 MCRn Modem Control MCR0, MCR1 (read/write) Expanded Addr: ISA Addr: Reset State: MCR0 F4FCH 03FCH 00H MCR1 F8FCH 02FCH 00H 7 0 — Bit Number — — LOOP OUT2 Bit Mnemonic OUT1 RTS DTR Function 7–5 — Reserved; for compatibility with future devices, write zeros to these bits. 4 LOOP Loop Back Test Mode: 0 = Normal mode 1 = Setting this bit puts the SIOn into diagnostic (or loop back test) mode.
SYSTEM REGISTER QUICK REFERENCE D.36 MSRn Modem Status MSR0, MSR1 (read only) Expanded Addr: ISA Addr: Reset State: MSR0 F4FEH 03FEH X0H MSR1 F8FEH 02FEH X0H 7 0 DCD Bit Number 7 RI DSR CTS DDCD Bit Mnemonic DCD TERI DDSR DCTS Function Data Carrier Detect: This bit is the complement of the data carrier detect (DCDn#) input. In diagnostic test mode, this bit is equivalent to MCRn.3 (OUT2). 6 RI Ring Indicator: This bit is the complement of the ring indicator (RIn#) input.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.37 OCW1 (MASTER AND SLAVE) Operation Command Word 1 OCW1 (master and slave) (read/write) Expanded Addr: ISA Addr: Reset State: master F021H 0021H XXH slave F0A1H 00A1H XXH 7 0 M7 Bit Number 7–0 M6 M5 Bit Mnemonic M7:0 M4 M3 M2 M1 M0 Function Mask IR: 0 = Enables interrupts on the corresponding IR signal. 1 = Disables interrupts on the corresponding IR signal. NOTE: Setting the mask bit does not clear the respective interrupt pending bit.
SYSTEM REGISTER QUICK REFERENCE D.38 OCW2 (MASTER AND SLAVE) Operation Command Word 2 OCW2 (master and slave) (write only) Expanded Addr: ISA Addr: Reset State: master F020H 0020H XXH slave F0A0H 00A0H XXH 7 0 R Bit Number SL EOI RSEL1 RSEL0 Bit Mnemonic L2 L1 L0 Function 7 R The Rotate (R), Specific Level (SL), and End-of-Interrupt (EOI) Bits: 6 SL These bits change the priority structure and/or send an EOI command.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.39 OCW3 (MASTER AND SLAVE) Operation Command Word 3 OCW3 (master and slave) (write only) Expanded Addr: ISA Addr: Reset State: master F020H 0020H XXH slave F0A0H 00A0H XXH 7 0 0 Bit Number ESMM SMM RSEL1 RSEL0 Bit Mnemonic POLL ENRR RDSEL Function 7 — 6 ESMM Enable Special Mask Mode (ESMM) and Special Mask Mode (SMM): 5 SMM Use these bits to enable or disable special mask mode.
SYSTEM REGISTER QUICK REFERENCE D.40 P1CFG Port 1 Configuration P1CFG (read/write) Expanded Addr: ISA Addr: Reset State: F820H — 00H 7 0 PM7 Bit Number 7 PM6 PM5 Bit Mnemonic PM7 PM4 PM3 PM2 PM1 PM0 Function Pin Mode: 0 = Selects P1.7 at the package pin. 1 = Selects HLDA at the package pin. 6 PM6 Pin Mode: 0 = Selects P1.6 at the package pin. 1 = Selects HOLD at the package pin. 5 PM5 Pin Mode: 0 = Selects P1.5 at the package pin. 1 = Selects LOCK# at the package pin.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.41 P2CFG Port 2 Configuration P2CFG (read/write) Expanded Addr: ISA Addr: Reset State: F822H — 00H 7 0 PM7 Bit Number 7 PM6 PM5 Bit Mnemonic PM7 PM4 PM3 PM2 Function Pin Mode: 0 = Selects P2.7 at the package pin. 1 = Selects CTS0# at the package pin. 6 PM6 Pin Mode: 0 = Selects P2.6 at the package pin. 1 = Selects TXD0 at the package pin. 5 PM5 Pin Mode: 0 = Selects P2.5 at the package pin. 1 = Selects RXD0 at the package pin.
SYSTEM REGISTER QUICK REFERENCE D.42 P3CFG Port 3 Configuration P3CFG (read/write) Expanded Addr: ISA Addr: Reset State: F824H — 00H 7 0 PM7 Bit Number 7 PM6 PM5 Bit Mnemonic PM7 PM4 PM3 PM2 PM1 PM0 Function Pin Mode: 0 = Selects P3.7 at the package pin. 1 = Selects COMCLK at the package pin. 6 PM6 Pin Mode: 0 = Selects P3.6 at the package pin. 1 = Selects PWRDOWN at the package pin. 5 PM5 Pin Mode: 0 = Selects P3.5 at the package pin. 1 = Connects master IR7 to the package pin (INT3).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.43 PINCFG Pin Configuration PINCFG (read/write) Expanded Addr: ISA Addr: Reset State: F826H — 00H 7 0 — Bit Number PM6 PM5 Bit Mnemonic 7 — 6 PM6 PM4 PM3 PM2 PM1 PM0 Function Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit. Pin Mode: 0 = Selects CS6# at the package pin. 1 = Selects REFRESH# at the package pin.
SYSTEM REGISTER QUICK REFERENCE D.44 PnDIR Port DIrection PnDIR (n=1–3) (read/write) Expanded Addr: ISA Addr: Reset State: F864H, F86CH, F874H — FFH 7 0 PD7 Bit Number 7–0 PD6 PD5 PD4 Bit Mnemonic PD7:0 PD3 PD2 PD1 PD0 Function Pin Direction: 0 = Configures the pin as a complementary output. 1 = Configures the pin as an open-drain output or high-impedance input.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.45 PnLTC Port Data Latch PnLTC (n=1–3) (read/write) Expanded Addr: F862H, F86AH, F872H ISA Addr: — Reset State: FFH 7 0 PL7 Bit Number 7–0 PL6 PL5 PL4 PL3 Bit Mnemonic PL7:0 PL2 PL1 PL0 Function Port Data Latch: Writing a value to a PL bit causes that value to be driven onto the corresponding pin. For a complementary output, write the desired pin value to its PL bit. This value is strongly driven onto the pin.
SYSTEM REGISTER QUICK REFERENCE D.47 POLL (MASTER AND SLAVE) Poll Status Byte POLL (master and slave) (read only) Expanded Addr: ISA Addr: Reset State: master F020H 0020H XXH slave F0A0H 00A0H XXH 7 0 INT Bit Number 7 — — — Bit Mnemonic INT — L2 L1 L0 Function Interrupt Pending: 0 = No request pending. 1 = Indicates that a device attached to the 82C59A requires servicing. 6–3 — Reserved. These bits are undefined.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.48 PORT92 Port 92 Configuration PORT92 (read/write) Expanded Addr: ISA Addr: Reset State: F092H 0092H XXXXXX10B 7 0 — Bit Number — — — Bit Mnemonic 7–2 — 1 A20G — — A20G CPURST Function Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. A20 Grounded: 0 = Clearing this bit forces address line A20 to 0. This bit affects addresses generated only by the core.
SYSTEM REGISTER QUICK REFERENCE D.49 PWRCON Power Control Register PWRCON (read/write) Expanded Addr: ISA Addr: Reset State: F800H — 00H 7 0 — Bit Number — — — WDTRDY Bit Mnemonic HSREADY PC1 PC0 Function 7–4 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. 3 WDTRDY Watch Dog Timer Ready: 0 = An external READY must be generated to terminate the cycle when the WDT times out in Bus Monitor Mode.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.50 RBRn Receive Buffer RBR0, RBR1 (read only) Expanded Addr: ISA Addr: Reset State: RBR0 F4F8H 03F8H XXH RBR1 F8F8H 02F8H XXH 7 0 RB7 RB6 Bit Number 7–0 RB5 RB4 Bit Mnemonic RB7:0 RB3 RB2 RB1 RB0 Function Receive Buffer Bits: These bits make up the last word received. The receiver shifts bits in, starting with the least-significant-bit.
SYSTEM REGISTER QUICK REFERENCE D.51 REMAPCFG Address Configuration Register REMAPCFG Expanded Addr: PC/AT Address: Reset State: 0022H 0022H 0000H 15 8 ESE — — — — — — — — S1R S0R ISR IMR DR — TR 7 0 Bit Number Bit Mnemonic Function 15 ESE 0 = Disables expanded I/O space 1 = Enables expanded I/O space 14–7 — Reserved.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.52 RFSADD Refresh Address RFSADD (read/write) Expanded Addr: ISA Addr: Reset State: F4A6H — 00FFH 15 8 — — RA13 RA12 RA11 RA10 RA9 RA8 7 0 RA7 Bit Number RA6 RA5 RA4 Bit Mnemonic 15–14 — 13–1 RA13:1 RA3 RA2 RA1 1 Function Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. Refresh Address Bits: These bits comprise A13:1 of the refresh address.
SYSTEM REGISTER QUICK REFERENCE D.54 RFSCIR Refresh Clock Interval RFSCIR (read/write) Expanded Addr: ISA Addr: Reset State: F4A2H — 0000H 15 8 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 7 0 Bit Number Bit Mnemonic Function 15–10 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. 9–0 RC9:0 Refresh Counter Value: Write the counter value to these ten bits. The interval counter counts down from this value.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.56 SCRn Scratch Pad SCR0, SCR1 (read/write) Expanded Addr: ISA Addr: Reset State: SCR0 F4FFH 03FFH XXH SCR1 F8FFH 02FFH XXH 7 0 SP7 Bit Number 7–0 D-56 SP6 Bit Mnemonic SP7:0 SP5 SP4 SP3 SP2 SP1 SP0 Function Writing and reading this register has no effect on SIOn operation.
SYSTEM REGISTER QUICK REFERENCE D.57 SIOCFG SIO and SSIO Configuration SIOCFG (read/write) Expanded Addr: ISA Addr: Reset State: F836H — 00H 7 0 S1M Bit Number 7 S0M Bit Mnemonic S1M — — — SSBSRC S1BSRC S0BSRC Function SIO1 Modem Signal Connections: 0 = Connects the SIO1 modem input signals to the package pins. 1 = Connects the SIO1 modem input signals internally. 6 S0M SIO0 Modem Signal Connections: 0 = Connects the SIO0 modem input signals to the package pins.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.58 SSIOBAUD SSIO Baud-rate Control SSIOBAUD (read/write) Expanded Addr: ISA Addr: Reset State: F484H — 00H 7 0 BEN Bit Number 7 BV6 BV5 BV4 BV3 Bit Mnemonic BEN BV2 BV1 BV0 Function Baud-rate Generator Enable: Setting this bit enables the baud-rate generator. Clearing this bit disables the baud-rate generator, clears the baud-rate count value, and forces the baud rate clock to zero.
SYSTEM REGISTER QUICK REFERENCE D.59 SSIOCON1 SSIO Control 1 SSIOCON1 (read/write) Expanded Addr: F486H ISA Addr: — Reset State: C0H 7 0 TUE Bit Number 7 THBE TIE TEN ROE Bit Mnemonic TUE RHBF RIE REN Function Transmit Underrun Error: The transmitter sets this bit to indicate a transmit underrun error in the TEN transfer mode. Clear this bit to clear the error flag. If a one is written to TUE, it is ignored and TUE retains its previous value.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.60 SSIOCON2 SSIO Control 2 SSIOCON2 (read/write) Expanded Addr: ISA Addr: Reset State: F488H — 00H 7 0 — Bit Number — — — Bit Mnemonic 7–3 — 2 AUTOTXM — AUTOTXM TXMM RXMM Function Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits.
SYSTEM REGISTER QUICK REFERENCE D.61 SSIOCTR Baud-rate Count Down SSIOCTR (read only) Expanded Addr: ISA Addr: Reset State: F48AH — 00H 7 0 BSTAT Bit Number 7 CV6 CV5 CV4 CV3 Bit Mnemonic BSTAT CV2 CV1 CV0 Function Baud-rate Generator Status: 0 = The baud-rate generator is disabled. 1 = The baud-rate generator is enabled. 6–0 CV6:0 Current Value: These bits indicate the current value of the baud-rate down counter. D.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.63 SSIOTBUF Transmit Holding Buffer SSIOTBUF (read/write) Expanded Addr: ISA Addr: Reset State: F480H — 0000H 15 8 TB15 TB14 TB13 TB12 TB11 TB10 TB9 TB8 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 0 Bit Number 15–0 Bit Mnemonic TB15:0 Function Transmit Buffer Bits: These bits make up the next data word to be transmitted. The control logic loads this word into the transmit shift register.
SYSTEM REGISTER QUICK REFERENCE D.65 TMRCFG . Timer Configuration TMRCFG (read/write) Expanded Addr: ISA Addr: Reset State: F834H — 00H 7 TMRDIS Bit Number 7 0 SWGTEN GT2CON CK2CON GT1CON Bit Mnemonic TMRDIS CK1CON GT0CON CK0CON Function Timer Disable: 0 = Enables the CLKINn signals. 1 = Disables the CLKIN n signals. 6 SWGTEN Software GATEn Enable 0 = Connects GATE n to either the VCC pin or the TMRGATEn pin.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.66 TMRCON Timer Control (Control Word Format) TMRCON Expanded Addr: ISA Addr: Reset State: F043H 0043H XXH 7 0 SC1 Bit Number 7–6 SC0 RW1 RW0 Bit Mnemonic SC1:0 M2 M1 M0 CNTFMT Function Select Counter: Use these bits to specify a particular counter. The selections you make for bits 5–0 define this counter’s operation. 00 = counter 0 01 = counter 1 10 = counter 2 11 is not an option for TMRCON’s control word format.
SYSTEM REGISTER QUICK REFERENCE D.67 TMRn Timer n (Read Format) TMRn (n = 0–2) Expanded Addr: ISA Addr: Reset State: F040H, F041H F042H 0040H, 0041H 0042H XXH 7 0 CV7 Bit Number 7–0 CV6 CV5 CV4 Bit Mnemonic CV7:0 CV3 CV2 CV1 CV0 Function Count Value: These bits contain the counter’s count value. When reading the counter’s count value, follow the read selection specified in the counter’s control word.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Timer n (Status Format) TMRn (n = 0–2) Expanded Addr: ISA Addr: Reset State: F040H, F041H F042H 0040H, 0041H 0042H XXH 7 OUTPUT Bit Number 7 0 NULCNT RW1 RW0 Bit Mnemonic OUTPUT M2 M1 M0 CNTFMT Function Output Status: This bit indicates the current state of the counter’s output signal. 0 = OUTn is low 1 = OUTn is high 6 NULCNT Count Status: This bit indicates whether the latest count written to the counter has been loaded.
SYSTEM REGISTER QUICK REFERENCE D.68 UCSADH See “CSnADH (UCSADH)” on page D-8. D.69 UCSADL See “CSnADL (UCSADL)” on page D-9. D.70 UCSMSKH See “CSnMSKH (UCSMSKH)” on page D-10. D.71 UCSMSKL See “CSnMSKL (UCSMSKL)” on page D-11.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.
SYSTEM REGISTER QUICK REFERENCE D.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.74 WDTSTATUS WDT Status WDTSTATUS (read/write) Expanded Addr: F4CAH ISA Addr: — Reset State: 00H 7 0 WDTEN Bit Number 7 — — — — Bit Mnemonic WDTEN — BUSMON CLKDIS Function Watchdog Mode Enabled: This read-only bit indicates whether watchdog mode is enabled. Only a lockout sequence can set this bit and only a device reset can clear it. 0 = Watchdog mode disabled 1 = Watchdog mode enabled 6–2 — 1 BUSMON Reserved.
E INSTRUCTION SET SUMMARY
APPENDIX E INSTRUCTION SET SUMMARY This appendix provides reference information for the Intel386™ processor family instruction set. The appendix is organized as follows: • Instruction Encoding and Clock Count Summary (see below) • Instruction Encoding (page E-22) E.1 INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY To calculate elapsed time for an instruction, multiply the instruction clock count, as listed in Table E-1, by the processor clock period (e.g., 62.5 ns for 16 MHz).
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Wait states: Wait states add 1 clock per wait state to instruction execution for each data access. Table E-1 lists the instructions with their formats and execution times. The description of the notes for Table E-1 begins on page E-20. See “Instruction Encoding” on page E-22 for the definition of the terms used in this table. Table E-1.
INSTRUCTION SET SUMMARY Table E-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1.
INSTRUCTION SET SUMMARY Table E-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1.
INSTRUCTION SET SUMMARY Table E-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1.
INSTRUCTION SET SUMMARY Table E-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1.
INSTRUCTION SET SUMMARY Table E-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1.
INSTRUCTION SET SUMMARY Table E-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1.
INSTRUCTION SET SUMMARY Table E-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1.
INSTRUCTION SET SUMMARY Table E-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1.
INSTRUCTION SET SUMMARY Table E-1.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1.
INSTRUCTION SET SUMMARY b = 10 for register with immediate to register b = 11 for memory with immediate to register. e. An exception may occur, depending on the value of the operand. f. LOCK# is automatically asserted, regardless of the presence or absence of the LOCK# prefix. g. LOCK# is asserted during descriptor table accesses. Notes h through r apply to Protected Virtual Address Mode only: h.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL E.2 INSTRUCTION ENCODING All instruction encodings are subsets of the general instruction format shown in Figure E-1. Instructions consist of one or two primary opcode bytes, possibly an address specifier consisting of the “mod r/m” byte and “scaled index” byte, a displacement if required, and an immediate data field if required. Within the primary opcode or opcodes, smaller encoding fields may be defined.
INSTRUCTION SET SUMMARY Table E-2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Unless specified otherwise, instructions with 8-bit and 16-bit operands do not affect the contents of the high-order bits of the extended registers. E.2.2 Encoding of Instruction Fields Within the instruction are several fields indicating register selection, addressing mode, and so on. The exact encodings of these fields are defined in the next several section. E.2.2.
INSTRUCTION SET SUMMARY Table E-5. Encoding of reg Field When w Field is Present in Instruction Register Specified by reg Field During 16-bit Data Operations Function of w Field reg (when w = 0) (when w = 1) AL CL DL BL AH CH DH BH AX CX DX BX SP BP SI DI 000 001 010 011 100 101 110 111 Register Specified by reg Field During 32-bit Data Operations Function of w Field reg (when w = 0) (when w = 1) AL CL DL BL AH CH DH BH EAX ECX EDX EBX ESP EBP ESI EDI 000 001 010 011 100 101 110 111 E.2.2.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL E.2.2.4 Encoding of Address Mode Except for special instructions, such as PUSH or POP, where the addressing mode is pre-determined, the addressing mode for the current instruction is specified by addressing bytes following the primary opcode. The primary addressing byte is the “mod r/m” byte, and a second byte of addressing information, the “s-i-b” (scale-index-base) byte can be specified.
INSTRUCTION SET SUMMARY Table E-7.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-8.
INSTRUCTION SET SUMMARY Table E-9.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL E.2.2.5 Encoding of Operation Direction (d) Field In many two-operand instructions the d field is present to indicate which operand is considered the source and which is the destination. Table E-10. Encoding of Operation Direction (d) Field E.2.2.6 d Direction of Operation 0 Register/Memory<--Register “reg” field indicates source operand; “mod r/m” or “mod ss index base” indicates destination operand.
INSTRUCTION SET SUMMARY E.2.2.8 Encoding of Control or Debug or Test Register (eee) Field For the loading and storing of the Control, Debug and Test registers. Table E-13. When Interpreted as Control Register Field eee Code Reg Name 000 010 011 CR0 CR2 CR3 NOTE: Do not use any other encoding Table E-14. When Interpreted as Debug Register Field eee Code Reg Name 000 001 010 011 110 111 DR0 DR1 DR2 DR3 DR6 DR7 NOTE: Do not use any other encoding Table E-15.
GLOSSARY
GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this manual. (Chapter 1, GUIDE TO THIS MANUAL, discusses notational conventions.) Assert The act of making a signal active (enabled). The polarity (high/low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To assert RD# is to drive it low; to assert HLDA is to drive it high. BIOS Basic input/output system.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL be mapped into this space. In this manual, the terms DOS address and PC/AT address are synonymous. DOS-compatible Mode The addressing mode in which the internal timer, interrupt controller, serial I/O ports, and DMA controller are mapped into the DOS address space. This mode decodes only the lower 10 address bits, so the expanded address space is inaccessible.
GLOSSARY Interrupt Response Time The amount of time required to complete an interrupt acknowledge cycle and transfer program control to the interrupt service routine. Interrupt Resolution The delay between the time that the interrupt controller receives an interrupt request and the time that the master 82C59A presents the request to the CPU. ISR Interrupt service routine. A user-supplied software routine designed to service specific interrupt requests. JTAG Joint Test Action Group.
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL PC/AT Address Space Addresses 0H–03FFH. The internal timers, interrupt controller, serial I/O ports, and DMA controller can be mapped into this space. In this manual, the terms DOS address and PC/AT address are synonymous. Pipelining A bus interface technique that controls the address and status outputs so the outputs for the next bus cycle become valid before the end of the current bus cycle, allowing external bus cycles to overlap.
GLOSSARY communications. The transmitter and receiver can operate independently (with different clocks) to provide full-duplex communication. State Time (or State) The basic time unit of the device; the combined period of the two internal timing signals, PH1 and PH2. With a 50 MHz external clock, one state time equals 80 ns. Because the device can operate at many frequencies, this manual defines time requirements in terms of state times rather than in specific units of time. TAP Test access port.
Index
INDEX #, defined, 1-3 82C59A, 9-1 A Address bus, 6-1 Address lines new, 3-1 Address space configuration register, 4-6 expanded I/O, 4-3 enabling/disabling, 4-8 I/O decoding techniques, 4-6 I/O for PC/AT systems, 4-2 peripheral registers, 4-15 Addressing modes, 4-9–4-14 DOS-compatible mode, 4-9–4-10 enhanced DOS mode, 4-11, 4-13 nonDOS mode, 4-11, 4-14 nonintrusive DOS mode, 4-11, 4-12 AEN signal, deriving, B-2–B-3 AEOI mode, 9-9 aligned data transfers, 6-9 Applications, typical, 2-1 Architectural overview,
INTEL386™ EX MICROPROCESSOR USER’S MANUAL operation during idle mode, 8-5 overview, 6-1–6-3 pipelining, 6-8 ready logic, 6-10 See also Bus control arbitration signals, 6-3–6-4 Bus signals, departures from PC/AT architecture, B-2–B-3 Bus size control for chip-selects, 14-11 BYPASS, 18-2 C CAS#-before-RAS# refresh, 15-1, 15-12 Chip-select unit, 14-1–14-24 operation, 14-2–14-12 bus cycle length adjustments, 14-12 bus cycle length control, 14-11 bus size control, 14-11 defining a channel’s address block, 14-2
INDEX D Deassert, defined, 1-4 Decoding techniques, I/O address, 4-6 Design considerations clock and power management unit, 8-11 input/output ports, 16-10 interrupt control unit, 9-29–9-30 JTAG test-logic unit, 18-14 refresh control unit, 15-11 synchronous serial I/O unit, 13-25 Device configuration, 5-1–5-37 procedure, 5-28 register addresses, 4-19, D-5 worksheets, 5-34–5-37 DMA controller, 12-1–12-61 block diagram, 12-2 configuring, 5-3 departures from PC/AT architecture, B-1–B-3 DMACLR command, 12-50 DM
INTEL386™ EX MICROPROCESSOR USER’S MANUAL DOS compatibility departures from PC/AT architecture bus signals, B-2 CPU-only reset, B-4 DMA unit, B-1 HOLD, HLDA pins, B-4, B-5 interrupt control unit, B-4 SIO units, B-4 DRAM, refreshing, 15-12 DRAM, See Refresh control unit E EISA compatibility, 4-3–4-5 ESE bit programming, 4-8 Exceptions and interrupts, relative priority, 7-7 Execution Unit, 3-4, 3-5 Expanded address, defined, 1-4 Expanded I/O address space, 4-3 enabling/disabling, 4-8 F FaxBack service, 1-6
INDEX operation, 9-4–9-16 overview, 9-1 programming, 9-15–9-32 considerations, 9-32 ICW1, 9-20, D-28 ICW1 register, 9-20 ICW2, 9-21, D-29 ICW2 register, 9-21 ICW3, 9-22, 9-23, D-29, D-30 ICW3 register, 9-22, 9-23 ICW4, 9-24, D-30 ICW4 register, 9-24 IERn, 11-27, D-32 IIRn, 11-28, D-33 INTCFG, 5-10, 9-19, D-34 INTCFG register, 9-19 OCW1, 9-25, D-40 OCW1 register, 9-25 OCW2, 9-26, D-41 OCW2 register, 9-26 OCW3, 9-27, D-42 OCW3 register, 9-27 P3CFG register, 9-18 POLL, 9-28, D-49 POLL register, 9-28 register
INTEL386™ EX MICROPROCESSOR USER’S MANUAL register locations, 4-5, 4-15 Peripherals, summary, 2-3 Physical address space, 3-1 Pin configuration, 5-23 PINCFG, 5-24, 10-23, 11-17, 12-31, 13-17, 14-15, D-46 Pin descriptions, A-1–A-10 Pin states after reset and during idle, powerdown, and hold, A-9 Pipelined instructions, defined, 3-2 Port configuration P1CFG, 5-25, 11-18, D-43 P2CFG, 5-26, 11-19, 14-16, D-44 P3CFG, 5-27, 9-18, 10-22, 11-20, D-45 PnCFG, 16-7 PnDIR, 16-8, D-47 PnLTC, 16-8, D-48 PnPIN, 16-9, D-4
INDEX register addresses, 4-18, D-4 registers, 15-6 signals, 15-4 Register naming conventions, 1-4 organization, 4-1–4-20 Register bits, notational conventions, 1-4 Register names, notational conventions, 1-4 Register, status during SMM, 7-3 Registers BOUND, 18-2 BYPASS, 18-2 CLKPRS, 8-6, 8-7, 13-16, 13-19, D-7 Component and revision ID, 7-15 CSnADH, 14-14, 14-17, D-8 CSnADL, 14-14, 14-18, D-9 CSnMSKH, 14-14, 14-19, D-10 CSnMSKL, 14-14, 14-20, D-11 DLHn, 11-15, 11-22, D-12 DLLn, 11-15, 11-22, D-12 DMA0BYCn
INTEL386™ EX MICROPROCESSOR USER’S MANUAL SSIOTBUF, 13-16, 13-24, D-61 TBRn, 11-15, 11-23, D-61 TMRCFG, 5-13, 10-4, 10-21, D-62 TMRCON, 10-4, 10-25, 10-28, 10-30, D-63 TMRn, 10-4, 10-26, 10-29, 10-32, D-64, D-65 UCSADH, 14-14, 14-17, D-8 UCSADL, 14-14, 14-18, D-9 UCSMSKH, 14-14, 14-19, D-10 UCSMSKL, 14-14, 14-20, D-11 WDTCLR, 17-7 WDTCNTH, 17-7, 17-8, D-67 WDTCNTL, 17-7, 17-8, D-67 WDTRLDH, 17-7, 17-10, D-68 WDTRLDL, 17-7, 17-10, D-68 WDTSTATUS, 17-7, 17-9, D-69 reload event, 17-4 Reserved bits, defined, 1
INDEX operation, 13-5–13-15 baud-rate generator, 13-5–13-6 receiver, 13-12–13-15 transmitter, 13-6 overview, 13-1–13-4 programming, 13-16–13-25 CLKPRS register, 13-19 PINCFG, 13-17 SIOCFG register, 13-18 SSIOBAUD, 13-20, D-58 SSIOBAUD register, 13-20 SSIOCON1, 13-22, D-59 SSIOCON1 register, 13-21, 13-22, D-59 SSIOCON2 register, 13-23 SSIOCTR, 13-21, D-60 SSIOCTR register, 13-21 SSIORBUF, 13-25, D-60 SSIORBUF register, 13-25 SSIOTBUF, 13-24, D-61 SSIOTBUF register, 13-24 register addresses, 4-18, D-4 regist
INTEL386™ EX MICROPROCESSOR USER’S MANUAL mode 3, 10-12–10-15 basic operation, 10-13–10-14 basic operation (odd count), 10-14 disabling the count, 10-14 writing a new count, 10-15 mode 4, 10-16–10-17 basic operation, 10-16 disabling the count, 10-17 writing a new count, 10-17 mode 5, 10-18–10-19 basic operation, 10-18 retriggering the strobe, 10-19 writing a new count, 10-19 operation, 10-5–10-19 operations caused by GATEn, 10-6 overview, 10-1–10-4 programming considerations, 10-33 initializing the counter
INDEX registers, 17-7 WDTCLR, 17-7 WDTCNTH, 17-7 WDTCNTL, 17-7 WDTRLDH, 17-7 WDTRLDL, 17-7 WDTSTATUS, 17-7 reload event, 17-4 signals, 17-3 WDT, See Watchdog timer unit Worksheets peripheral configuration, 5-34 pin configuration, 5-34 World Wide Web, 1-7 Index-11
