Computer Hardware User Manual

40 Intel® 41110 Serial to Parallel PCI Bridge Design Guide
PCI-X Layout Guidelines
8.6.5 PCI 33 MHz Embedded Mode Topology
Figure 21 and Table 14 provide routing details for a topology with an embedded PCI 33 MHz
design.
Figure 21. PCI 33 MHz Embedded Mode Routing Topology
Table 14. PCI 33 MHz Embedded Routing Recommendations
Parameter Routing Guideline for Lower AD Bus
Reference Plane Route over an unbroken ground plane
Board Impedance 60 Ω +/- 15%
Stripline Trace Spacing 12 mils, edge to edge
Microstrip Trace Spacing 18 mils edge to edge
Group Spacing Spacing from other groups: 25 mils min, edge to edge
Breakout 5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils.
Trace Length 1 TL1: From
41110 signal Ball to first
junction
5.0” max
Trace Length TL2 to TL5 -
between junctions
0.5” min - 3.5” max
Trace Length TL_EM1 to
TL_EM10 from junction to
embedded devices
2.0” min - 3.0” max
Length Matching
Requirements
Clocks coming from the clock driver must be length matched to within 25 mils.
B2723 -01
EM1
EM2
TL1
TL_EM2 TL_EM1
EM3
EM4
TL2
TL_EM4 TL_EM3
EM5
EM6
TL3
TL_EM6 TL_EM5
EM7
EM8
TL4
TL_EM8 TL_EM7
EM9
EM10
TL5
TL_EM10 TL_EM9