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Intel® 460GX Chipset System

Software Developer’s Manual

June 2001

Document Number: 248704-001

Summary of content (294 pages)

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Intel® 460GX Chipset System Software Developer’s Manual June 2001 Document Number: 248704-001
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THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Contents 1 Introduction......................................................................................................................1-1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 System Overview ...............................................................................................1-1 1.1.1 Component Overview............................................................................1-2 Product Features..........................................................................................
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3 System Architecture ........................................................................................................3-1 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4 System Address Map ......................................................................................................4-1 4.1 4.2 4.3 4.4 5 5.2 5.3 5.4 5.5 Organization.......................................................................................................5-1 5.1.1 DIMM Types ............................................
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6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 6.1.6 Private Bus between SAC and SDC .....................................................6-2 Memory ECC Routing ........................................................................................6-3 Data Poisoning ...................................................................................................6-3 Usage of First-error and Next-error ....................................................................6-3 6.4.1 Masked Bits.......
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7.2 7.3 7.4 7.5 8 WXB Hot-Plug .................................................................................................................8-1 8.1 8.2 vi AGP Traffic.........................................................................................................7-6 7.2.1 Addresses Used by the Graphics Card .................................................7-6 7.2.2 Traffic Priority ........................................................................................7-7 7.2.
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8.2.14 Extended Hot-Plug Miscellaneous ......................................................8-18 9 IFB Register Mapping......................................................................................................9-1 9.1 9.2 9.3 9.4 10 IFB Usage Considerations ............................................................................................10-1 10.1 10.2 10.3 10.4 10.5 10.6 11 PCI / LPC / FWH Configuration..........................................................................
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11.2 12 IDE Configuration..........................................................................................................12-1 12.1 12.2 12.3 13 PCI Configuration Registers (Function 1) ........................................................12-1 IDE Controller Register Descriptions (PCI Function 1) ....................................12-1 12.2.1 VID–Vendor Identification Register (Function 1) .................................12-2 12.2.2 DID–Device Identification Register (Function 1) ........
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13.3 14 13.2.4 PCISTS–PCI Device Status Register (Function 2)..............................13-3 13.2.5 RID–Revision Identification Register (Function 2)...............................13-3 13.2.6 CLASSC–Class Code Register (Function 2) .......................................13-4 13.2.7 MLT–Master Latency Timer Register (Function 2) ..............................13-4 13.2.8 HEDT–Header Type Register (Function 2) .........................................13-4 13.2.
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15 PCI/LPC Bridge Description..........................................................................................15-1 15.1 15.2 15.3 15.4 15.5 16 PCI Interface ....................................................................................................15-1 15.1.1 Transaction Termination .....................................................................15-1 15.1.2 Parity Support .....................................................................................15-1 15.1.
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7-4 7-5 GART Entry Format for 4 MB Pages..................................................................7-3 GART SRAM Timings ........................................................................................7-5 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 4-1 5-1 5-2 5-3 5-4 6-1 6-2 Intel® 460GX Chipset Components ...................................................................1-2 Device Mapping on Bus CBN.............................................................................
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10-10 10-11 10-12 10-13 10-14 12-1 12-2 12-3 12-4 13-1 13-2 15-1 15-2 16-1 16-2 16-3 16-4 xii Ultra DMA Timing Value Based on Drive Mode .............................................10-11 Ultra DMA/Multi Word DMA/Single Word Transfer/Mode Values ..................10-12 PIO Transfer/Mode Values.............................................................................10-12 Drive Capabilities Checklist............................................................................
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1 Introduction This document provides information about the Intel® 460GX chipset components. The 460GX chipset is a high performance memory and I/O chipset for the Intel Itanium™ processor, targeted for multiprocessor server and high-end workstation designs. This document describes the software programmer's interface to the 460GX chipset.
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Introduction 1.1.1 Component Overview Table 1-1 lists the 460GX chipset components. Table 1-1.
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Introduction 1.2 Product Features • High performance hardware based on IA-64 architecture — 4.
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Introduction 1.4 DRAM Interface Support • • • • • • • • • • • • • 1.5 SDRAM 3.3 volt, 168-pin DIMM’s are the only memory type supported. Support for 64 MB to 64 GB of DRAM. Minimum memory size is 64 MB using 16 MB DIMM’s. Minimum incremental size is 64 MB using 16 MB DIMM’s. Maximum memory size is 16 GB using 128 MB DIMM’s. Maximum memory size is 64 GB using 1 GB DIMM’s. Only 3.3 volt memory is supported. Support for Auto Detection of SDRAM Memory Type. Supports 16, 64, 128 and 256 Mbit DRAM devices.
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Introduction • Parity protection on all PCI signals. • Data collection & write assembly. — Combines back-to-back sequential processor-to-PCI memory writes to PCI burst writes. — Processor to PCI write assembly of full/partial line writes. • Two outbound read requests containing a total of two cache lines of read data for each PCI bus. • Supports six outbound write requests containing a total of three cache lines of write data for each 32 bit PCI bus.
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Introduction • I2C Slave Interface will allow viewing and modifying of specific error and configuration registers. 1.7 Other Platform Components These 460GX devices provide access to flash space, interrupt collection and legacy features. 1.7.1 I/O & Firmware Bridge (IFB) The 460GX chipset is designed to work with the IFB south bridge. As part of this support, the PXB includes an internal PCI arbiter as well as support for an external PCI arbiter.
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Introduction • JTAG IEEE 1149.1 Specification (http://www.ieee.com) • Universal Serial Bus Specification (http://www.usb.org) • System Management Bus Specification, Rev. 1.0 • Low Pin Count (LPC) Interface Specification, Rev 1.0 Note: 1.9 Contact your Intel representative for the latest revision of the documents without document numbers. Revision History Date June 2001 Description Initial release.
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Introduction 1-8 Intel® 460GX Chipset Software Developer’s Manual
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Register Descriptions 2 The 460GX chipset has both memory mapped and PCI configuration space mapped registers. The 460GX chipset supports access mechanism #1 as defined in the PCI specification. Two 32-bit register locations (CONFIG_ADDRESS and CONFIG_DATA) are defined in the Itanium processor’s I/O space; I/O accesses to these registers are translated by the 460GX chipset into appropriate PCI configuration cycles.
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Register Descriptions to a PCI bus. Reads result in data being returned by the xXB through the SAC to the system bus. • Otherwise, the access is forwarded to the xXB to be placed on the PCI bus (or AGP bus) as a Configuration Read or Configuration Write cycle. Reads will result in data being returned through the xXB and SAC back to the system bus, just as in normal Outbound Read operations. 2.
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Register Descriptions translates CF8/CFC accesses to the MAC registers into read/write commands over the I2C port. The SAC also contains an IIADR pointer register that can be used in conjunction with a CF8/CFC access to generate I2C commands to generic I2C devices on the memory boards. 2.2.2 Register Attributes Registers have designated “access attributes”, with the following definitions: 2.2.3 Read Only Writes to this register have no effect.
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Register Descriptions 2.2.6 Consistency There are a number of registers that are repeated in both the SAC and xXB/PCI spaces. It is software’s responsibility to insure that these registers are programmed in a consistent fashion. Failure to insure consistency can produce indeterminate results. See the Initialization Chapter for an overview on initializing all chipset components.
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Register Descriptions subordinate bus number is in that range. For a type 1 cycle, the Bus Number is mapped to AD[23:16] during the address phase. 2.3.2 15:11 Device Number. This field selects one agent on the PCI bus selected by the Bus Number. Device 16 (10h) on Bus #0 is always reserved for programming the CBN. On the bus that the chipset is mapped into (determined by the CBN register), Device Numbers 0-31 are reserved for the 460GX chipset components as shown in Table 2-1.
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Register Descriptions Bits Description 7 Disable This bit can be written by software. When set, the ITID is retired immediately and not captured. Therefore there can be no checking of the address. See Section 6 for the usage of this bit. 6 Valid If set then the ITID in bits 5:0 is valid and shows the address of a single-bit memory error. Writing a 1 to this bit will clear the ITID and reset the valid bit. 5:0 ITID The ITID of the SEC error. These bits are read-only. 2.4.1.
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Register Descriptions Bits Description 7 Disable This bit can be written by software. When set, the ITID is retired immediately and not captured. Therefore there can be no checking of the address. See Section 6 for the usage of this bit. 6 Valid If set then the ITID in bits 5:0 is valid and shows the address of a system bus data error. Writing a 1 to this bit will clear the ITID and reset the valid bit. 5:0 ITID The ITID of the system bus error. These bits are read-only. 2.4.1.
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Register Descriptions 2.4.1.5 18 ‘Completion’ Command Underflow; MAC B, Stack R (CCBR) One of these 4 bits is set when the SAC receives a completion from the MAC and the SAC has no outstanding transaction. 17 BERR# Observed (BER) BERR# seen on the system bus. Set whenever BERR# is observed active. 16 IOQ Underflow/Overflow (IUE) Set when the IOQ is empty and the SDC sends out a signal saying it popped something from the top of the queue.
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Register Descriptions 2.4.1.6 SA_FERR: System Address on First Error Bus CBN, Device Number: Address Offset: Default Value: Sticky: 00h 60h undefined after Yes Function: Size: Attribute: Locked: 1 128 bits Read Only No This register records and latches the address for the first system bus error detected. 2.4.1.7 Bits Description 127:107 Reserved (0) 106 LOCK, ’b’ phase. 105 ADS, ’b’ phase. 104 RP#, ’b’ phase. 103:99 REQ, ’b’ phase. 98 AP1; ’b’ phase. 97 AP0; ’b’ phase.
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Register Descriptions 2.4.1.8 BIUDATA: BIU Data Register Bus CBN, Device Number: Address Offset: Default Value: Sticky: 00h 90h undefined No Function: Size: Attribute: Locked: 1 128 bits Read Only No This is the contents of the CAM concatenated with the contents of the RAM associated with the ITID in BIUITID. Note: 2-10 Bits Description 127:116 reserved(0) 115:82 Address bits [35:2].
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Register Descriptions 2.4.2 SDC 2.4.2.1 SEC0_D_FERR: Data on First Memory Card B SEC Bus CBN, Device Number: Address Offset: Default Value: 04h 40-47h 0 Size: Attribute: 64 bits Read Only, New Value Latched anytime appropriate FERR register bit is set This register records and latches the data corresponding to the first SEC detected by memory interface 0 in the SDC. 2.4.2.2 Bits Description 63:0 DE - System Data of Error.
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Register Descriptions 2.4.2.4 DED0_D_FERR: Data on First Memory Card B DED Bus CBN, Device Number: Address Offset: Default Value: 04h 50-57h 0 Size: Attribute: 64 bits Read Only, New Value Latched anytime appropriate FERR register bit is set This register records and latches the data corresponding to the first DED detected by memory interface 0 in the SDC. 2.4.2.5 Bits Description 63:0 DE - System Data of Error.
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Register Descriptions This register records and latches the data corresponding to the first SEC detected by memory interface 1 in the SDC. 2.4.2.8 Bits Description 63:0 DE - System Data of Error.
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Register Descriptions 2.4.2.11 DED1_ECC_FERR: ECC on First Memory Card A DED Bus CBN, Device Number: Address Offset: Default Value: 04h 78h 00h Size: Attribute: 8 bits Read Only, New Value Latched anytime appropriate FERR register bit is set This register records and latches the ECC checkbits corresponding to the first DED detected by memory interface 0 in the SDC. 2.4.2.12 Bits Description 7:0 ECC - ECC of Error.
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Register Descriptions 26 ’Forward’ Overlapping ’Forward’; Card A (FWMDI1) Indicates FWMDI sampled asserted while a store transaction is in progress 25 ’Load’ Overlapping ’Load’; Card A (LRMDI1) Indicates LRMDI sampled asserted while a store transaction is in progress 24 ’Load’ Overlapping ’Forward’; Card A (WrRd1) Memory interface 1 detected simultaneous read and write operation. Write and Read collision.
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Register Descriptions 2.4.2.14 5 System Bus Double Bit Error (DEDF) ECC Double Bit Error Detected on system bus. 4 System Bus Single Bit Error (SECF) ECC Single Bit Error Detected on system bus. 3 SDC Card A Double Bit Error (DED1) ECC Double Bit Error Detected from Memory Card A. 2 SDC Card A Single Bit Error (SEC1) ECC Single Bit Error Detected from Memory Card A. 1 SDC Card B Double Bit Error (DED0) ECC Double Bit Error Detected from Memory Card B.
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Register Descriptions This register records and latches the data associated with the first parity error detected on the PITID bus. 2.4.2.17 Bits Description 7 If set then the error was detected on the 1st half of the double-pumped transfer. Otherwise, these fields contain the information from the 2nd half of the double-pumped transfer. 6 Parity of Error 5:0 PITID - Private ITID bus value of Error.
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Register Descriptions while masked will return an invalid ECC code. To disable testing, the mask value is left at 0h (the default). The mask is a bit-wise XOR with the computed ECC. 2.4.2.20 Bits Description 7:0 ECC Generation Mask - For 64 bits of data. ECCMSK1: ECC Mask Register - Card A Bus CBN, Device Number: Address Offset: Default Value: 04h C9h 00h Size: Attribute: 8 bits Read/Write This register is used to test the ECC error detection logic in the memory subsystem for memory card 1.
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Register Descriptions 2.4.2.23 5 Memory Bus A ECC correction/detection enable. 4 Memory Bus B ECC correction/detection enable. 3:0 Double byte parity mask for 128 bits of data. PVD_D_FERR: Data on First PVD Parity Error Bus CBN, Device Number: Address Offset: Default Value: 04h D0-D7h 0 Size: Attribute: 64 bits Read Only, New Value Latched anytime appropriate FERR register bit is set This register records and latches the data associated with the first parity error detected on the PVD bus. 2.4.
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Register Descriptions 2.4.2.26 SECF_D_FERR: Data on First System Bus SEC Bus CBN, Device Number: Address Offset: Default Value: 04h E0-E7h 0 Size: Attribute: 64 bits Read Only, New Value Latched anytime appropriate FERR register bit is set This register records and latches the data corresponding to the first SEC detected by system bus interface in the SDC. 2.4.2.27 Bits Description 63:0 DE - System Data of Error.
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Register Descriptions This register records and latches the data corresponding to the first DED detected by system bus interface in the SDC. 2.4.2.30 Bits Description 63:0 DE - System Data of Error.
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Register Descriptions 0 2.4.3.2 Parity Error - CMND Parity Error Detected on SAC-MAC CMND Bus. Look in CMND_FERR Register to isolate. When the error is detected, the MAC will complete those operations which have a RAS pending, and stop. No new RAS cycles will be issued after the parity error and that card is effectively dead.
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Register Descriptions 2.4.4.2 3 Inbound Delayed Read Time-out Flag Each inbound read request that is accepted and serviced as a delayed read (i.e. the PXB retries the request) will initiate a watchdog timer (215 cycles, per the PCI spec). If the data has been returned and the timer expires before the requesting master initiates its repeat request, this flag will be set. This flag may be configured to assert SERR# or PERR# in the ERRCMD register.
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Register Descriptions 2.4.5 GXB 2.4.5.1 FERR_GXB Function Number: Address Offset: Default Value: Sticky: BFN+1 80h 00h Yes Size: Attribute: Locked: 8 bits Read/Write Clear No These registers record the first error detected by the GXB. For the order to clear this register with respect to the other GXB error registers. 2.4.5.
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Register Descriptions Default Value: Sticky: 00h Yes Attribute: Locked: Read/Write Clear No These registers record and latch the first error detected in the AGP interface. 2.4.5.4 Bits Description 7:6 reserved (0) 5 Lo-priority Read Data Que Parity Error This is data returned to the graphics card out of the Low-priority buffer. 4 Hi-priority Read Data Que Parity Error This is data returned to the graphics card out of the Hi-priority buffer.
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Register Descriptions 2.4.5.6 NERR_GART Function Number: Address Offset: Default Value: Sticky: BFN+1 8Eh 00h each Yes Size: Attribute: Locked: 8 bits Read/Write Clear No This register records all error conditions detected in the GART logic after the first error. Errors recorded in FERR_GART are not recorded here. 2.4.5.7 Bits Description 7:0 See FERR_GART for definitions of these bits.
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Register Descriptions 2.4.6 WXB 2.4.6.1 ERRSTS: Error Status Register Address Offset: Default Value: Sticky 44h 00h Size: Attribute: 8 bits Read/Write Clear, This register records certain error conditions detected from the PCI bus. This register is sticky through reset; that is, the contents of the register remain unchanged during and following the assertion of XRST#. This allows system recovery software invoked following a forced reset to examine the flags to determine the cause of an error.
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Register Descriptions 2.4.6.2 ERRCMD: Error Command Register Address Offset: Default Value: 45h– 46h 8040h Size: Attribute: 16 bits Read/Write This register provides extended control over the signalling of errors through SERR_OUT#, XBINIT#, and INTRQ#. These controls are in addition to the defined controls specified in the PCIstandard PCICMD register for SERR# assertion. Bits Description 15 XBINITO: XBinit Override Enable This bit should always be initially set to 0 by software.
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Register Descriptions each of these errors varies and is (generally) controlled through a combination of the PCICMD and ERRCMD registers. Refer to Section 6.12 for information on the conditional reporting of these errors via the SERR#, XBINIT#, or INTRQ# outputs. Note, if multiple errors are observed very close in time multiple errors may be signaled as a first error. 2.4.6.
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Register Descriptions 2.4.6.5 FEPCIAL: PCI First Error Address/Command Log Address Offset: Default Value: Sticky A5h–ADh 000000000000000000h Size: Attribute: 72 bits Read/Write Clear, These registers record and latch the address/command information, sent or received, associated with a PCI Bus error for the first error detected. 2.4.6.
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Register Descriptions The IT_MON_PMD_[0 to 5] registers hold the performance monitoring count values. 39-bits of the counter are used for event counting, the 40th-bit is used as a overflow detection bit. The 39-bit count value allows up to 70 minutes of event collection at 133 MHz. Event selection is controlled by the PMC registers (Section 2.5.1.2). Each counter may be stopped/started independently, using the controls available in the associated PMC register. 2.5.1.
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Register Descriptions Note: 23:15 UMASK Encodings 0 0000 0000 - Processor 0 - Monitor transactions originating from Processor 0 0 0000 0010 - Processor 1 - Monitor transactions originating from Processor 1 0 0000 0100 - Processor 2 - Monitor transactions originating from Processor 2 0 0000 0110 - Processor 3 - Monitor transactions originating from Processor 3 0 1000 0000 - All Processors - Monitor transactions originating from all Processors 0 0001 1010 - Configuration Space - Monitor transactions origin
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Register Descriptions 001 0111b Memory Read that was to be retried and received a HITM 001 1000b Memory Read with active OWN# and received a HITM 001 1001b Memory Read from a CPU that received a HITW 001 1010b Memory Read from a CPU that received a HITM 001 1011b Memory Read from PCI that received a HITW 001 1100b Memory Read from PCI that received a HITM 001 1101b Memory Write from PCI that received a HITM 010 0001b EV0 Events 010 0010b EV0 Clocks 010 0011b EV1 Events 010 0100b EV1 Clocks 7 reserved(0).
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Register Descriptions 2.5.2 SDC 2.5.2.1 FSB_D_PMC_[1,0]: System Bus Performance Monitor Configuration Register Bus CBN, Device Number: 04h Address Offset: 98-9Ah, 9C-9Eh Default Value: 000000h each Size: Attribute: 24 bits each Read/Write The FSB_D_PMC_[1,0] Registers specify the configuration of the SDC system bus performance monitors. This includes specifying Event Selection, Unit Mask, Enable & Divisible Source & Reload Control. Bits Description 23:17 reserved(0). 16:15 Mask.
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Register Descriptions 01b Disable when counter overflows. 10b Disable on falling edge (Deassertion) of SDC Event 0. 11b Disable on falling edge (Deassertion) of SDC Event 1. 4:3 Enable Source. Selects event that will enable the performance monitor. 00b Never Enable (in this mode the counter will never count). 01b Enable Always (note that if this setting is used, the disable events in bits [6:5] will only disable counting for one clock, and then the counter resumes.
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Register Descriptions 2.5.3 PXB 2.5.3.1 PMD[1:0]: Performance Monitoring Data Register Address Offset: Default Value: D8-DBh, E0-E3h 0000_0000h each Size: Attribute: 32 bits each Read/Write Two performance monitoring counters, with associated event selection and control registers, are provided for each PCI bus in the PXB. Each counter may be configured to track PCI bus events.
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Register Descriptions Once configured to count, all counters in the SAC and each PXB can be (nearly) simultaneously started and stopped using a separate enable. 1:0 2.5.3.3 Reload Mode Reload has priority over increment. That is, if a Reload event and a count event happen simultaneously, the count event has no effect. 0 Never Reload 1 Reload when this counter overflows. 2 Reload when the other counter overflows. 3 Reload unless the other counter increments.
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Register Descriptions 5:0 Event Selection This field specifies the basic PCI bus transaction or PCI bus signal to be monitored.
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Register Descriptions 38:0 2.5.4.2 Count Value This register contains the Performance Monitor Data Register. You may preset the value of the performance counter by writing to this register. You may read back the value of the performance counter by reading this register.
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Register Descriptions 0 2.5.4.4 Event 0 Input This bit is fed an input into Event 0 logic. This bit is OR’ed with any other logic generating Event 0, guaranteeing that if this bit is set, then Event 0 will be asserted. AGP_PMC_[0,1]: AGP Performance Monitor Configuration Register Function Number: Address Offset: Default Value: Sticky: BFN+1 ECh, F0h 000000h No Size: Attribute: Locked: 32 bits Read/Write No The AGP_G_PMC Register specifies the configuration of the GXB AGP Performance Monitor.
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Register Descriptions 7 EVENT1 Count Enable If set, then this bit over-rides bits 13:8. If set, then AGP_PMD_0 will count the number of occurrences of EVENT1 and AGP_PMD_1 will count the number of clocks that EVENT1 is active. When this bit is not set, then the 2 counters are controlled by bits 13:8. 6:5 Disable Source Selects event that will disable the performance monitor. 00b Never Disable. 01b Disable when counter overflows. 10b Disable on falling edge of GXB Event 0.
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Register Descriptions 00 0010b All PCI Clocks 00 0100b Idle Bus Cycles 00 0111b All Disconnect Events 00 1000b Lock Asserted Clocks 00 1001b Lock Asserted Events 00 1011b I/O Reads - Events 00 1101b I/O Writes - Events 00 1111b Memory Read Events 01 0001b Memory Write Events 01 0011b SRAM Read Events 01 0101b SRAM Write Events 01 0111b Write Combining Events 01 1000b WBF# Active - Clocks 01 1001b WBF# Active - Events 01 1011b Retry Read that’s not Delayed - Events 01 1101b Retry Write because no Write Slot
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Register Descriptions 2.5.5 WXB 2.5.5.1 PCI_WXB_PMC0: PCI Performance Monitor Configuration Register Address Offset: Default Value: DCh – DFh 00000000h Size: Attribute: 32bits Read/Write This register controls the PCI performance monitors. There are two performance monitors for each PCI bus. This register defines the events to be monitored, and when monitoring should start and stop. The selected event can be qualified by data transferred, and issuing agent.
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Register Descriptions 2.5.5.2 PCI_WXB_PMC1: PCI Performance Monitor Configuration Register Address Offset: Default Value: E8h – EBh 00000000h Size: Attribute: 32bits Read/Write This register controls the PCI performance monitors. There are two performance monitors for each PCI bus. This register defines the events to be monitored and when monitoring starts and stops. The selected event can be qualified by data transferred, and issuing agent. Bits Description 31:0 See PCI_WXB_PMC0 definitions. 2.
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Register Descriptions 2.6.2 15:8 XTPR 1 These bits represent the external task priority for symmetric agent ID 01h. 7:0 XTPR 0 These bits represent the external task priority for symmetric agent ID 00h. PID PCI Memory-mapped Registers The PID uses two 32-bit memory-mapped registers to provide the indirect addressing access to its (x)APIC interrupt redirection registers as well as to its ID, version, and arbitration ID registers.
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Register Descriptions 2.6.2.2 I/O Window Register (FEC00010h) This register is mapped onto the PID’s internal register that is selected by the I/O register select register. Readability/writeability by software is determined by the characteristics of the internal register that is currently selected. The format of the I/O window register is shown in Table 2-4 below. This register must be accessed using 32-bit read or write operations. Table 2-4.
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Register Descriptions 2.6.3.1 I/O (x)APIC ID Register (00h) Table 2-6.
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Register Descriptions Table 2-6.
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Register Descriptions Table 2-7. I/O APIC ID Register Format Register Offset: 00h Bit(s) Name Description 31:28 Reserved These four bits are reserved. 27:24 ID[3:0] These four bits provide the APIC ID. This field is used by the I/O APIC unit of the PID. In SAPIC or compatibility mode of operation, these bits are ignored. 23:16 Reserved These 24 bits are reserved. 15 DT This bit defines the delivery type. A ‘0’ in this field indicates APIC delivery mechanism.
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Register Descriptions Table 2-9. I/O (x)APIC Arbitration ID Register Format Register Offset: 02h Bit(s) 2.6.3.4 Default Value: [00000000h]Attribute: Read-Only Name Description 31:28 Reserved These four bits are reserved. 27:24 ARBID APIC Arbitration ID. 23:0 Reserved These 24 bits are reserved. I/O (x)APIC RTE (10h-8Fh) The interrupt RT has a dedicated entry for each interrupt input pin. Software can individually choose the interrupt vector number for input pins.
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Register Descriptions Table 2-10. I/O (x)APIC RTE Format (Cont’d) Register Offset: 10-8Fh Bit(s) 16 SAPIC Mode Name MASK Default Value: Undefined except mask bit is 1Attribute: Read/Write APIC Mode Name MASK Description This bit masks the (x)APIC delivery of this interrupt. A 0 indicates that delivery of this interrupt is not masked. An edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination.
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Register Descriptions Table 2-10. I/O (x)APIC RTE Format (Cont’d) Register Offset: 10-8Fh Bit(s) 11 Default Value: Undefined except mask bit is 1Attribute: Read/Write SAPIC Mode Name APIC Mode Name DESTINATION MODE DESTINATION MODE Description This bit determines the interpretation of the destination field. A 0 indicates physical mode. In physical APIC mode, a destination APIC is identified by its ID. Bits 56 through 59 of the destination field specify the 4-bit APIC ID.
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System Architecture 3 This chapter provides an explanation of the 460GX chipset’s handling of various aspects of the system architecture. It covers coherency, ordering, interrupts and related issues. 3.1 Coherency For any computer system, data coherency between processor caches and other elements within the system is one of the main concerns of the system designer. In a Symmetric Multiprocessor (SMP) system, hardware is usually required to maintain this coherency.
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System Architecture For WC memory, one processor may write to an address that is marked WC in its page table and hold the write in its own data buffer, while waiting to write to the bus. If a different processor were to read this address, the first processor does not snoop the WC holding registers and therefore would not provide the newly written data. So the 2nd processor would get the data from memory which is stale or un-updated with respect to the first processor.
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System Architecture New EM code may be weakly ordered. To allow the processor to take advantage of this, the 460GX chipset defers all reads and returns the data out-of-order to the processor. By returning data in an out-of-order fashion, the DRAM’s may be accessed in an optimal manner. Accesses are sent out of the memory queue to free banks of SDRAM’s.
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System Architecture Arbitration for Outbound Transactions The WXB relies heavily on the PCIset core and the PCI Specification regarding transaction ordering for dealing with starvation on outbound transactions. Once the WXB has won PCI arbitration for an outbound transaction, the WXB will initiate the request at the top of the Outbound Transaction Queue (OTQ) unless there is a read within the Outbound Read Request FIFO (ORRF).
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System Architecture AGP LOCKS There is no LOCK signal on the AGP bus. However, legacy code that issues read-modify-write (RMW) transactions could still be converted for use with an AGP device. The GXB will attempt to establish a “pseudo-lock” to cover such an event. However, there is still a deadlock case within the AGP controller that the GXB can not address. This case is covered in a “special design considerations” section of the AGP specification.
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System Architecture location, there is no guarantee that AGP has not written the location while the lock was active on the system bus. AGP may read or write those locations or any other memory location, independent of the processor lock. 3.7 Interrupt Delivery Interrupts may be delivered to the processors over the system bus. The interrupts may come from an I/O device or from another processor. The new system bus delivery method for interrupts to Itanium processor is referred to as SAPIC.
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System Architecture 3.8.1 Slot Power-up and Enable To power-up a PCI slot, software sets a command bit in a register. Then the hot-plug logic performs the following steps: 1. Set PWREN active to the slot and clock the parallel latch. 2. Set CLKEN# active to the slot but do not clock the parallel latch. 3. Wait 200 msec for slot power to stabilize, except in test mode. 4. Gain ownership of the PCI bus through arbitration. 5. Clock the parallel latch. 6. Release ownership of the bus after 480 nsec. 7.
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System Architecture 3-8 Intel® 460GX Chipset Software Developer’s Manual
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System Address Map 4.1 4 Memory Map The Itanium™ processor supports a 44 bit address space. The 460GX chipset supports only 36 bits of the address bus for a 64 GB of physical memory and must address up to several GB of memory mapped I/O space. The 460GX chipset attaches to A#[35:3].
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System Address Map Figure 4-1.
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System Address Map 4.1.2 Low Extended Memory Region The 15 MB Low Extended Memory region is always mapped to main memory. Since the 460GX chipset does not support ISA cards, there is no gap provided in this region. 4.1.3 Medium Extended Memory Region The Medium Extended Memory region is divided into two primary regions: A fixed gap containing the firmware area along with gaps for Itanium processor and chipset specific functions, and a variable gap to support memory mapped I/O.
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System Address Map — FEB0_0CC0: This address is used for BSP selection. It is a write once register in the SAC. Figure 4-1 shows how the SAPIC and GART spaces are allocated. There may be up to 255 I/O SAPICs in the system. There is one region defined for the GART space. 4.1.3.1 Variable GAP The variable gap starts at 4G-32M, and can grow downward in 32M increments. This gap is used to provide memory mapped I/O spaces to all of the logical PCI buses (this includes AGP buses) in the system.
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System Address Map Figure 4-2. Itanium™ Processor and Chipset-specific Memory Space FEFF_FFFF I/O reserved 1 MB Interrupt Delivery On system bus - 1MB I/O reserved 1 MB FEF0_0000 FEE0_0000 PCI Bus mapping of SAPIC addresses.
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System Address Map • I/O addresses used for VGA controllers: 03B0h-03BBh and 03C0h-03DFh. These addresses are specifically decoded so they can be mapped to the PCI bus specified by the VGA Space Register. An I/O access must be contained fully within the VGA I/O range to be remapped (e.g. an I/O read spanning 03BBh and 03BCh would not be remapped because it crosses the VGA I/O range).
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System Address Map 4.3 Devices View of the System Memory Map Figure 4-1 shows an Expander Bridge device’s view of system memory. The goal is to prevent invalid accesses at the expander bridge level, since different expander bridge devices are allowed to access different regions. For example, PXBs are allowed to access other logical PCI segments and GXBs are not. The SAC does not perform special checking to prevent this, and therefore the expander bridges must be set up by firmware accordingly.
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System Address Map 4.4 Legal and Illegal Address Disposition Below is the disposition of addresses done by the Bus Interface Unit (BIU). Table 4-1. Address Disposition Address Range Inbound Dest.
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System Address Map Table 4-1. Address Disposition (Cont’d) Address Range Outbound Inbound Dest. Decision FEF0_0000h to FEFF_FFFFh PCI0a unclaimed Reads are sent to PCI-0a for master abort. Writes get No-Data response and are dropped.
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System Address Map 4-10 Intel® 460GX Chipset Software Developer’s Manual
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Memory Subsystem 5 The Intel 460GX chipset’s memory subsystem consists of the SAC’s DRAM controller, the SDC’s buffering and datapath access, the MAC and MDC components, and the DRAMs themselves. Table 5-1 summarizes the 460GX chipset’s general memory characteristics. Table 5-1.
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Memory Subsystem Figure 5-1.
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Memory Subsystem Figure 5-2 for an illustration. In theory all 4 of these lines could be transferring data at the same time. It would then be muxed by the MDC to the SDC and then by the SDC to the bus. This allows data to be moved with no dead cycles on consecutive reads. Another possibility is that the data from cardA is going to the system bus, while the data from cardB is going to a PCI port.
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Memory Subsystem 5.2 Interleaving/Configurations Maximum system bandwidth is obtainable in several ways. If the address patterns are well-behaved then one can use the page mode of the DRAM itself to obtain high bandwidths. Generally page hits can sustain about 5 times the bandwidth of page misses with a one-bank memory system. In systems with only several memory banks, designs tend to try and optimize the page hit rate to increase bandwidth.
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Memory Subsystem 5.2.1 Summary of Configuration Rules The memory system may populate any row in any order. There are preferred ways of populating the memory subsystem for performance, but all configurations will work. The following rules summarize the way the memory system may be built up. The one hard rule is that a given row must be populated with 4 of the same DIMMs. There is no mixing allowed within a row.
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Memory Subsystem 5.4 Memory Subsystem Clocking The DIMMs are clocked at half the system bus frequency. For the Itanium processor, this means the DRAMs are clocked at 15 ns. Data is clocked out at the rate of 32B per 15 ns. The following table lists the DRAM parameters used for the 460GX chipset. Table 5-3. Required DRAM Parameters Parameter Symbol Clock cycle time at CL=2 Tck Access time from CLK Tac CAS Latency TCL RAS latency Min. (clocks) Max. (clocks) 15 ns. 6 ns.
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Memory Subsystem 5.5.3 Hardware Initialization In order to decrease boot time of systems with large amounts of DRAM installed, hardware initialization of memory will be supported. Since multiple rows will be initialized simultaneously, the memory system will be able to initialize to 0 about 8 times faster than having the processor looping through memory with writes. The MDC will force all zeroes on the data lines, with good ECC, and the MAC will cycle through the memory addresses generating writes.
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Memory Subsystem 5-8 Intel® 460GX Chipset Software Developer’s Manual
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Data Integrity and Error Handling 6.1 6 Integrity This chapter explains the various errors in the chipset. Error handling requires catching the error, containing it, notifying the system, and recovery or system restart. Different platforms have different requirements for error handling. A server is most interested in containment. It wants bad data to be stopped before it reaches the network or the disk. On the other hand workstations with graphics may be less interested in containment.
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Data Integrity and Error Handling 6.1.2 DRAM • The 460GX chipset provides ECC generation on all writes into the DRAM, and ECC checking on all reads from the DRAM. Single-bit errors are corrected. Multi-bit errors will return poisoned data. Both types of errors are logged, with the address and ECC bits for the data being recorded. The row which failed, as well as the bit for single-bit errors, can be identified by software. • The first instance of a single-bit error is logged.
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Data Integrity and Error Handling 6.2 Memory ECC Routing The ECC code used in DRAM is the same code as used in the Itanium processor, requiring 8 check bits to cover 64 bits of data. On the system bus, this code detects and corrects all single-bit errors, and detects double-bit errors.
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Data Integrity and Error Handling Note: In the SAC if there is a single-bit error and a double-bit error reported from the SDC on the same cycle, then only the double-bit error is reported and only the double-bit error has its ITID captured in the SAC. The SDC will have its SEC bit set and so software must read and clear all the errors in the SDC after clearing the SAC. A bit in FERR may be set that signals a minor error, such as correctable ECC error or other nonfatal error.
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Data Integrity and Error Handling 6.4.4 XBINIT# XBINIT# is an input to the SAC and an output from one of the xXB’s or can also be generated by platform logic. XBINIT# is GTL+ level, and therefore all the outputs from the xXB’s can be tied together and fed into the SAC’s input. XBINIT# is held by the xXB until the xXB is reset, so if it takes multiple clocks to drive from the xXB to the SAC, there should be no problem. 6.4.5 XSERR# XSERR# is an input to the SAC.
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Data Integrity and Error Handling 6.5.2 System Bus Errors There are several errors that are detected by the SAC. • System Bus Address Parity Error. Parity is checked on both address phases. — On A[43:24]#, detected by AP[1]#. — On A[23:3]#, detected by AP[0]#. • System Bus Request Parity Error. Parity on both phases of the request bus is checked. — On REQ[4:0]#, detected by RP#. • Address above TOM. Set for addresses above TOM and not in a PCI range.
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Data Integrity and Error Handling The SDC will capture the following errors on its side of the interface. • PDB Data Parity Error. On data received from the SAC, parity is checked. If parity is bad, the data is sent to memory or the system bus with poisoned ECC. • PDB Byte Enable Parity Error. On parity errors for the byte enables, the entire data transfer is sent to memory or the system bus with bad ECC. If the transfer is 64B then the entire line will have bad ECC. • PDB Command Parity Error.
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Data Integrity and Error Handling • ‘Load’ Overlapping ‘Forward’. Set when the SDC is doing a ‘Forward’ by sending data to the MDC and the MDC starts to send the SDC data before the ‘Forward’ is complete. • ‘Forward’ overlapping ‘Load’. Set when the SDC is receiving data from the MDC, and then is told to send data to the MDC at the same time it is receiving data. 6.5.6 SDC/System Bus Errors • LEN# Protocol Error.
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Data Integrity and Error Handling Other errors capture the address associated with the failure. This is also for debug and diagnostic purposes, but also has the potential for use in system recovery. For instance, if there is an uncorrectable error on a data read, and the access can be isolated, then instead of re-starting the whole system, it might be possible to kill only the failing process and allow other users to continue running. 6.6.
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Data Integrity and Error Handling After this the error reporting is in the clean state. After the ITID is found, the actual address is needed. Again this is somewhat indirect. There are 2 locations in the SAC in which the address may be found. One is the Bus Interface Unit’s (BIU) CAM and RAM, and the second is the MIU’s RAM. The BIU’s CAM contains the address for coherent transactions. The RAM contains the address, command and other information.
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Data Integrity and Error Handling • • • • DEDF - first double-bit ECC error on the system bus. PCMD - first parity error on the command bus. PITID - first parity error on the ITID bus. SDCRSP - first failing transmission on the response bus. The response bus does not have parity, instead it sends the response in clock x and the inversion of the response in clock x+1. All of these registers are independent. Having one of these valid doe not block any other from being valid.
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Data Integrity and Error Handling capable of any recovery. The first error, especially if it is fatal, may itself have caused downstream errors to be flagged. The error that is flagged as first should be considered as correct and an indication of some real problem. The problem may have been a transient condition or a true hardware failure.
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Data Integrity and Error Handling 6.8.2 SAC Multiple Errors There are several important cases of multiple errors in the SAC. Some of these are caused by the SAC and SDC not being in one chip and therefore having delays in the handshaking paths that will allow events that occur after a fatal problem to appear as errors, even when they are not real.
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Data Integrity and Error Handling Take the case where processor 1 reads a line from memory and there are no errors, and then does a write into its cache. Later processor 2 does a read, getting an IWB. The SAC starts a speculative read for the line before seeing the HITM#. If the data in DRAM has a 2x error on this read the SDC data buffer will be marked as having a 2x error on this line.
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Data Integrity and Error Handling Figure 6-2. SDC Error Data Flow From Processor Correct if 1x; if 2x, then write into DB with bad parity on chunk that is bad. Set status. No reporting. 1b/16b parity To SAC Check and flag status; regenerate new parity, if incoming is bad then generate new parity as bad. On data to SAC send with bad parity if parity if data is bad in buffer. Report error. 1b/8b parity 6.10 Error Conditions 6.10.
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Data Integrity and Error Handling Table 6-1. Error Cases Error System Bus 1x ECC Chip Detecting SDC System Action Correct the data and pass to bus. Status Register SDC Write into memory with bad ECC (poison data).
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Data Integrity and Error Handling Table 6-1.
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Data Integrity and Error Handling Table 6-1. Error Cases (Cont’d) Error ‘Accept’ Underflow Chip Detecting System Action Status Register Log Register Qualifier SDC Unconditional BINIT# SDC_FERR[AEx], FERR_SAC[SFE] Nothing SDC Unconditional Interrupt SDC_FERR[RPE], FERR_SAC[SNE] Nothing AGP Request Queue Overflow GXB Unconditional XBINIT# FERR_AGP Nothing Use of Pipe with Sideband Enabled GXB Unconditional XBINIT# FERR_AGP Nothing AGP Address [ ..
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Data Integrity and Error Handling Table 6-1. Error Cases (Cont’d) Error GART Parity Error Chip Detecting GXB System Action Continue, use address as read from GART, Unconditional XINTR#, Conditional XBINIT#.
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Data Integrity and Error Handling Table 6-1. Error Cases (Cont’d) Chip Detecting Error System Action Status Register Log Register Qualifier Detected as PCI Target PCI Par-err on Address from Card PXB PCI Par-err on Data for an IB Write PERR# Asserted by Card 6.11 Accept address as sent and process as if parity were good. Conditionally assert SERR#. PCISTS[PE], PCISTS [SSE], ERRSTS[2] Nothing PXB Set Status. Drive PERR#. Pass data with good parity to Expander.
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Data Integrity and Error Handling The default option is to return a “normal” response. If the aborted transaction was a read, the PXB will return all 1’s for the data. If the aborted transaction was a write, the PXB will discard the write data. SERR# is not asserted in either case. 6.11.2.2 Received Target Disconnect A PCI target may issue a disconnect to indicate it is unable to respond within the PCI latency guidelines. Disconnect is signalled when the target asserts both STOP# and DEVSEL#.
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Data Integrity and Error Handling • After the first data transfer if the transaction is using an unrecognized addressing mode (the PXB will only support linear incrementing as a target), • On reads, when no more data is available in the read buffers, and • On writes, when the write crosses a 4 KB boundary. These conditions are not treated as an error, and will not be logged or reported. 6.11.3.
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Data Integrity and Error Handling 6.11.4.1 GXB Error Signals The GXB has 2 error signals: XBINIT# and XINTR#. 6.11.4.1.1 GXB_XBINIT# XBINIT# is used to signal a fatal error. All header errors are fatal, since the GXB and SAC are out of sync with each other at that point. Data parity errors may be considered fatal in some systems. For graphics, the error may be in a texture or some field that is a transient screen blip. The OEM may configure the system to BINIT# on data parity errors or not.
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Data Integrity and Error Handling 6.11.4.2.2 GART Interface Errors • GART Parity Error - There is one parity bit covering each GART entry. When the GART is accessed, parity is checked. If an error occurs, then this bit is set. Parity errors are only reported when the access falls within the GART aperture range. This prevents errors being reported when the GART entry was not used. • GART Entry Invalid - Each GART entry has a valid bit associated with it.
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Data Integrity and Error Handling • PCI Outbound Write Que Data Parity Error - This error signifies that either a) data was received from the Expander bus with bad parity or b) the OB write Que was corrupted. As data is read from the queue and passed to the PCI bus, the parity is checked. • AGP Low-priority Read Data Que Parity Error - This error signifies that either a) data was received from the Expander bus with bad parity or b) the read Que was corrupted.
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Data Integrity and Error Handling 6.12 WXB Data Integrity and Error Handling 6.12.1 Integrity Error handling in the context of a chipset component requires observing the error, containing it, notifying the system, and recovery or system restart. Different platforms have different requirements for error handling. A server is generally most interested in containment. It attempts to stop bad data before it reaches the network or the disk.
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Data Integrity and Error Handling Note: Additionally, error responses such as SERR#, XBINIT# and INTRQ# are predicated on both First Error and Next Error contents since a second error may occur while the first error is in the process of being serviced by the WXB hardware. Thus, for example, the system may observe an interrupt associated with an error at almost the same instant XBINIT# is asserted for another.
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Data Integrity and Error Handling Table 6-4.
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Data Integrity and Error Handling 6.12.5.2 XBINIT# Generation A certain subset of errors within the WXB will always result in the WXB attempting to signal an XBINIT#. Whenever an error occurs that forces an XBINIT#, an internal “override” bit is set as XBINIT# is driven to the bus. While the override bit is set, XBINIT# will no longer be reasserted, even for qualifying errors. This prevents the presence of a single error from causing XBINIT# to be signaled multiple times.
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Data Integrity and Error Handling 6.12.8 Error Conditions 6.12.8.1 WXB as Bus Master 6.12.8.1.1 Master Abort If the WXB initiates a PCI transaction and no target responds, the WXB will terminate the transaction with a master-abort. The WXB will wait five PCI clocks after asserting FRAME# for a target to respond with DEVSEL#. If no target responds, the WXB will perform a master abort to terminate the cycle on the PCI bus.
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Data Integrity and Error Handling (DPE) bit is asserted. Regardless, if the transaction is a read, the PCISTS register’s Parity Error (PE) bit will be set. Additionally, address, command, and data related information is logged in the FEPCIAL and FEPCIL registers if the error is the first error observed by the WXB. 6.12.8.1.6 Other Violations The PCI specification identifies numerous cases that are violations of the PCI protocol.
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Data Integrity and Error Handling • MWI to a misaligned (non-cache-line-boundary) address • MWI to an aligned address, but with one or more byte enables not asserted Refer to the PCI specification for a complete description of the required PCI protocol. 6.12.8.3 PCI Interface Errors Other PCI interface errors that are handled by the WXB are: • System Error Signaled Set within the FEPCI register when the WXB sees an SERR# asserted by another PCI agent. This is not set when the WXB drives SERR#.
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AGP Subsystem 7 AGP is a new port defined for graphics adapters. In the initial implementation it is a 500 MB/s port. There is also an extension called AGP 4X mode, which has a bandwidth of 1 GB/s. AGP 2X mode cards will work in an AGP 4X mode slot. The 460GX chipset is designed to work at the AGP 4X mode bandwidths. It will support 3.3V AGP 1X and 2X mode cards as well. AGP 4X mode is a high-bandwidth port targeted to workstation graphics needs. It provides 1 GB of data bandwidth.
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AGP Subsystem Figure 7-1. GART Table Usage for 4k Pages 39 11 AGP address 0 Offset 12b AGP address (39:12) - APBASE(39:12) (If less than APBASE+Aperture) 24 Bit 24b 18b (16b if256 MB of GART space) + GART Entry GART Table 36b Main Memory Address Figure 7-2.
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AGP Subsystem 7.1.1 GART Implementation The GX implementation will support 256 MB, 1 GB, or 32 GB (32 GB requires 4 MB pages by the O.S.) of translation space. This limit is implementation-based not architectural. Each entry in the GART requires 24 bits for the address, 1 bit for coherency, 1 parity bit and 1 valid bit for a total of 27 bits. The width of each GART entry will be 32 bits. Each entry covers one 4kB (or 4 MB) page.
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AGP Subsystem 7.1.1.1 Page Sizes The Itanium processor supports both a 4kB and a 4 MB page size. The AGP programming model is designed using 4kB pages for GART entries. Using the larger page size would greatly reduce the number of misses and reduce the number of entries needed in the GART, thus lowering system cost. The GXB will support 4 MB pages. Using 4 MB pages, 256kB of SRAM could provide 256 GB of AGP space. The 460GX chipset will not support more than 32 GB of translatable graphics space. 7.1.1.
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AGP Subsystem 7.1.3 GART Implementation Figure 7-5 shows the timings for the SRAM interface. Synchronous SRAM will be clocked at 7.5 ns. The SRAM will be used in the pipelined mode. This allows addresses to be presented to the SRAM every cycle. The data is valid to be latched by the GXB on the 3rd clock edge after the clock edge which drove the address. Writes require the data to be driven with the address. The entire 32 bits of data are read or written at one time. Figure 7-5.
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AGP Subsystem For all AGP-type accesses which hit in the AGP range, there is a bit per GART entry which determines whether the address is coherent. For AGP-type accesses outside the AGP range, there is a bit in a configuration register of the GXB which determines the coherency. Coherency or noncoherency applies to accesses using AGP protocol only. Accesses using PCI protocol are always done coherently, whether they hit the translation table or not.
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AGP Subsystem The range may lie above the top of physical memory. Or the range may be placed in one of the gaps used to map addresses to PCI, and have that gap marked as reserved and not usable for addressing PCI devices. In the first case, the virtual range used by the graphics card may be above or below the 4 GB boundary. If it is above, then it can be placed anywhere in the 40 bit address range supported by the GXB.
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AGP Subsystem Note: Accesses from an AGP card that are directed to a PCI bus are a system fault and cause a BINIT# (system reboot). The 460GX chipset does NOT support any access originating from the AGP port to another PCI bus. This is true for PCI cycles (FRAME# active) as well as AGP cycles. PCI accesses are always disconnected at a line boundary for writes and a read will at most prefetch to the end of the line. Therefore each PCI request will have only one translation.
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AGP Subsystem this point the inbound Expander logic establishes a pseudo-lock and will no-longer send coherent requests from the AGP streams. Non-coherent requests can still be issued, but anything that can block the PCI stream in the SAC’s queues must be held in the GXB. 5. The outbound Locked Write request is transferred across the Expander bus. 6.
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AGP Subsystem Delayed transactions are issued and serviced as follows: 1. Upon receiving a read request, the address is compared against the GXB’s internal buffers. Unless the data corresponding to this request is already available in the buffers (i.e. from a previously retried request), the read cycle is immediately retried (the GXB retries the read cycle in three PCI clocks from FRAME# driven active). 2.
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AGP Subsystem Table 7-2. Delayed Read Matching Criteria Command Address Any Memory Read Match BEs Match When a DRC is valid in the GXB, a 215 PCI clock timer is started as described in the PCI 2.2 Specification. When the timer expires the DRC is discarded and the associated delayed read matching registers are cleared. This condition is optionally treated as an error. See the “Error” Chapter for details. 7.2.7.5 Inbound I/O Reads I/O reads on the PCI bus are not claimed by the GXB. 7.2.7.
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AGP Subsystem 7.2.7.8 Retry/Disconnect Conditions The GXB as a PCI target retries the initial data phase of inbound access when: • The read request is to an address that has already been accepted as a delayed transaction (i.e. the request is already being serviced, but data has not arrived). • A write request has insufficient buffering in the gxb to allow it to be posted. (a full line is not available for mwi). • The pci interface is locked from the host side. • No delayed read buffer is available.
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AGP Subsystem Table 7-3. Burst Write Combining Modes Write Command Used Memory Write Memory Write Memory Write Memory Write Invalidate Transfer Mode 1X 2X 4X All Data Length Combining Supported < 4 DW Can not be combined with the next access. >= 4 DW Can combine next access if it is sequential, regardless of next access size. < 8 DW Can not be combined with the next access. >= 8 DW Can combine next access if it is sequential, regardless of next access size.
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AGP Subsystem Table 7-5. Bandwidth Estimates for Various Request Sizes Request Size (in bytes) 7.3.1 Sustainable Bandwidth (MB/s) Latency (in ns.) for First Data Returned on AGP Bus 8 100-300 500 16 250-500 500 32 450-700 530 64 750-850 600 128 850-925 750 256 800-850 1000 Inbound Read Prefetching The PCI protocol has no transfer size explicitly spelled out. Reads begin and continue until the device has the data it needs.
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AGP Subsystem All regions, including the two described above, must be checked after GART translation. The GXB must only allow accesses that are directed to physical memory to reach the SAC.
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AGP Subsystem 7-16 Intel® 460GX Chipset Software Developer’s Manual
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WXB Hot-Plug 8.1 8 IHPC Configuration Registers Each WXB supports two independent Integrated Hot-Plug1 Controllers (IHPCs). The A-side controller (IHPA) and the B-side controller (IHPB) are configured independently. Each IHPC therefore has its own configuration space. Both configuration spaces are identical. Each IHPC reserves a 256 byte configuration space. A list of the configuration registers specific to hot-plug operation follows.
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WXB Hot-Plug Table 8-1.
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WXB Hot-Plug 8.1.1 Page Number List for the IHPC PCI Register Descriptions Register Page Arbiter SERR Status...................................................................................... 8-10 Base Address ................................................................................................... 8-7 CLASS: Class Register .................................................................................. 8-6 CLS: Cache Line Size .............................................................
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WXB Hot-Plug 8.1.4 PCICMD: PCI Command Register Address Offset: Default Value: 04h-05h 0000h Size: Attribute: 16 bits Partial Read/Write The PCI command register provides control over the IHPC’s ability to generate and respond to PCI cycles. When a zero (0) is written to this register, the IHPC is logically disconnected from the PCI bus for all accesses except configuration.
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WXB Hot-Plug 8.1.5 PCISTS: PCI Status Register Address Offset: Default Value: 06h – 07h 0200h Size: Attribute: 16 bits Partial Read/Write, Sticky The PCI status register is used to record status information for PCI bus-related events. The definition of each of the bits is given in the register bit list below. The specific implementation of each bit in the IHPC is also given. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set.
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WXB Hot-Plug 8.1.7 Bits Description 7:0 Revision Identification Number This is an 8-bit value that indicates the revision identification number for the IHPC WXB A Steppings: Hardwired Value = 00h WXB B0 Step: Hardwired Value = 01h CLASS: Class Register Address Offset: Default Value: 09 – 0Bh 080400h Size: Attribute: 24 bits Read-Only This register contains the Class Code for the IHPC, specifying the device function. Writes to this register will have no effect. 8.1.
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WXB Hot-Plug 8.1.11 Bits Description 7 Multi-function Device Selects whether this is a multi-function device, that may have alternative configuration layouts. The IHPC is not a multifunction device. Hardwired Value = 0. 6:0 Configuration Layout This field identifies the format of the 10h through 3Fh space. This field specifies the “standard” or “default” PCI configuration layout.
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WXB Hot-Plug This is a standard PCI configuration register which defines which interrupt request line on the interrupt controller this function’s interrupt pin (see register 3DH) is connected to. The power-up default value is FFh. 8.1.15 Interrupt Pin Address Offset: Default Value: 3Dh 01h Size: Attribute: 8 bits Read Only This is a standard PCI configuration register which defines which of the four PCI interrupt pins, INTA# through INTD#, this function is connected to.
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WXB Hot-Plug 8.1.18 11:8 reserved(0) 7 Enable PCI Configuration Space Access to Hot-Plug Registers. Enables IHPC memorymapped register access through the index register (configuration offset 50h) and data port (configuration offset 54h). 6:2 reserved (0) 1 reserved (1) 0 On / Off Busy (OOBS) status. Read Only. Same as bit 24 of the memory-mapped HotPlug Miscellaneous register.
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WXB Hot-Plug 8.1.21 Arbiter SERR Status Address Offset: Default Value: 8.1.
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WXB Hot-Plug Table 8-2.
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WXB Hot-Plug 8.2.1 Page Number List for IHPC Memory Mapped Register Descriptions Register Page Extended Hot-Plug Miscellaneous................................................................ 8-18 LED Control.................................................................................................. 8-13 General Purpose Output ................................................................................ 8-17 Hot-Plug Interrupt and Clear............................................................
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WXB Hot-Plug 8.2.3 Hot-Plug Miscellaneous Address Offset: Default Value: Bits 8.2.4 02h - 03h 0040h Size: Attribute: 16 bits Partial Read/Write Description 15 reserved (0) 14 Enable SERR on Power Fault. When set, the assertion of a slot power fault causes a SERR# to be asserted if SERR# generation is enabled in the PCI device command register, the slot is connected to the bus or PCI clock, and IHPC power fault functions are enabled (bit 10 of this register).
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WXB Hot-Plug for unpopulated slots and slots with open switches. The set of usable LED Control bits is determined by the strapping values on the P(A,B)HSIL, P(A,B)HSOL, and P(A,B)HSOC inputs. Unsupported slots in a system do not have writeable LED Control bits. LEDs are not affected by changes to these register bits until a SOGO is initiated following the changes. 8.2.
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WXB Hot-Plug into this register. Writing a logic 1 will clear the pending interrupt. If there are no other pending interrupts on the bit, the bit will clear. This register takes on a value based on the monitored status of the slots and therefore has no particular default value. 8.2.
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WXB Hot-Plug 8.2.
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WXB Hot-Plug 8.2.8 Serial Input Byte Pointer Address Offset: Default Value: 11h 00h Size: Attribute: 16 bits Read/Write, Read-Only Used to input a byte into the IHPC input registers. The byte number is written to the pointer. After the Serial Input Busy Status is read as a logic zero, the requested byte will be in the Serial Input Data Register.
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WXB Hot-Plug 8.2.12 Hot-Plug Switch Interrupt Redirect Enable Address Offset: Default Value: 2Ch 00h Size: Attribute: 8 bits Read/Write This register allows the slot switch change interrupts to be redirected to the SERR# instead of the INTA#. 8.2.
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9 IFB Register Mapping The IFB internal registers are organized into four Functions–LPC/FWH interface bridge, IDE Controller, USB Host Controller, and Enhanced Power Management. Each Function has its registers divided into 1 set of PCI Configuration Registers and one or more register sets located in system I/O space. Software should not map programmable memory or I/O address registers such that any part of the range overlaps addresses decoded by other IFB devices.
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IFB Register Mapping Table 9-1.
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IFB Register Mapping 9.2 IDE Configuration The IFB PCI function 1 contains an IDE Controller capable of standard Programmed I/O (PIO) transfers as well as Bus Master transfer capability. It also supports the “Ultra DMA/33” synchronous DMA mode of data transfer. 9.2.1 PCI Configuration Registers (Function 1) Table 9-2.
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IFB Register Mapping 9.3 Universal Serial Bus (USB) Configuration The IFB integrates an USB Controllers. The USB Controller is UHCI 1.1 compliant. It implements the root hub of the USB, which contains two ports. The IFB PCI function 2 reflects both the Universal Serial Bus Host and Root Hubs, with 2 connected USB ports. 9.3.1 PCI Configuration Registers (Function 2) Table 9-3.
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IFB Register Mapping 9.4 SMBus Controller Configuration The IFB PCI function 3 contains the SMBus Controller configuration space. 9.4.1 SMBus Configuration Registers (Function 3) Table 9-4.
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IFB Register Mapping 9-6 Intel® 460GX Chipset Software Developer’s Manual
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IFB Usage Considerations 10 This section talks about the normal usage for some of the features in the IFB component. 10.1 Usage of 1MIN Timer in Power Management IFB does not support the global standby timer concept. The determination of a system inactivity can be done by using the 1MIN Timer that can be used by the SMI handler to generate an SMI# every minute. The SMM handler can check all the appropriate power management status registers in IFB to see if there is any system inactivity.
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IFB Usage Considerations into the system firmware by the vendor. This reporting will make these register locations safe and the OS will not use these locations randomly if a PNP conflicting device is relocatable in those I/O or memory locations. These locations also got to be reported to the OS whenever the OEM sends the systems for their WHQL suite test. 10.5 Ultra DMA Configuration The following registers are programmed in systems that contain devices that implement the Ultra DMA Protocol.
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IFB Usage Considerations NOTES: • The Ultra DMA Enable bit specifies the current Ultra DMA enabled status: — Disabled by default: This field needs to be enabled in order to take advantage of the IFB Ultra DMA timings. When this field is disabled, the IFB Ultra DMA Timing Register is disabled. • The Ultra DMA Cycle Time Field specifies the current Ultra DMA timing mode. Note that this field only applies if the corresponding Ultra DMA Enable field is set. 10.5.
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IFB Usage Considerations Table 10-1.
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IFB Usage Considerations 10.5.4 Determining a Drive’s Best Ultra DMA Capability The drive’s ultra DMA mode capability and current configuration are specified in the IDENTIFY_DRIVE buffer, Word 88. Software must first check to see that the Word 88 is valid before determining the Ultra DMA drive capability. Table 10-2.
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IFB Usage Considerations The drive’s multi word DMA mode capability and current configuration are specified in the IDENTIFY_DRIVE buffer, Words 63 and 65 Software must first check to see that the Words 64-70 are valid before determining the drive’s multi word DMA drive capability. The drive’s single word DMA mode capability and current configuration are specified in the IDENTIFY_DRIVE buffer, Word 62. Table 10-3.
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IFB Usage Considerations Table 10-4.
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IFB Usage Considerations Software at this stage needs to determine if at least one of the above modes is supported by the drive. Software should initially determine a drive’s best PIO w/IORDY capability (PIO4 w/IORDY or PIO3 w/IORDY) initially. If these PIO w/IORDY modes are not supported, the drive should determine the PIO2 mode support with IORDY or PIO2 mode support without IORDY. Otherwise, Compatible timings should be applied to the drive.
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IFB Usage Considerations 10.5.6 IFB Timing Settings 10.5.6.1 DMA/PIO Timing Settings In Table 10-7, ‘x’=depends on the type of drive installed, ‘1’=enabled, and ‘0’=disabled. Ultra DMA mode settings are completely independent of the following timings. Table 10-7.
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IFB Usage Considerations Configurations where a drive reports a PIO speed much slower than its reported DMA speed require the DMA Timing Enable Only Select bit to be Enabled. Table 10-8.
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IFB Usage Considerations Table 10-9.
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IFB Usage Considerations Table 10-11.
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IFB Usage Considerations 10.5.7.1 BMIS1 - Bus Master IDE Status Register 1 (Primary: Bus Master IDE Base I/O Address + Offset 02h) 10.5.7.2 BMIS2 - Bus Master IDE Status Register 2 (Secondary: Bus Master IDE Base I/O Address + Offset 0Ah) 7 6 5 Reserved Drive 1 DMA Capable (DMACAP1) Drive 0 DMA Capable (DMACAP0) 0: Drive is PIO only. 0: Drive is PIO only. 1: Drive is capable and configured for DMA transfers. 1: Drive is capable and configured for DMA transfers.
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IFB Usage Considerations Table 10-14. IFB Settings Checklist Register Type Offset PCI Command Register PCI 04h PCI Master Latency Timer PCI 0Dh PCI Bus Master IDE Base I/O Address PCI 20-23h IDE Timing Register 1 PCI 40-41h IDE Timing Register 2 PCI 42-43h Secondary IDE Timing Register PCI 44h Ultra DMA Control Register PCI 48h Ultra DMA Timing Register PCI 4A-4Bh 10.5.
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IFB Usage Considerations 10.5.9.
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IFB Usage Considerations In the above configuration, none of the drives supports Ultra DMA. Only Non-ultra DMA and Fast PIO support will be enabled on each drive. Register Type Offset Value Comments PCI Command Register PCI 04h 0005h PCI Master Latency Timer PCI 0Dh System dependent PCI Bus Master IDE Base I/O Address PCI 20-23h System dependent Ensure that bit 0 (of register value) is ‘1’. IDE Timing Register 1 PCI 40-41h E377h Mode config.
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IFB Usage Considerations II. Provide recovery for data transfers that fail as the result of Ultra DMA/33 Interface CRC Errors: A. Determine that the data transfer command’s error source is Ultra DMA/33 Interface CRC error. B. Retry data transfer command when Ultra DMA/33 Interface CRC is the source of error. III. Ensure that the Ultra DMA/33 configuration of the devices and host controller is restored when events that clear the Ultra DMA/33 enabled status are encountered.
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IFB Usage Considerations This register enables/disables bus master capability for the IDE function and provides direction control for the IDE DMA transfers. This register also provides bits that software uses to indicate DMA capability of the IDE device. Bit Description 7:4 3 2:1 0 Reserved. Bus Master Read/Write Control (RWCON). 0=Reads; 1=Writes. This bit must NOT be changed when the bus master function is active. While a Ultra DMA transfer is in progress, this bit will be READ ONLY.
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IFB Usage Considerations Interrupt/Activity Status Combinations Bit 2 10.6 Bit 0 Description 0 1 DMA transfer is in progress. No interrupt has been generated by the IDE device. 1 0 The IDE device generated an interrupt and the Physical Region Descriptors exhausted. This is normal completion where the size of the physical memory regions is equal to the IDE device transfer size. 1 1 The IDE device generated an interrupt. The controller has not reached the end of the physical memory regions.
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IFB Usage Considerations 10-20 Intel® 460GX Chipset Software Developer’s Manual
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LPC/FWH Interface Configuration 11 The IFB PCI Function 0 contains a LPC/FWH interface, interrupt controller and counter / timers, including the real time clock. The register set associated with this Functionality and associated logic is shown below with actual register descriptions given in this section. 11.1 PCI to LPC/FWH Interface Configuration Space Registers (PCI Function 0) 11.1.
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LPC/FWH Interface Configuration 11.1.3 PCICMD–PCI Command Register (Function 0) Address Offset: Default Value: Attribute: 04–05h 0007h Read/Write This 16-bit register provides basic control over the IFB's ability to respond to PCI cycles. Bit 15:10 Reserved. 9 Fast Back-to-Back Enable (Not Implemented). This bit is hardwired to 0. 8 SERR# Enable (SERRE). 1=Enable. 0=Disable. When enabled (and DLC Register, bit 3=1), a delayed transaction time-out causes the IFB to assert the SERR# signal.
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LPC/FWH Interface Configuration Bit 8 PERR# Response (Not Implemented). Read as 0. 7 Fast Back to Back–RO. This bit indicates to the PCI Master that IFB as a target is capable of accepting fast back-to-back transactions. This bit is hardwired to 1. 6:0 11.1.5 Description Reserved. RID–Revision Identification Register (Function 0) Address Offset: Default Value: Attribute: 08h Stepping Dependent Read Only This 8 bit register contains device stepping information.
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LPC/FWH Interface Configuration 11.1.8 ACPI Base Address (Function 0) Address: Default Value: Attribute: 40-43h 00000001h Read/Write Bit 31:16 Reserved. 15:6 Base Address: Provides the 64 bytes of I/O space. 5:1 Reserved. 0 11.1.9 Description Resource Indicator: Tied to 1 to indicate I/O space ACPI Enable (Function 0) Address: Default Value Attribute: 44h 00 Read/Write Bit 7:1 0 11.1.10 Description Reserved.
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LPC/FWH Interface Configuration 11.1.11 BIOSEN–BIOS Enable Register (FUNCTION 0) Address Offset: Default Value: Attribute: 4E-4Fh 07C1h Read/Write This register is used to implement protections to writes to firmware (BIOS) ranges. Bit Description 15 BLE - BIOS Lock Enable: When the bit is a “1”, setting BIOS_WEN bit will cause SMIs. When this bit is a “0”, setting BIOS_WEN will not cause SMIs. Once set, this bit can only be cleared by a PCIRST#. 14:11 Reserved. 10:3 Reserved.
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LPC/FWH Interface Configuration 11.1.13 SerIRQC–Serial IRQ Control Register (Function 0) Address Offset: Default Value: Attribute: 64h 10h R/W This register controls the Start Frame Pulse Width generated on the Serial Interrupt signal (SERIRQ). Bit Description 7 Serial IRQ Enable. 1=Serial Interrupts are enabled. 0=Serial Interrupts disabled. 6 Serial IRQ Mode Select. When this bit is a “1”, the serial IRQ machine will be in continuous mode.
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LPC/FWH Interface Configuration 11.1.15 MSTAT–Miscellaneous Status Register (Function 0) Address Offset: Default Value: Attribute: 6A–6Bh 0000h Read/Write This register provides miscellaneous status and control Functions. Bit Description 15 SERR# Generation Due To Delayed Transaction Time-out–R/WC.
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LPC/FWH Interface Configuration 11.1.17 MGPIOC–Muxed GPIO Control (Function 0) Offset: Default Value: Attribute: 84-85h 0500h Read/Write Bit 11.1.18 Description 16:13 Reserved. 12 Reserved. Must be set to ‘1’. 11 Reserved. 10 Reserved. Must be set to ‘1’. 9 Reserved. 8 Reserved. Must be set to ‘1’. 7 Reserved. Must be set to ‘1’. 6 Reserved. Must be set to ‘1’. 5 Reserved. Must be set to ‘1’. 4 Reserved. Must be set to ‘1’. 3:0 Reserved.
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LPC/FWH Interface Configuration These registers provide the base address for distributed DMA slave channel registers, one for each DMA controller. Bits 5:0 are reserved to provide access to a 64 byte I/O space (16 bytes per channel). The channels are accessed using offset from base address as follows (Note that Channel 4 is reserved and is not accessible). Base Offset Channel 00 - 0Fh 0,4 10 - 1Fh 1,5 20 - 2Fh 2,6 30 - 3Fh 3,7 Bits 11.1.
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LPC/FWH Interface Configuration 11.1.21 GPIO Base Address (FUNCTION 0) Address: Default Value: Attributes: D0-D3h 00000001h Read/Write Bit Description 31:16 Reserved. 15:6 Base Address: Provides the 64 bytes of I/O space. 5:1 Reserved. 0 11.1.22 Resource Indicator: Tied to 1 to indicate I/O space GPIO Enable (FUNCTION 0) Address: Default Value Attributes: D4h 00h Read/Write Bit Description 7:1 Reserved. 0 11.1.
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LPC/FWH Interface Configuration Bit 3 2:0 Description Reserved. Decode Range: The following table describes which range to decode for the COMA Port Bits 11.1.24 Decode Range 000 3F8 - 3FF (COM 1) 001 2F8 - 2FF (COM 2) 010 220 - 227 011 228 - 22F 100 238 - 23F 101 2E8 - 2EF (COM 4) 110 338 - 33F 111 3E8 - 3EF (COM 3) LPC FDD/LPT Decode Ranges (Function 0) Address: Default Value: Attributes: E1h 00h Read/Write Bit 7:5 4 Description Reserved.
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LPC/FWH Interface Configuration 11.1.25 LPC Sound Decode Ranges (Function 0) Address: Default Value: Attributes: E2h 00h Read/Write Bit Description 7:6 Reserved.
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LPC/FWH Interface Configuration 11.1.27 LPC Enables (Function 0) Address: Default Value: Attributes: E6-E7h 0000h Read/Write Bit Description 15 Reserved. This bit must be a “0”. 14:13 11.1.27.1 Reserved. 12 Secondary Configuration Enable: Enables I/O locations 4Eh and 4Fh to be sent to the LPC bus. Super I/Os use these addresses as an alternate index/data register pair for Super I/O configuration. 11 Configuration Enable: Enables I/O locations 2Eh and 2Fh to be sent to the LPC bus.
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LPC/FWH Interface Configuration 11.1.27.2 Bit Description 5 FWH_E8_EN: This enables decoding 512KB of the FWH memory range starting at 4 GB – 1.5 MB (FFE80000H) to 4 GB – 1 MB (FFEFFFFFH). Additionally, this enables decoding of 512K of register space starting at (4 GB – 4 MB) - 1.5MB (FFA80000h) to (4 GB – 4 MB) - 1MB (FFAFFFFFh). 4 FWH_E0_EN: This enables decoding 512 KB of the FWH memory range starting at 4 GB – 2 MB (FFE00000H) to 4 GB - 1.5 MB (FFE7FFFFH).
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LPC/FWH Interface Configuration 11.1.27.3 Bit Description 7:4 FWH_C8_IDSEL: This dictates the IDSEL of 512 KB of the FWH memory range starting at 4 GB 3.5 MB (FFC80000H) to 4 GB - 3 MB (FFCFFFFFH) as well as register space starting at (4 GB4MB) - 3.5MB (FF880000h) to (4 GB-4MB) - 3MB (FF8FFFFFh). The enable for this range is controlled through bit 1 of the FWH Decode Enable Register at E3H.
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LPC/FWH Interface Configuration 11.2.1.2 Dcm–Dma Channel Mode Register (I/O) I/O Address: Default Value: Attribute: Channels 0-3=0Bh; Channels 4-7=0D6h Bits[7:2]=0; Bits[1:0]=undefined (CPURST or Master Clear) Write Only Each channel has a 6-bit DMA Channel Mode Register. The Channel Mode Registers provide control over DMA transfer type, transfer mode, address increment/decrement, and autoinitialization. Bit Description 7:6 DMA Transfer Mode.
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LPC/FWH Interface Configuration 11.2.1.4 WSMB–Write Single Mask Bit (I/O) I/O Address: Default Value: Attribute: Channels 0-3–0Ah; Channels 4-7–0D4h Bits[1:0]=undefined; Bit 2=1; Bits[7:3]=0 (CPURST or a Master Clear) Write Only A channel's mask bit is automatically set when the Current Byte/Word Count Register reaches terminal count (unless the channel is programmed for auto-initialization).
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LPC/FWH Interface Configuration 11.2.1.6 Ds–Dma Status Register (I/O) I/O Address: Default Value: Attribute: Channels 0-3–08h; Channels 4-7–0D0h 00h Read Only Each DMA controller has a read-only DMA Status Register that indicates which channels have reached terminal count and which channels have a pending DMA request. Bit Description 7:4 Channel Request Status. When a valid DMA request is pending for a channel (on its DREQ signal line), the corresponding bit is set to 1.
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LPC/FWH Interface Configuration 11.2.1.8 DBCNT–Dma Base and Current Count Registers (I/O) I/O Address: Default Value: Attribute: DMA Channel 0–001h DMA Channel 4–0C2h DMA Channel 1–003h DMA Channel 5–0C6h DMA Channel 2–005h DMA Channel 6–0CAh DMA Channel 3–007h DMA Channel 7–0CEh Undefined (CPURST or Master Clear) Read/Write This register determines the number of transfers to be performed.
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LPC/FWH Interface Configuration Bit 7:0 11.2.1.11 Description Clear Byte Pointer. No specific pattern. Command enabled with a write to the I/O port address. Dmc–Dma Master Clear Register (I/O) I/O Address: Default Value: Attribute: Channel 0-3–00Dh; Channel 4-7–0DAh All bits undefined Write Only This software instruction has the same effect as the hardware Reset. Bit 7:0 11.2.1.12 Description Master Clear. No specific pattern.
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LPC/FWH Interface Configuration Bit 7:5 11.2.2.2 Description ICW/OCW select. These bits should be 000 when programming the IFB. 4 ICW/OCW select. Bit 4 must be a 1 to select ICW1. After the fixed initialization sequence to ICW1, ICW2, ICW3, and ICW4, the controller base address is used to write to OCW2 and OCW3. Bit 4 is a 0 on writes to these registers. A 1 on this bit at any time will force the interrupt controller to interpret the write as an ICW1.
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LPC/FWH Interface Configuration 11.2.2.4 Icw3–Initialization Command Word 3 Register (I/O) I/O Address: Default Value: Attribute: INT CNTRL-2–0A1h All bits undefined Write Only On CNTRL-2 (the slave controller), ICW3 is the slave identification code broadcast by CNTRL-1. Bit 11.2.2.5 Description 7:3 Reserved. Must be programmed to all 0s. 2:0 Slave Identification Code. Must be programmed to 02h.
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LPC/FWH Interface Configuration 11.2.2.7 Bit Description 7:0 Interrupt Request Mask (Mask [7:0]). When a 1 is written to any bit in this register, the corresponding IRQx line is masked. For example, if bit 4 is set to a 1, then IRQ4 is masked. Interrupt requests on IRQ4 do not set channel 4’s interrupt request register (IRR) bit as long is the channel is masked. When a 0 is written to any bit in this register, the corresponding IRQx is unmasked.
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LPC/FWH Interface Configuration Bit 5 4:3 Description Enable Special Mask Mode (ESMM). 1=Enable SMM bit; 0=Disable SMM bit. OCW3 Select. Must be programmed to 01 selecting OCW3. 2 Poll Mode Command. 0=Disable Poll Mode Command. When bit 2=1, the next I/O read to the interrupt controller is treated as an interrupt acknowledge cycle indicating highest priority request. 1:0 Register Read Command.
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LPC/FWH Interface Configuration 11.2.2.10 Elcr2–Edge/Level Control Register (I/O) I/O Address: Default Value: Attribute: INT CNTRL-2–4D1h 00h Read/Write ELCR2 register allows IRQ[15,14,12:9] to be edge or level programmable on an interrupt by interrupt basis. Note that, IRQ[13,8#] are not programmable and are always edge sensitive. When level triggered, the interrupt is signaled active when input IRQ signal is high. Bit Description 7 IRQ15 ECL. 0 = Edge Triggered mode; 1 = Level Triggered mode.
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LPC/FWH Interface Configuration The Timer Control Word Register specifies the counter selection, the operating mode, the counter byte programming order and size of the count value, and whether the counter counts down in a 16bit or binary-coded decimal (BCD) format. After writing the control word, a new count can be written at any time. The new value takes effect according to the programmed mode.
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LPC/FWH Interface Configuration Register bit definitions are different during the Counter Latch Command than for a normal Timer Counter Register write. Note that, If a counter is programmed to read/write two-byte counts, a program must not transfer control between reading the first and second byte to another routine that also reads from that same counter. Otherwise, an incorrect count will be read. 11.2.3.
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LPC/FWH Interface Configuration 11.2.4 NMI Registers The NMI logic incorporates two different 8-bit registers. The CPU reads the NMISC Register to determine the NMI source (bits set to a 1). After the NMI interrupt routine processes the interrupt, software clears the NMI status bits by setting the corresponding enable/disable bit to a 1. The NMI Enable and Real-Time Clock Register can mask the NMI signal and disable/enable all NMI sources.
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LPC/FWH Interface Configuration 11.2.4.2 NmiEN–Nmi Enable Register (Shared with Real-time Clock Index Register) (I/O) I/O Address: Default Value: Attribute: 070h Bit[6:0]=undefined; Bit 7=1 Write Only This port is shared with the real-time clock. Do not modify the contents of this register without considering the effects on the state of the other bits. Bit 7 6:0 Description NMI Enable. 1=Disable generation of NMI; 0=Enable generation of NMI. Real Time Clock Address.
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LPC/FWH Interface Configuration 11.2.5.3 RTCEI–Real-time Clock Extended Index Register (I/O) I/O Address: Default Value: Attribute: 072h Unknown Write Only The index port for accesses to the RTC extended RAM bank. Bit 7 6:0 11.2.5.4 Description Reserved. Real Time Clock Extended Address. Latched by the Real Time Clock to address memory locations within the extended RAM bank accessed via the Real Time Clock Extended Data Register (073h).
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LPC/FWH Interface Configuration 11.2.6.2 APMS–Advanced Power Management Status Port (I/O) I/O Address: Default Value: Attribute: 0B3h 00h Read/Write This register passes status information between the OS and the SMI handler. The IFB operation is not effected by the data in this register. Bit 7:0 11.2.7 Description APM Status Port (APMS). Writes store data in this register and reads return the last data written. ACPI Registers The ACPI registers are I/O mapped.
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LPC/FWH Interface Configuration Bit 0 11.2.7.2 Description TMROF_STS: This is the timer overflow status bit. This bit gets set anytime the 22nd bit of the 24 bit timer goes from high to low (bits are counted from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit is set, the setting of the TMROF_STS bit will generate an SCI or SMI. SMI will be generated if ACPI_TMR_EN, SMI_EN and TMROF_EN are set, and SCI_EN is not set. SCI will be generated if SCI_EN and TMROF_EN are set.
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LPC/FWH Interface Configuration Bit Description Bits Mode 000 ON 001 Typically mapped to S1 state. STPCLK# active. CPU in StopGrant state. Equivalent to Level 2. 010 Typically mapped to S1 state. Both STPCLK# and SLP# signals active. CPU in Sleep state. Equivalent to Level 3. 011 S3 state. This is also known as Suspend-To-RAM (STR). The SUSB signal will go active. 100 S4/S5 state. The S4 state is also known as Suspend-To-Disk (STD). The S5 state is also known as Soft-Off.
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LPC/FWH Interface Configuration Bit 15:12 Reserved. 11 PWR_FAIL: This bit will be set to 1 when a power failure occurs. This is defined as either PWROK or RSMRST# going inactive unexpectedly. This bit is only set by hardware and can only be reset by writing a one to this bit position. This bit is not affected by a hard reset caused by a CF9 write. Upon power up, this bit is set to ‘1’. 10 RI_STS: This bit will be set by 1 to hardware when the RI# input signal goes active.
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LPC/FWH Interface Configuration 11.2.7.7 Bit Description 1 NMI_EN: This bit enables an SCI to be generated on a NMI event. Upon power up, this bit is set to ‘0’. 0 THRM_EN: This is the thermal enable bit. When this bit is set an active level assertion of the THRM# signal (as defined by the THRM_POL bit) will set the THRM_STS bit and generate a power management event (an SCI or SMI). Upon power up, this bit is set to ‘0’.
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LPC/FWH Interface Configuration 11.2.8.1 Global Control and Enable Address Offset: Attributes: Default Value: Size: Bit 15:13 11-36 1A-1Bh Read/Write Bits 8 Undefined, Bit 3 ‘1’, All other bits ‘0’ 16 bits Description Reserved. 12 ACPI_TMR_EN: If not using ACPI (SCI) mode, as indicated by SCI_EN not set, then the ACPI_TMR_EN bit can be set to cause an SMI#. SMI will be generated if this bit, SMI_EN and TMROF_EN are set, and SCI_EN is not set. 11 Reserved.
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LPC/FWH Interface Configuration 11.2.8.2 Global Status Register Address Offset: Attributes: Default Value: Size: 1Ch-1Dh Read/Write 0000h 16 bits Bit 15:11 Description Reserved. 10 ECC_STS: This bit is set when ECCINT# asserted for more than 1 PCI clock with the ECC SERR# bit in configuration space set, or for one or more clocks if the ECC SERR# bit is not set. The setting of this bit will cause an SMI if the ECC_EN bit in the Global Control and Enable register (offset 1A-1Bh) is set.
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LPC/FWH Interface Configuration 11.2.9.1 Bit GPIO Bit GPIO 25 GPIO[19] 5 GPIO[5] 24 GPIO[18] 4 GPIO[4] 23 Reserved 3 GPIO[3] 22 Reserved 2 GPIO[2] 21 Reserved 1 GPIO[1] 20 Reserved 0 GPIO[0] 19 GPIO[13] 18 GPIO[12] 17 GPIO[11] 16 GPIO[10] GP Output Offset: Attribute: Default Value: Size: 00-03h Read/Write 00000000h 32 bits Bit 11.2.9.2 Description 31:29 Reserved. 28:24 Mux Output: When set to a ‘0’, the muxed GPIO pin is programmed as an input.
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LPC/FWH Interface Configuration 11.2.9.3 Bit Description 19:16 Muxed Data: If a data bit is programmed to be an output, then this bit can be updated by software to drive a value on the output pin. If the data bit is programmed as an input, then this bit reflects the state of the input pin and cannot be updated by software. This bit cannot be changed once the GP Lock bit is set. The value of this bit only has meaning if the muxed GPIO is enabled as a GPIO. 15:9 Reserved.
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LPC/FWH Interface Configuration 11.2.9.4 GP Blink Offset: Attribute: Default Value: Size: 0C-0Fh Read/Write 00000000h 32 bits Bit 11.2.9.5 Description 31:9 Reserved. 8:0 Blink: When set to a ‘1’, and the GP pin is programmed as an output, it will blink at a rate of once per second. The value of the data bit remains unchanged during the blink process. If it was set, it remains set. The setting of this bit has no effect if the pin is programmed as an input.
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LPC/FWH Interface Configuration 11.2.9.7 GP SMI Offset: Attribute: Default Value: Size: 1C-1Fh Read/Write 00000000h 32 bits Bit 11.2.9.8 Description 31:9 Reserved. 8:0 SMI Rout: When set to a ‘1’, and the corresponding data bit is set to an input, a ‘1’ in the data bit register will be routed to an SMI. If the data bit is set to an output, this value of this bit has no effect. When cleared, no routing is performed. This bit cannot be changed once the GP Lock bit is set.
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LPC/FWH Interface Configuration 11-42 Intel® 460GX Chipset Software Developer’s Manual
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12 IDE Configuration The IFB PCI Function 1 contains an IDE Controller capable of Programmed I/O (PIO) transfers as well as Bus Master transfer capability. It also supports the “Ultra DMA/33” synchronous DMA mode of data transfer. The register set associated with IDE Controller is shown below. 12.1 PCI Configuration Registers (Function 1) Table 12-1. PCI Configuration Registers–Function 1 (IDE Interface) 12.
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IDE Configuration 12.2.1 VID–Vendor Identification Register (Function 1) Address Offset: Default Value: Attribute: 00–01h 8086h Read only The VID Register contains the vendor identification number. This register, along with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 12.2.2 Description Vendor Identification Number.
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IDE Configuration 12.2.4 PCISTS–PCI Device Status Register (Function 1) Address Offset: Default Value: Attribute: 06–07h 0280h Read/Write PCISTS is a 16-bit status register for the IDE interface Function. The register also indicates the IFB's DEVSEL# signal timing. Bit 15 Detected Parity Error. Read as 0. 14 SERR# Status. Read as 0. 13 Master-Abort Status (MAS)–R/WC. When the Bus Master IDE interface Function, as a master, generates a master abort, MAS is set to a 1.
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IDE Configuration 12.2.6 MLT–Master Latency Timer Register (Function 1) Address Offset: Default Value: Attribute: 0Dh 00h Read/Write MLT controls the amount of time IFB, as a bus master, can burst data on the PCI Bus. The count value is an 8 bit quantity. However, MLT[3:0] are reserved and 0 when determining the count value. The Master Latency Timer is cleared and suspended when IFB is not asserting FRAME#. When IFB asserts FRAME#, the counter begins counting.
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IDE Configuration 12.2.8 SVID–Subsystem Vendor ID (Function 1) Address: Default Value: Attribute: 2C-2Dh 0000h Read only Bit Description 15:0 12.2.9 Subsystem Vendor ID. SID–Subsystem ID (Function 1) Address: Default Value: Attribute: 2E-2Fh 0000h Read only Bit Description 15:0 12.2.10 Subsystem ID.
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IDE Configuration Bit 9:8 Description Recovery Time (RTC). This field selects the minimum number of PCI clocks between the last IORDY# sample point and the DIOx# strobe of the next cycle. Bits[9:8] Number of Clocks 00 4 01 3 10 2 11 1 7 DMA Timing Enable Only (DTE1). When DTE1=1, fast timing mode is enabled for DMA data transfers for drive 1. PIO transfers to the IDE data port will run in compatible timing. When DTE1 = 0, both DMA and PIO data transfers for drive 1 will use the fast timing mode.
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IDE Configuration Bit Description 7:6 Secondary Drive 1 IORDY Sample Point (SISP1). This field selects the number of PCI clocks between SDIOx# assertion and the first SIORDY sample point for the slave drive on the secondary channel. Bits[7:6] Number of Clocks 00 5 01 4 10 3 11 2 5:4 Secondary Drive 1 Recovery Time (SRTC1). This field selects the minimum number of PCI clocks between the last SIORDY# sample point and the SDIOx# strobe of the next cycle for the slave drive on the secondary channel.
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IDE Configuration 12.2.13 SDMATIM–Synchronous DMA Timing Register (Function 1) Address Offset: Default Value: Attribute: 4A-4Bh 0000h Read/Write only This register controls the timings used by each Synchronous DMA enabled device. For nonsynchronous DMA operation, this register should be left programmed to its default value. Bit Description 15:14 Reserved.
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IDE Configuration Table 12-2. Ultra DMA/33 Timing Mode Settings Ultra DMA/33 Timing Modes Cycle Time Bit Settings Mode 0 (120 ns) Mode 1 (90 ns) Mode 2 (60 ns) 00 01 10 Table 12-3.
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IDE Configuration Bit 7:4 3 Description Reserved. Bus Master Read/Write Control (RWCON). 0=Reads; 1=Writes. This bit must NOT be changed when the bus master Function is active. While a synchronous DMA transfer is in progress, this bit will be READ ONLY. The bit will return to read/write once the synchronous DMA transfer has been completed or halted. 2:1 0 Reserved. Start/Stop Bus Master (SSBM). 1=Start; 0=Stop. When this bit is set to 1, bus master operation starts.
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IDE Configuration Table 12-4. Interrupt/Activity Status Combinations 12.3.3 Bit 2 Bit 0 Description 0 1 DMA transfer is in progress. No interrupt has been generated by the IDE device. 1 0 The IDE device generated an interrupt and the Physical Region Descriptors exhausted. This is normal completion where the size of the physical memory regions is equal to the IDE device transfer size. 1 1 The IDE device generated an interrupt.
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IDE Configuration 12-12 Intel® 460GX Chipset Software Developer’s Manual
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Universal Serial Bus (USB) Configuration 13 The IFB integrates one USB Controller. The USB Controller is UHCI 1.1 compliant and implements the root hub of the USB, which contains two ports. The IFB PCI Function 2 reflects the USB Host and Root Hubs, with 2 connected USB ports. The register set associated with USB Host Controller is shown below with actual register descriptions given in Section 13.2 and Section 13.3. 13.1 PCI Configuration Registers (Function 2) Table 13-1.
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Universal Serial Bus (USB) Configuration 13.2 USB Host Controller Register Descriptions (PCI Function 2) This section describes in detail the registers associated with the IFB USB Host Controller Functions. This includes UHCI compatible registers and Legacy Keyboard registers. 13.2.1 VID–Vendor Identification Register (Function 2) Address Offset: Default Value: Attribute: 00–01h 8086h Read only The VID Register contains the vendor identification number.
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Universal Serial Bus (USB) Configuration Bit 13.2.4 Description 1 Memory Space Enable (Not Implemented). This bit is hardwired to 0. 0 I/O Space Enable (IOSE). 1=Enable. 0=Disable. This bit controls the access to the I/O space registers. If this bit is set, access to the host controller I/O registers is enabled. The base register for the I/O registers must be programmed before this bit is set.
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Universal Serial Bus (USB) Configuration 13.2.6 CLASSC–Class Code Register (Function 2) Address Offset: Default Value: Attribute: 0A-0Bh 0C03h Read only This register identifies the Base Class Code, Sub-Class Code, and Device Programming interface for IFB PCI Function 2. Bit 13.2.7 Description 23:16 Base Class Code (BASEC). 0Ch=Serial Bus controller. 15:8 Sub-Class Code (SCC). 03h=USB Host Controller.. 7:0 Programming Interface (PI). 00h=Universal Host Controller Interface.
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Universal Serial Bus (USB) Configuration 13.2.9 USBBA–USB I/O Space Base Address (Function 2) Address Offset: Default Value: Attribute: 20-23h 00000001h Read/Write This register contains the base address of the USB I/O Registers. Bit 31:16 Reserved. Hardwired to 0s. Must be written as 0S. 15:5 Index Register Base Address. Bits [15:5] correspond to I/O address signals AD [15:5], respectively. 4:1 Reserved. Read as 0. 0 13.2.10 Description Resource Type Indicator (RTE)–RO.
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Universal Serial Bus (USB) Configuration 13.2.13 INTPN–Interrupt Pin (Function 2) Address Offset: Default Value: Attribute: 3Dh 04h Read only This register indicates which PCI interrupt pin is used for the USB module interrupt. The USB interrupt is internally ORed to the interrupt controller with the PIRQD# signal. Bit 13.2.14 Description 7:3 Reserved. 2:0 Serial Bus Module Interrupt Routing.
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Universal Serial Bus (USB) Configuration Bit Description 15 End OF A20GATE Pass Through Status (A20PTS)–R/WC. This bit is set to 1 to indicate that the A20GATE pass-through sequence has ended. This bit will only be set if bit 7 of this register is also set. Software must use the enable bits to determine the exact cause of an SMI#. Software clears this bit by writing a 1 to it. 14 Reserved. 13 USB PIRQ Enable (USBPIRQDEN)–R/W. 1 (default) = USB interrupt is routed to PIRQD.
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Universal Serial Bus (USB) Configuration 13.2.17 USBREN–USB Resume Enable Address Offset: Default Value: Attribute: Bit 7:2 C4h 00h Read/Write Description Reserved. 1 PORT1EN: Enable port 1 of the USB controller to look at wakeup events. When set, the USB controller will monitor port 1 for a connect/disconnect, which is a resume event for USB. When cleared, the USB controller will not look at this port for a wakeup event. This bit applies to port 1.
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Universal Serial Bus (USB) Configuration Bit Description 3 Enter Global Suspend Mode (EGSM). 1=Host Controller enters the Global Suspend mode. No USB transactions occur during this time. The Host Controller is able to receive resume signals from USB and interrupt the system. Software resets this bit to 0 to come out of Global Suspend mode. Software writes this bit to 0 at the same time that Force Global Resume (bit 4) is written to 0 or after writing bit 4 to 0.
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Universal Serial Bus (USB) Configuration 13.3.2 USBSTS–USB Status Register (I/O) I/O Address: Default Value: Attribute: Base + (02-03h) 0000h Read/Write Clear This register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by writing a 1 to it. Bit 15:6 Description Reserved. 5 HCHalted.
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Universal Serial Bus (USB) Configuration 13.3.4 FRNUM–Frame Number Register (I/O) I/O Address: Default Value: Attribute: Base + (06-07h) 0000h Read/Write (Writes must be Word Writes) Bits [10:0] of this register contain the current frame number which is included in the frame SOF packet. This register reflects the count value of the internal frame number counter. Bits [9:0] are used to select a particular entry in the Frame List during schedule execution.
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Universal Serial Bus (USB) Configuration required by the USB specification. It’s initial programmed value is system dependent based on the accuracy of hardware USB clock and is initialized by system BIOS. It may be reprogrammed by USB system software at any time. Its value will take effect from the beginning of the next frame. This register is reset upon a Host Controller Reset or Global Reset. Software must maintain a copy of its value for reprogramming if necessary. Bit 7 6:0 Description Reserved.
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Universal Serial Bus (USB) Configuration Bit 12 Description Suspend–R/W. 1=Port in suspend state. 0=Port not in suspend state. This bit should not be written to a 1 if global suspend is active (bit 3=1 in the USBCMD register). Bit 2 and bit 12 of this register define the hub states as follows: Bits [12,2] Hub Port State x0 Disable 01 Enable 11 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for singleended 0 resets (global reset and port reset).
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Universal Serial Bus (USB) Configuration 13-14 Intel® 460GX Chipset Software Developer’s Manual
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14 SM Bus Controller Configuration The IFB PCI Function 3 contains the SMBus Controller configuration space. 14.
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SM Bus Controller Configuration 14.2 System Management Register Descriptions This section describes in detail the registers associated with the IFB System Management Function. 14.2.1 VID–Vendor Identification Register (Function 3) Address Offset: Default Value: Attribute: 00–01h 8086h Read only The VID Register contains the vendor identification number. This register, along with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect.
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SM Bus Controller Configuration 14.2.4 Bit Description 1 Memory Space Enable (Not Implemented). 1=Enable. 0=Disable. This bit controls the access to memory space. If this bit is set, access to the memory space by power management logic is enabled. 0 I/O Space Enable (IOSE). 1=Enable. 0=Disable. This bit controls the access to the I/O space registers. If this bit is set, access to the power management I/O registers is enabled.
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SM Bus Controller Configuration 14.2.6 CLASSC–Class Code Register (Function 3) Address Offset: Default Value: Attribute: 09-0Bh 0C0500h Read only This register identifies the Base Class Code, Sub-Class Code, and Device Programming interface for IFB PCI Function 3. Bit 14.2.7 Description 23:16 Base Class Code (BASEC). 0Ch = Serial Bus Controller. 15:8 Sub-Class Code (SCC). 05h = System Management Bus (SMBus) Controller. 7:0 Programming Interface (PI).
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SM Bus Controller Configuration 14.2.9 SID–Subsystem ID (Function 3) Address: Default Value: Attribute: 2E-2Fh 0000h Read only Bit 15:0 14.2.10 Description Subsystem ID. INTLN–Interrupt Line Register (Function 3) Address Offset: Default Value: Attribute: 3Ch 00h Read/Write Software programs this register with interrupt information concerning the Power Management module. Bit 7:0 14.2.11 Description Interrupt Line. The value in this register has no affect on IFB hardware operations.
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SM Bus Controller Configuration 14.2.13 smbslvc–SMBus Slave Command (Function 3) Address Offset: Default Value: Attribute: 14.2.14 Bit Description 7:0 SMBus Host Slave Command (SMBCMD)–R/W. Specifies the command values to be matched for SMBus master accesses to the SMBus controller host slave interface (SMBus port 10h). smbshdw1–SMBus Slave Shadow Port 1 (Function 3) Address Offset: Default Value: Attribute: 14.2.15 42h 00h Read/Write Bit Description 7:0 SHDW1_ADD: Slave shadow address 1.
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SM Bus Controller Configuration 14.3.1 smbhststs–SMBus Host Status Register (I/O) I/O Address: Default Value: Attribute: Base + (00h) 00h Read/Write This register provides status information concerning the SMBus controller host interface. Bit 7:5 Description Reserved. 4 Failed (FAILED)–R/WC. 1 = Indicates that the source of SMBus interrupt was a failed bus transaction, set when KILL bit is set (SMBHSTCNT register). 0 = SMBus interrupt not caused by KILL bit.
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SM Bus Controller Configuration 14.3.3 Bit Description 2 Slave Status (SLV_STS)–R/WC. 1 = Indicates that the source of SMBus interrupt or resume event was a slave cycle event match of the SMBSLVC (command match) and SMBSLVEVT (data event match). 0 = SMBus interrupt not caused by slave event match. This bit is only set by hardware and can only be reset by writing a 1 to this bit position. 1 Reserved. 0 Slave Busy (SLV_BSY)–RO.
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SM Bus Controller Configuration 14.3.4 smbhstcmd–SMBus Host Command Register (I/O) I/O Address: Default Value: Attribute: Base + (03h) 00h Read/Write This register is transmitted by the SMBus controller host interface in the command field of the SMBus protocol. Bit 7:0 14.3.5 Description SMBus Host Command (HST_CMD)–R/W. This field contains the data transmitted in the command field of SMBus host transaction.
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SM Bus Controller Configuration 14.3.7 smbhstdat1–SMBus Host Data 1 Register (I/O) I/O Address: Default Value: Attribute: Base + (06h) 00h Read/Write This register is transmitted by the SMBus controller host interface in the Data1 field of the SMBus protocol. Bit 7:0 14.3.8 Description SMBus Data 1 (SMBD1)–R/W. This register should be programmed with the value to be transmitted in the Data1 field of an SMBus host interface transaction.
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SM Bus Controller Configuration 14.3.9.1 Bit Description 0 Slave Enable (SLV_EN)–R/W. 1 = Enable the generation of an interrupt or resume event upon an external SMBus master generating a transaction with an address that matches the host controller slave port of 10h, a command field which matches the SMBSLVC register, and a match of one of the corresponding enabled events in the SMBSLVEVT register. 0 = Disable. 10.3.10.
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SM Bus Controller Configuration 14-12 Intel® 460GX Chipset Software Developer’s Manual
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PCI/LPC Bridge Description 15.1 15 PCI Interface The IFB incorporates a fully PCI Bus compatible master and slave interface. As a PCI master, the IFB runs cycles on behalf of DMA, Bus Master IDE, and USB. The IFB implements an internal arbiter to request the PCI bus IDE and USB for these master Functions. All memory cycles run by the IFB master interface target system DRAM.
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PCI/LPC Bridge Description internal interrupts are used for internal Functions only. IRQ2 is used to cascade the two controllers together and is not available to the user. IRQ0 is used as a system timer interrupt and is tied to Interval Timer 1, Counter 0. IRQ13 is connected internally to FERR#. The remaining 13 interrupt lines (IRQ1, IRQ3-IRQ12, IRQ14, and IRQ15) are available for external system interrupts.
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PCI/LPC Bridge Description For CNTRL-2, ICW3 is the slave identification code used during an interrupt acknowledge cycle. CNTRL-1 broadcasts a code to CNTRL-2 over three internal cascade lines if an IRQ[x] line from CNTRL-2 won the priority arbitration on the master controller and was granted an interrupt acknowledge by the CPU.
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PCI/LPC Bridge Description perform a non-specific EOI operation at the trailing edge of the last interrupt acknowledge pulse. Note that from a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single Interrupt Controller. The AEOI mode can only be used in a master Interrupt Controller and not a slave (on CNTRL-1 but not CNTRL-2). 15.2.3 Modes of Operation 15.2.3.
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PCI/LPC Bridge Description 15.2.3.4 Specific Rotation (Specific Priority) The programmer can change priorities by programming the bottom priority and thus fixing all other priorities. For example, if IRQ5 is programmed as the bottom priority device, then IRQ6 will be the highest priority device. The Set Priority Command is issued in OCW2 where: R=1, SL=1; LO-L2 is the binary priority level code of the bottom priority device. See the register description for the bit definitions.
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PCI/LPC Bridge Description 15.2.5 Edge and Level Triggered Mode This mode is programmed using bit 3 in ICW1. With IFB this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. This is the Edge/Level control Registers ELCR1 and ELCR2. The default programming is equivalent to programming the LTIM bit (ICW1 bit 3) to a 0 (all interrupts selected for edge triggered mode).
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PCI/LPC Bridge Description Thus, any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern. Without Special Mask Mode, if an interrupt service routine acknowledges an interrupt without issuing an EOI to clear the IS bit, the interrupt controller inhibits all lower priority requests. The Special Mask Mode provides an easy way for the interrupt service routine to selectively enable only the interrupts needed by loading the Mask register.
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PCI/LPC Bridge Description individual PIRQx# line to any one of 11 IRQ inputs. The assignment is programmable through the PIRQx Route Control registers. One or more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not required, the Route Registers can be programmed to disable steering. Bits 0-3 in each PIRQx Route Control register are used to route the associated PIRQx# line to an internal IRQ input. Bit 7 in each register is used to disable routing of the associated PIRQx#.
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PCI/LPC Bridge Description During the Sample phase, the device drives SERIRQ low if the corresponding interrupt signal is low. If the corresponding interrupt is high, then the devices will tri-state the SERIRQ signal. It will remain high due to pull-up resistors. During the other two phases (turnaround and recovery), no device should drive the SERIRQ signal. The IRQ/DATA frames have a specific order and usage, as shown in Table 15-1.
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PCI/LPC Bridge Description 15.4 Timer/Counters The IFB contains three counters that are equivalent to those found in the 82C54 programmable interval timer. The three counters are contained in one IFB timer unit, referred to as Timer-1. Each counter output provides a key system Function. Counter 0 is connected to interrupt controller IRQ0 and provides a system timer interrupt for a time-of-day, diskette time-out, or other system timing Functions.
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PCI/LPC Bridge Description The Counter Latch Command latches the current count so that it can be read by the system. The countdown process continues. The Read Back Command reads the count value, programmed mode, the current state of the OUT pins, and the state of the Null Count Flag of the selected counter. The Read/Write Logic selects the Control Word Register during an I/O write when address lines A[1:0]=11.
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PCI/LPC Bridge Description If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. Otherwise, the counter will be loaded with an incorrect count. The count must always be completely loaded with both bytes. 15.4.1.3 Read Operations It is often desirable to read the value of a counter without disturbing the count in progress.
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PCI/LPC Bridge Description If a counter is programmed to read/write two-byte counts, a program must not transfer control between reading the first and second byte to another routine which also reads from that same counter. Otherwise, an incorrect count will be read. 15.4.1.6 Read Back Command The third method uses the Read Back Command. The Read Back Command is used to determine the count value, programmed mode, and current states of the OUT pin and Null Count flag of the selected counter or counters.
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PCI/LPC Bridge Description The time and calendar data should match the data mode (BCD or binary) and hour mode (12 or 24 hour) as selected in register B. It is up to the programmer to make sure that data stored in these locations is within the reasonable values ranges and represents a possible date and time. The exception to these ranges is to store a value of C0 - FF in the Alarm bytes to indicate a don’t care situation.
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PCI/LPC Bridge Description The extended RAM bank is also accessed using an indexed scheme. I/O address 72h is used as the address pointer and I/O address 73h is used as the data register. Index addresses above 127h are not valid. 15.5.1.1 Register A Address Offset: Default Value: Attribute: 0Ah NA - This register is not affected by any system reset signal. Read/Write This register is used for general configuration of the RTC Functions.
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PCI/LPC Bridge Description 15.5.1.2 Register B Address Offset: Default Value: Attribute: 0Bh X0000XXXb Read/Write This register is used for general configuration of the RTC Functions. 15.5.1.3 Bit(s) Description 7 SET: Enables the update cycles. When is zero, update cycle occurs normally once a second. If set to one, a current update cycle will abort and subsequent update cycles will not occur until SET is returned to zero.
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PCI/LPC Bridge Description 15.5.1.4 Register D Address Offset: Default Value: Attribute: 0Dh NA - This register is not affected by any system reset signal. Read/Write This register is used for various flags. Bit(s) Description 7 Valid RAM and TIME Bit (VRT): The Valid Ram and Time bit is set to one when the PWRGD (power good) signal provided is high. This feature is not typically used. This bit should always be set to 0 for write to this register. 6 Reserved.
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PCI/LPC Bridge Description 15-18 Intel® 460GX Chipset Software Developer’s Manual
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16 IFB Power Management 16.1 Overview IFB is designed for desktop systems, and includes the following power management features for the desktop design: 1. Compliance with industry standard specifications: APM Rev 1.2 ACPI Rev 1.0 Energy Star (30W idle) PCI Power Management Rev 1.0 2. ACPI S1 Sleep State with STPCLK# and/or SLP# active. 3. ACPI S4/S5 Sleep States (Suspend-to-Disk and Soft-Off). 4. ACPI Power management timer. 5. APCI Compliant Power Button and Thermal Input signals. 6.
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IFB Power Management 16.2 IFB Power Planes 16.2.1 Power Plane Descriptions The IFB contains three power planes: 16.2.2 RTC Plane This plane includes the RTC, as well as some of the power management logic. It is intended to be backed up by a battery, even when all other power to the system is shut. Resume Plane This plane contains additional power management logic, as well as other circuits that can wake the systems from the S4-S5 states.
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IFB Power Management 16.2.3 SCI Generation In an ACPI environment, an SCI (system control interrupt) must be generated for any event that must be handled by ACPI software. If the SCI_EN bit is set, the IFB will generate an SCI based on the sources listed below in Table 16-3. Each source can be individually enabled/disabled. Table 16-3. Causes of SCI# SCI Event Comment Overflow of ACPI Timer Time-out every 2.34 seconds. If SCI_EN is not set, the timer overflow will instead cause an SMI#.
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IFB Power Management 16.2.5 ACPI Bits Not Implemented by IFB Many ACPI registers and bits are optional, and do not have to be implemented for a standard desktop design. Table 16-4 shows which bits are not implemented by IFB. Table 16-4. ACPI Bits Not Implemented in IFB Offset 00-01h Register Name/Function PM1 Status 4 04-05h OE-0Fh 15h 16.2.6 BM_STS Not needed for standard desktop. PM1 Control 1 0C-0Dh Comment BM_RLD Stopping CPU clock not supported.
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IFB Power Management A Wake event will cause an exit from the Soft-Off state. The wake events that can wake from the S5 state are: S5 Wake Event 16.
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IFB Power Management 16-6 Intel® 460GX Chipset Software Developer’s Manual