Intel® Core™2 Extreme Processor QX9000Δ Series, Intel® Core™2 Quad Processor Q9000Δ, Q9000SΔ, Q8000Δ, and Q8000SΔ Series Datasheet — on 45 nm process in the 775 land package August 2009 Document Number: 318726-010
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Contents 1 Introduction ............................................................................................................ 11 1.1 Terminology ..................................................................................................... 12 1.1.1 Processor Terminology Definitions ............................................................ 12 1.2 References .......................................................................................................
5.3 5.2.3 On-Demand Mode ...................................................................................84 5.2.4 PROCHOT# Signal ..................................................................................85 5.2.5 THERMTRIP# Signal ................................................................................85 Platform Environment Control Interface (PECI) ......................................................86 5.3.1 Introduction ................................................................
Figures 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 VCC Static and Transient Tolerance......................................................................... 24 VCC Overshoot Example Waveform ......................................................................... 25 Differential Clock Waveform ..................................................................................
Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 3-1 3-2 3-3 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 6-1 7-1 7-2 6 References ..........................................................................................................14 Voltage Identification Definition..............................................................................17 Absolute Maximum and Minimum Ratings ................................................................
Revision History Revision Number Description -001 • Initial release -002 • Added Intel® Core™2 Quad processors Q9550, Q9450, and Q9300 -003 Revision Date November 2007 • Added 1600 MHz FSB • Added Intel® Core™2 Extreme processor QX9770 January 2008 March 2008 • Added Intel® Core™2 Quad processors Q9650 and Q9400 -004 • Added PSI# signal • Updated Sections 6.2.3, 6.2.4, 6.2.5, 6.2.6, 6.2.7, and 6.
Datasheet
Intel® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, Q8000S Series Features • Available at 3.20 GHz and 3.00 GHz (Intel® Core™2 Extreme processor QX9000 series) • Available at 3.0 GHz, 2.83 GHz, 2.66 GHz, and 2.50 GHz (Intel® Core™2 Quad processor Q9650, Q9550, Q9505, Q9450, Q9400, and Q9300) • Available at 2,66 GHz, 2.50 GHz and 2.33 GHz (Intel® Core™2 Quad processor Q8400, Q8300, and Q8200) • Available at 2.83 GHz and 2.
The Intel Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000 and Q9000S series, and Intel® Core™2 Quad processors Q8400 and Q8400S support Intel® Virtualization Technology. Virtualization Technology provides silicon-based functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve on software-only solutions. The Intel® Core™2 Quad processor Q9000 and Q9000S series support Intel® Trusted Execution Technology (Intel® TXT).
Introduction 1 Introduction The Intel® Core™2 Extreme processor QX9000 series and Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series are based on the Enhanced Intel® Core™ microarchitecture. The Enhanced Intel Core microarchitecture combines the performance of previous generation Desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems.
Introduction The processor uses some of the infrastructure already enabled by 775_VR_CONFIG_05 platforms including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling. 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level.
Introduction • • • • • • • • Datasheet memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB. Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1-1. References Document Location Intel® Core™2 Extreme Processor QX9000 Series, Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, and Q8000S Series Specification Update http://www.intel.com/ design/processor/specupdt/ 318727.htm Intel® Core™2 Extreme Processor and Intel® Core™2 Quad Processor Thermal and Mechanical Design Guidelines http://www.intel.
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.
Electrical Specifications Table 2-1. Voltage Identification Definition VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 Voltage VID VID VID VID VID VID VID VID Voltage 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1.6 0 1 0 1 1 1 1 0 1.025 0 0 0 0 0 1 0 0 1.5875 0 1 1 0 0 0 0 0 1.0125 0 0 0 0 0 1 1 0 1.575 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1.5625 0 1 1 0 0 1 0 0 0.
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.
Electrical Specifications 2.6 Voltage and Current Specification 2.6.1 Absolute Maximum and Minimum Ratings Table 2-2 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications 2.6.2 DC Voltage and Current Specification Table 2-3. Voltage and Current Specifications Symbol VID Range Parameter VID Min Typ Max Unit Notes2, 10 0.8500 — 1.3625 V 1 Processor Number V VCC Core QX9770 3.20 GHz (12 MB Cache) Processor Number VCC for 775_VR_CONFIG_05B: QX9650 3.00 GHz (12 MB Cache) Processor Number VCC for 775_VR_CONFIG_05A: Q9650 3.0 GHz (12 MB Cache) Q9550 2.83 GHz (12 MB Cache) Q9550S 2.83 GHz (12 MB Cache) Q9505 2.
Electrical Specifications Table 2-3. Voltage and Current Specifications Symbol Parameter Min Typ — — Max Unit Notes2, 10 Processor Number ICC VTT VTT_OUT_LEFT and VTT_OUT_RIGHT ICC ITT A QX9770 3.20 GHz (12 MB Cache) Processor Number ICC for 775_VR_CONFIG_05B: QX9650 3.00 GHz (12 MB Cache) Processor Number ICC for 775_VR_CONFIG_05A: Q9650 3.0 GHz (12 MB Cache) 100 Q9550 2.83 GHz (12 MB Cache) 100 Q9550S 2.83 GHz (12 MB Cache) 100 Q9505 2.83 GHz (8 MB Cache) 100 Q9505S 2.
Electrical Specifications 5. 6. 7. 8. 9. 10. 22 capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe. Refer to Table 2-4 and Figure 2-1 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current.
Electrical Specifications Table 2-4. VCC Static and Transient Tolerance Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.30 mΩ Typical Voltage 1.38 mΩ Minimum Voltage 1.45 mΩ 0 0.000 -0.019 -0.038 5 -0.007 -0.026 -0.045 10 -0.013 -0.033 -0.053 15 -0.020 -0.040 -0.060 20 -0.026 -0.047 -0.067 25 -0.033 -0.053 -0.074 30 -0.039 -0.060 -0.082 35 -0.046 -0.067 -0.089 40 -0.052 -0.074 -0.096 45 -0.059 -0.081 -0.103 50 -0.065 -0.088 -0.
Electrical Specifications Figure 2-1. VCC Static and Transient Tolerance Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 120 VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 Vcc Maximum VID - 0.050 VID - 0.063 VID - 0.075 VID - 0.088 Vcc [V] VID - 0.100 VID - 0.113 Vcc Typical VID - 0.125 VID - 0.138 VID - 0.150 Vcc Minimum VID - 0.163 VID - 0.175 VID - 0.188 VID - 0.200 VID - 0.213 VID - 0.225 NOTES: 1.
Electrical Specifications 2.6.3 VCC Overshoot The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID).
Electrical Specifications 2.7 Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary.
Electrical Specifications Table 2-6.
Electrical Specifications 2.7.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/ deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional timing requirements for entering and leaving the low power states. 2.7.
Electrical Specifications Table 2-11. CMOS Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage -0.10 VTT * 0.30 V 3, 6 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V 4, 5, 6 VOL Output Low Voltage -0.10 VTT * 0.10 V 6 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 2, 5, 6 IOL Output Low Current VTT * 0.10 / 67 VTT * 0.10 / 27 A 6, 7 IOH Output Low Current VTT * 0.10 / 67 VTT * 0.
Electrical Specifications Table 2-12. PECI DC Electrical Limits Symbol Vin Vhysteresis Definition and Conditions Input Voltage Range Hysteresis Min Max Units -0.15 VTT V 0.1 * VTT — V Vn Negative-edge threshold voltage 0.275 * VTT 0.500 * VTT V Vp Positive-edge threshold voltage 0.550 * VTT 0.725 * VTT V -6.0 N/A mA 0.5 1.0 mA Isource Isink High level output source (VOH = 0.75 * VTT) Low level output sink (VOL = 0.
Electrical Specifications 2.8 Clock Specifications 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. The processor supports Half Ratios between 7.5 and 13.
Electrical Specifications 2.8.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 2-15 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
Electrical Specifications Table 2-17. FSB Differential Clock Specifications (1600 MHz FSB) T# Parameter Notes1 Min Nom Max Unit Figure BCLK[1:0] Frequency 397.962 - 400.037 MHz - T1: BCLK[1:0] Period 2.499766 - 2.512800 ns 2-3 2 - - 150 ps 2-3 3, 4, 7 T5: BCLK[1:0] Rise and Fall Slew Rate 2.5 - 8 V/ns 2-4 5 Slew Rate Matching N/A N/A 20 % - 6 T2: BCLK[1:0] Period Stability NOTES: 1.
Electrical Specifications . Figure 2-3. Differential Clock Waveform Tph Overshoot BCLK1 VH Rising Edge Ringback V CROSS (ABS) Threshold Region V CROSS (ABS) Ringback Margin Falling Edge Ringback BCLK0 VL Undershoot Tpl Tp Tp = T1: BCLK[1:0] period T2: BCLK[1:0] period stability (not shown) Tph = T3: BCLK[1:0] pulse high time Tpl = T4: BCLK[1:0] pulse low time T5: BCLK[1:0] rise time through the threshold region T6: BCLK[1:0] fall time through the threshold region Figure 2-4.
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications Figure 3-4.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications Figure 3-6. Processor Top-Side Markings Example (Intel® Core™2 Quad Processor Q9000 Series) INTEL M ©'06 Q9550 INTEL® CORE™2 Quad SLAN3 XXXX 2.
Package Mechanical Specifications Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 3-7.
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 4-1.
Land Listing and Signal Descriptions Figure 4-2.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # 46 Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # Datasheet Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # 48 Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # Datasheet Signal Buffer Type Direction Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # 50 Signal Buffer Type Direction Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # Datasheet Signal Buffer Type Direction Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # 52 Signal Buffer Type Direction Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # Datasheet Signal Buffer Type Direction Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # 54 Signal Buffer Type Direction Table 4-1.
Land Listing and Signal Descriptions Table 4-2. Datasheet Numerical Land Assignment Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 56 Numerical Land Assignment Land # Land Name Signal Buffer Type AE28 VSS AE29 VSS AE30 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Land # Datasheet Numerical Land Assignment Land Name Signal Buffer Type Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 58 Numerical Land Assignment Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Land # Datasheet Numerical Land Assignment Table 4-2.
Land Listing and Signal Descriptions Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type H12 VSS H13 VSS H14 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 62 Numerical Land Assignment Land # Land Name Signal Buffer Type M25 VCC M26 VCC M27 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Land # Datasheet Numerical Land Assignment Land Name Signal Buffer Type Table 4-2.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 10) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 10) Name BPM[5:0]# BPMb[3:0]# Type Input/ Output Description BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# and BPMb[3:0]# should connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 10) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 4 of 10) Name DEFER# DPRSTP# Type Description Input DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 5 of 10) Name Type Description FERR#/PBE# Output FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 6 of 10) Name ITP_CLK[1:0] LINT[1:0] Type Description Input ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 10) Name PWRGOOD Type Input Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 8 of 10) Name SLP# SMI# Type Description Input SLP# (Sleep), when asserted in Extended Stop Grant or Stop Grant state, causes the processor to enter the Sleep state. In the Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 9 of 10) Name Type Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 10 of 10) Name Type Description VID[7:0] Output The VID (Voltage ID) signals are used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator Design Guide for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals becomes valid.
Land Listing and Signal Descriptions 74 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption.
Thermal Specifications and Design Considerations Table 5-2. Intel® Core™2 Extreme Processor QX9770 Thermal Profile Power Maximum (W) Tc (°C) Figure 5-1. Power Maximum (W) Tc (°C) Power Maximum (W) Tc (°C) Power Maximum (W) Tc (°C) 0 37.8 34 42.2 68 46.6 102 51.1 2 38.1 36 42.5 70 46.9 104 51.3 4 38.3 38 42.7 72 47.2 106 51.6 6 38.6 40 43.0 74 47.4 108 51.8 8 38.8 42 43.3 76 47.7 110 52.1 10 39.1 44 43.5 78 47.9 112 52.4 12 39.4 46 43.8 80 48.
Thermal Specifications and Design Considerations Intel® Core™2 Extreme Processor QX9650 Thermal Profile Table 5-3. Power Maximum (W) Tc (°C) Figure 5-2. Power Maximum (W) Tc (°C) Power Maximum (W) Tc (°C) Power Maximum (W) Tc (°C) 0 42.4 34 48.2 68 54.0 102 59.7 2 42.7 36 48.5 70 54.3 104 60.1 4 43.1 38 48.9 72 54.6 106 60.4 6 43.4 40 49.2 74 55.0 108 60.8 8 43.8 42 49.5 76 55.3 110 61.1 10 44.1 44 49.9 78 55.7 112 61.4 12 44.4 46 50.2 80 56.
Thermal Specifications and Design Considerations Table 5-4. Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile Power Maximum (W) Tc (°C) Figure 5-3. Power Maximum (W) Tc (°C) Power (W) Maximum Tc (°C) Power Maximum (W) Tc (°C) 0 44.8 26 52.1 52 59.4 78 66.6 2 45.4 28 52.6 54 59.9 80 67.2 4 45.9 30 53.2 56 60.5 82 67.8 6 46.5 32 53.8 58 61.0 84 68.3 8 47.0 34 54.3 60 61.6 86 68.9 10 47.6 36 54.9 62 62.2 88 69.4 12 48.2 38 55.
Thermal Specifications and Design Considerations Table 5-5. Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile Power Maximum (W) Tc (°C) Figure 5-4. Power Maximum (W) Tc (°C) Power Maximum (W) Tc (°C) Power Maximum (W) Tc (°C) 0 49.6 18 57.0 36 64.4 54 71.7 2 50.4 20 57.8 38 65.2 56 72.6 4 51.2 22 58.6 40 66.0 58 73.4 6 52.1 24 59.4 42 66.8 60 74.2 8 52.9 26 60.3 44 67.6 62 75.0 10 53.7 28 61.1 46 68.5 64 75.8 12 54.5 30 61.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 5-1. This temperature specification is meant to help ensure proper operation of the processor. Figure 5-5 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (See Section 1.2). Figure 5-5.
Thermal Specifications and Design Considerations periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.
Thermal Specifications and Design Considerations Figure 5-6. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 Temperature fMAX fTM2 Frequency VID VIDTM2 VID PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode.
Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Thermal Specifications and Design Considerations 5.3 Platform Environment Control Interface (PECI) 5.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2Kbps to 2Mbps).
Thermal Specifications and Design Considerations 5.3.2 PECI Specifications 5.3.2.1 PECI Device Address The PECI register resides at address 30h. 5.3.2.2 PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported PECI command function and codes. 5.3.2.
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 6-1.
Features The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.2.2 Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled using the BIOS.
Features 6.2.3.2 Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extended Stop Grant has been enabled using BIOS. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID.
Features state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through the Stop-Grant state.
Features In response to entering Deeper Sleep, the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID pins. Unlike typical Dynamic VID changes (where the steps are single VID steps) the processor will perform a VID jump on the order of 100 mV. To support the Deeper Sleep State the platform must use a VRD 11.1 compliant solution. 6.2.8 Enhanced Intel SpeedStep® Technology The processor supports Enhanced Intel SpeedStep Technology.
Boxed Processor Specifications 7 Boxed Processor Specifications 7.1 Introduction The Intel Core™2 Extreme processor QX9650, Intel Core™2 quad-core processor Q9000, Q9000S, Q8000, and Q8000S series will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution.
Boxed Processor Specifications 7.2 Mechanical Specifications 7.2.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 7-4. Space Requirements for the Boxed Processor (overall view) 7.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (See Section 1.2) for details on the processor weight and heatsink requirements. 7.2.
Boxed Processor Specifications The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 7-6 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 110 mm [4.33 inches] from the center of the processor socket. Figure 7-5.
Boxed Processor Specifications 7.4 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.4.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator.
Boxed Processor Specifications 7.4.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Boxed Processor Specifications If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output (CONTROL see Table 7-1) and remote thermal diode measurement capability the boxed processor will operate as follows: As processor power has increased the required thermal solutions have generated increasingly more noise.
Boxed Processor Specifications Figure 7-10. Space Requirements for the Boxed Processor (side view) 7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight The Boxed Intel® Core™2 Extreme processor QX9650 fan heatsink weight will complies with the socket specifications. See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (See Section 1.2) for details on the processor weight and heatsink requirements. Figure 7-11.
Boxed Processor Specifications Figure 7-12.
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Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Intel® Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature.
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