Intel Xeon Processor MP Specification Update

10 Intel
®
Xeon
®
Processor MP Specification Update
Identification Information
NOTES:
1. These parts require the inputs from A20M#, IGNNE#, LINT[1]/NMI and LINT[0]/INTR pins during RESET to set the correct core
to bus frequency ratio.
2. The Intel
®
Xeon
®
Processor MP listed here is installed onto a micro pin grid array (mPGA) interposer. The overall
processor package is called INT-mPGA.
3. This part is an Intel boxed processor.
4. This part is the Intel
®
Xeon
®
Processor MP with up to 4-MB L3 cache on 0.13- micron process.
5. This part has a VID of 1.5V.
SL6Z2
SL6Z7
B1 0F25h 2.50/400
512-KB
1-MB Yes 01 603-pin
micro-PGA
interposer with
42.5 mm
FC-BGA
package
1, 2, 4
1, 2, 3,4
SL6YL
SL6Z8
B1 0F25h 2.80/400
512-KB
2-MB Yes 01 603-pin
micro-PGA
interposer with
42.5 mm
FC-BGA
package
1, 2,4
1, 2, 3, 4
SL79V C0 0F26h 3/400
512-KB
4-MB Yes 01 603-pin
micro-PGA
interposer with
42.5 mm
FC-BGA
package
1,2,4,5
SL79Z C0 0F26h 2.70/400
512-KB
2-MB Yes 01 603-pin
micro-PGA
interposer with
42.5 mm
FC-BGA
package
1, 2,4
SL7A5 C0 0F26h 2.20/400
512-KB
2-MB Yes 01 603-pin
micro-PGA
interposer with
42.5 mm
FC-BGA
package
1, 2, 4
Table 1. Intel
®
Xeon
®
Processor MP Identification Information(Sheet 2 of 2)
S-Spec
Core
Stepping
Processor
Signature
Speed
Core/Data
Bus
(GHz/MHz)
L2
Cache
Size
L3
Cache
Size
Hyper-
Threading
Technology
Processor
Interposer
Revision
Package And
Revision
2
S-Spec
Notes