Intel Xeon Processor MP Specification Update

Intel
®
Xeon
®
Processor MP Specification Update 35
Errata
Implication: This only impacts JTAG/TAP accesses to the processor. Other bus accesses are not affected.
Workaround: To minimize the effects of this issue, reduce noise on the TCK-net at the processor relative to
ground, and position TCK relative to BCLK to minimize the TAP error rate. Decreasing rise times
to under 800ps reduced the failure rate but does not stop all failures.
Status: For the steppings effected, see the Summary Table of Changes.
O55 Disabling a local APIC disables both logical processor APICs on a
Hyper-Threading Technology enabled processor
Problem: Disabling a local APIC on one logical processor of a HT Technology enabled processor by clearing
bit 11 of the IA32_APIC_BASE MSR will effectively disable the Local APIC on the other logical
processor.
Implication: Disabling a local APIC on one logical processor prevents the other logical processor from sending
or receiving interrupts. Multiprocessor Specification compliant BIOSs and multiprocessor
operating systems typically leave all local APICs enabled preventing any end-user visible impact
from this erratum.
Workaround: Do not disable the local APICs in a HT Technology enabled processor.
Status: For the steppings effected, see the Summary Table of Changes.
O56 Using STPCLK and executing code from very slow memory could lead to a
system hang
Problem: The system may hang when the following conditions are met:
1. Periodic STPCLK mechanism is enabled via the chipset.
2. HT Technology is enabled.
3. One logical processor is waiting for an event (i.e. hardware interrupt).
4. The other logical processor executes code from very slow memory such that every code fetch
is deferred long enough for the STPCLK to be re-asserted.
Implication: If this erratum occurs, the processor will go into and out of the sleep state without making forward
progress, since the logical processor will not be able to service any pending event. This erratum has
not been observed in any commercial platform running commercial software.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O57 Simultaneous cache line eviction from L2 and L3 caches may result in the
write back of stale data
Problem: If a cache line is evicted simultaneously from both the L2 and L3 caches, and the internal bus
queues are full, an older L3 eviction may be allowed to remain in an internal queue entry. If in a
narrow timing window an external snoop is generated the data from the older eviction may be used
to respond to the external snoop.
Implication: In the event that this erratum occurs the contents of memory will be incorrect. This may result in
application, operating system or system failure.
Workaround: BIOS may contain a workaround for this erratum.
Status: For the steppings effected, see the Summary Table of Changes.
O58 The state of the resume flag (RF flag) in a task-state segment (TSS) may be
incorrect
Problem: ITP will not continue in single step execution after the first software breakpoint. ITP is unable to
reset the resume flag (RF) bit in the EFLAGS Register.