64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

16 64-bit Intel

Xeon

Processor MP with up to 1 MB L2 Cache Specification Update

Errata

J1. Transaction is not retired after BINIT#

Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase

it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during

this transaction, the transaction will not be retried.

Implication: When this erratum occurs, locked transactions will not be retried.

Workaround: None identified.

Status: For the steppings affected, see the Summary Table of Changes.

J2. Invalid opcode 0FFFh requires A ModRM byte

Problem: Some invalid opcodes require a ModRM byte and other following bytes, while others do not. The

invalid opcode 0FFFh did not require a ModRM in previous generation microprocessors such as

Pentium

II or Pentium III processors, but it is required in the Intel

Xeon

processor.

Implication: The use of an invalid opcode 0FFFh without the ModRM byte may result in a page or limit fault on

the Intel Xeon processor. When this erratum occurs, locked transactions will not be retried.

Workaround: To avoid this erratum use ModRM byte with invalid 0FFFh opcode.

Status: For the steppings affected, see the Summary Table of Changes.

J3. Processor may hang due to speculative page walks to non-existent system

memory

Problem: a load operation issued speculatively by the processor that misses the data translation lookaside

buffer (dtlb) results in a page walk. a branch instruction older than the load retires so that this load

operation is now in the mispredicted branch path. due to an internal boundary condition, in some

instances the load is not canceled before the page walk is issued.

The Page Miss Handler (PMH) starts a speculative page-walk for the Load and issues a cacheable

load of the Page Directory Entry (PDE). This PDE load returns data that point to a page table entry

in uncacheable (UC) memory. The PMH issues the PTE Load to UC space, which is issued on the

Front Side Bus. No response comes back for this load PTE operation since the address is pointing

to system memory, which does not exist.

This load to non-existent system memory causes the processor to hang because other bus requests

are queued up behind this UC PTE load, which never gets a response. If the load was accessing

valid system memory, the speculative page-walk would successfully complete and the processor

would continue to make forward progress.

Implication: Processor may hang due to speculative page walks to non-existent system memory.

Workaround: Page directories and page tables in UC memory space must point to system memory that exists.

Status: For the steppings affected, see the Summary Table of Changes.

J4. Memory type of the load lock different from its corresponding store unlock

Problem: The Intel Xeon Processor employs a use-once protocol to ensure that a processor in a multipro-

cessor system may access data that are loaded into its cache on a Read-for-Ownership operation at

least once before it is snooped out by another processor. This protocol is necessary to avoid a dual

processor livelock scenario where no processor in the system can gain ownership of a line and