64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

34 64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update
Errata
J59. An REP MOVS or an REP STOS instruction with RCX >= 2^32 may fail to
execute to completion or may write to incorrect memory locations on
processors supporting Intel
®
Extended Memory 64 Technology
(Intel
®
EM64T)
Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP MOVS or an REP STOS
instruction executed with the register RCX >= 2^32, may fail to execute to completion or may
write data to incorrect memory locations.
Implication: This erratum may cause an incomplete instruction execution or incorrect data in the memory. Intel
has not observed this erratum with any commercially available software or system.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J60. An REP LODSB or an REP LODSD or an REP LODSQ instruction with
RCX >= 2^32 may cause a system hang on processors supporting
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP LODSB or an REP LODSD or an
REP LODSQ instruction executed with the register RCX >= 2^32 may fail to complete execution
causing a system hang. Additionally, there may be no #GP fault due to the non-canonical address in
the RSI register.
Implication: This erratum may cause a system hang on Intel EM64T-enabled platforms. Intel has not observed
this erratum with any commercially available software or system.
Workaround: It is possible for the BIOS to contain a workaround for this erratum
Status: For the steppings affected, see the Summary Table of Changes.
J61. CPUID instruction returns incorrect brand string
Problem: When a CPUID instruction is executed on an Intel Xeon processor MP the system reports Intel
Pentium 4 CPU when it should return the Intel Xeon MP brand string.
Implication: When this erratum occurs, the processor will report the incorrect brand string.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J62. Data access which spans both canonical and non-canonical address space
may hang system
Problem: If a data access causes a page split across the canonical to non-canonical address space, the
processor may livelock which in turn would cause a system hang.
Implication: When this erratum occurs, the processor may livelock, resulting in a system hang. Intel has not
observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J63. Running in System Management Mode (SMM) and l1 data cache adaptive
mode may cause unexpected system behavior when SMRAM is mapped to
cacheable memory
Problem: In a HT Technology-enabled system, unexpected system behavior may occur if a change is made to
the value of the CR3 result from an Resume from System Management (RSM) instruction while in