64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

20 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update
Errata
U8 EMON event counting of x87 loads may not work as expected
Problem: If a performance counter is set to count x87 loads and FP exceptions are unmasked, the FPU
Operand (Data) Pointer (FDP) may become corrupted.
Implication: When this erratum occurs, FPU Operand (Data) Pointer (FDP) may become corrupted.
Workaround: This erratum will not occur with FP exceptions masked. If FP exceptions are unmasked, then
performance counting of x87 loads should be disabled.
Status: For the steppings affected, see the Summary Table of Changes.
U9 System bus interrupt messages without data and which receive a hard
failure response may hang the processor
Problem: When a system bus agent (processor or chipset) issues an interrupt transaction without data onto
the system bus, and the transaction receives a hard failure response, a potential processor hang can
occur. The processor, which generates an inter-processor interrupt (IPI) that receives hard failure
response, will still log the MCA error event cause as hard failure, even if the APIC causes a hang.
Other processors, which are true targets of the IPI, will also hang on hard failure-without-data, but
will not record an MCA hard failure event as a cause. If a hard Failure response occurs on a system
bus interrupt message with data, the APIC will complete the operation so as not to hang the
processor.
Implication: The processor may hang
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U10 The processor signals Page Fault exception (#PF) instead of Alignment
Check exception (#AC) on an unlocked CMPXCHG8B instruction
Problem: If a page fault exception (#PF) and alignment check exception (#AC) both occur for an unlocked
CMPXCHG8B instruction, then #PF will be flagged.
Implication: Software that depends on the #AC before the #PF will be affected since #PF is signaled in this case.
Workaround: Remove the software's dependency on #AC having precedence over #PF. Alternately, correct the
page fault in the page fault handler and then restart the faulting instruction.
Status: For the steppings affected, see the Summary Table of Changes.
U11 FSW may not be Completely Restored after Page Fault on FRSTOR or
FLDENV instructions
Problem: If the FPU operating environment or FPU state (operating environment and register stack) being
loaded by an FLDENV or FRSTOR instruction wraps around a 64-Kbyte or 4-Gbyte boundary and
a page fault (#PF) or segment limit fault (#GP or #SS) occurs on the instruction near the wrap
boundary, the upper byte of the FPU status word (FSW) might not be restored. If the fault handler
does not restart program execution at the faulting instruction, stale data may exist in the FSW.
Implication: When this erratum occurs, stale data will exist in the FSW.
Workaround: Ensure that the FPU operating environment and FPU state do not cross 64-Kbyte or 4-Gbyte
boundaries. Alternately, ensure that the page fault handler restarts program execution at the faulting
instruction after correcting the paging problem.
Status: For the steppings affected, see the Summary Table of Changes.
U12 Processor issues inconsistent transaction size attributes for locked
operation
Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the
Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte