64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

32 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update
Errata
U59 An REP MOVS or an REP STOS instruction with RCX >= 2^32 may fail to
execute to completion or may write to incorrect memory locations on
processors supporting Intel
®
Extended Memory 64 Technology
(Intel
®
EM64T)
Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP MOVS or an REP STOS
instruction executed with the register RCX >= 2^32, may fail to execute to completion or may
write data to incorrect memory locations.
Implication: This erratum may cause an incomplete instruction execution or incorrect data in the memory. Intel
has not observed this erratum with any commercially available software or system.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U60 An REP LODSB or an REP LODSD or an REP LODSQ instruction with
RCX >= 2^32 may cause a system hang on processors supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP LODSB or an REP LODSD or an
REP LODSQ instruction executed with the register RCX >= 2^32 may fail to complete execution
causing a system hang. Additionally, there may be no #GP fault due to the non-canonical address in
the RSI register.
Implication: This erratum may cause a system hang on Intel EM64T-enabled platforms. Intel has not observed
this erratum with any commercially available software or system.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U61. The IA32_MC0_STATUS/IA32_MC1_STATUS/ IA32_MC4_STATUS Overflow
Bit is not set when multiple un-correctable machine check errors occur at
the same time.
Problem: When two enabled MC0/MC1/MC4 un-correctable machine check errors are detected in the same
bank in the same internal clock cycle, the highest priority error will be logged in
IA32_MC0_STATUS / IA32_MC1_STATUS / IA32_MC4_STATUS register, but the overflow bit
may not be set.
Implication: The highest priority error will be logged and signaled if enabled, but the overflow bit in the
IA32_MC0_STATUS / IA32_MC1_STATUS / IA32_MC4_STATUS register may not be set.
Workaround: None identified.
Status: No Fix
U62 Disabled correctable machine check errors may be logged as disabled
uncorrectable errors
Problem: Disabled correctable machine check errors may be logged as disabled un-correctable errors in the
IA32_MC4_STATUS register. This behavior can only occur if the correctable error is not enabled
in the IA32_MC4_CTL register.
Implication: Due to this erratum, the Un-Correctable (UC) and Processor Context Corrupt (PCC) flags could be
set when a disabled correctable error is detected.
Workaround: It is possible for the BIOS to workaround this erratum by enabling the correctable error bits in
IA32_MC4_CTRL.
Status: For the steppings affected, see the Summary Table of Changes.