64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update 33
Errata
U63 Machine check registers may contain incorrect information if a correctable
error is followed by a un-correctable error
Problem: If any two machine check errors (correctable or un-correctable) are detected within the same bus
clock, the address and miscellaneous register information for IA32_MC4_ADDR and IA32_
MC4_MISC may not be reliable.
Implication: Due to this erratum, the contents of IA32_MC4_MISC and IA32_ MC4_ADDR may be incorrect
if two MCA errors are detected within the same bus clock.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U64 Deferred Phase Support (DPS#) and Deferred Enable (DEN#) are asserted
when Branch Trace Messages (BTMs) are issued
Problem: The processor asserts the extended function signals, DEN# and DPS#, with BTM transactions. It is
required that the BTM transaction must be completed in order without being retired or deferred.
The assertion of DEN# and/or DPS# for BTM transactions is not consistent with that requirement.
Implication: A footnote to Table 4-20 in Section 4.3.3 of the current RS - Intel
®
Pentium
®
4 and Intel
®
Xeon™
Processor External Hardware Specification states: “BTM may or may not have DEN# asserted.
However, BTM must not have DEFER# asserted during its Snoop Phase.” No mention is made of
the DEN# and DPS# for BTM transactions in RS - 64-bit Intel
®
Xeon™ processor MP with up to
8 MB L3 Cache External Hardware Specification Addendum. This may have left an ambiguity in
the central agent's handling of BTM transactions when the DEN# and/or DPS# is asserted.
Workaround: The central agent must adhere to the “do not defer/do not retry” warning of the RS - 64-bit Intel
®
Xeon™ processor MP with up to 8 MB L3 Cache External Hardware Specification Addendum
concerning PTM transactions without regard to the DEN# or the DPS# signals.
Status: For the steppings affected, see the Summary Table of Changes.
U65 A data Access which spans both the canonical and the non-canonical
address space may hang the system
Problem: If a data access causes a page split across the canonical to non-canonical address space the
processor may livelock which in turn would cause a system hang.
Implication: When this erratum occurs, the processor may livelock resulting in a system hang. Intel has not
observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U66 A 64-bit value of Linear Instruction Pointer (LIP) may be reported incorrectly
in the Branch Trace Store (BTS) Memory or in the Precise Event Based
Sampling (PEBS) memory record
Problem: On a processor supporting Intel EM64T,
• If an instruction fetch wraps around the 4G boundary in Compatibility Mode, the 64-bit value
of LIP in the BTS memory record will be incorrect (upper 32 bits will be set to FFFFFFFFh
when they should be 0).
• If a PEBS event occurs on a instruction whose last byte is at memory location FFFFFFFFh, the
64-bit value of LIP in the PEBS record will be incorrect (upper 32 bits will be set to
FFFFFFFFh when they should be 0).
Implication: Intel has not observed this erratum on any commercially available software.When this erratum
occurs, the processor may livelock resulting in a system hang. Intel has not observed this erratum
with any commercially available software.