64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

36 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update
Errata
U75. Using 2M/4M pages when A20M# is asserted may result in incorrect address
translations
Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates
real-address mode address wraparound at 1 MB. However, if all of the following conditions are
met, address bit 20 may not be masked. Paging is enabled a linear address has bit 20 set the address
references a large page A20M# is enabled
Implication: When A20M# is enabled and an address references a large page the resulting translated physical
address may be incorrect. This erratum has not been observed with any commercially available
operating system.
Workaround: Operating systems should not allow A20M# to be enabled if the masking of address bit 20 could be
applied to an address that references a large page. A20M# is normally only used with the first
megabyte of memory.
Status: No Fix
U76. Writing shared unaligned data that crosses a cache line without proper
semaphores or barriers may expose a memory ordering issue
Problem: Software which is written so that multiple agents can modify the same shared unaligned memory
location at the same time may experience a memory ordering issue if multiple loads access this
shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans
a cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with
any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying shared data by
multiple agents:
• The shared data is aligned.
• Proper semaphores or barriers are used in order to prevent concurrent data accesses.
Status: No Fix
U77. Processor may hang during entry into No-Fill Mode or No-Eviction Mode
Problem: Only one logical processor per core can be active when processor is put in No-Fill Mode or No-
Eviction Mode. If the other logical processor is active or there is an internal or external event
pending to wake that logical processor, the processor may hang when writing to MSR
IA32_BIOS_CACHE_AS_RAM (80H).
Implication: A processor may hang due to this erratum. Intel has not observed this erratum with any
commercially available software or system.
Workaround: None identified.
Status: No Fix
U78. FPU operand pointer may not be cleared following FINIT/FNINIT
Problem: Initializing the floating point state with either FINIT or FNINT, may not clear the x87 FPU
Operand (Data) Pointer Offset and the x87 FPU Operand (Data) Pointer Selector (both fields form
the FPUDataPointer). Saving the floating point environment with FSTENV, FNSTENV, or floating
point state with FSAVE, FNSAVE or FXSAVE before an intervening FP instruction may save
uninitialized values for the FPUDataPointer.
Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point image or
floating point environment structure may appear to be random values. Executing any non-control
FP instruction with memory operand will initialize the FPUDataPointer. Intel has not observed this
erratum with any commercially available software.