64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update 37
Errata
Workaround: After initialization, do not expect the FPUDataPointer in a floating point state or floating point
environment saved memory image to be correct, until at least one non-control FP instruction with a
memory operand has been executed.
Status: No Fix
U79. L2 cache ECC machine check errors may be erroneously reported after an
asynchronous RESET# assertion
Problem: Problem: Machine check status MSRs may incorrectly report the following L2 Cache ECC
machine-check errors when cache transactions are in-flight and RESET# is asserted:
• Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153)
• L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145)
Implication: Uncorrected or corrected L2 ECC machine check errors may be erroneously reported. Intel has not
observed this erratum on any commercially available system.
Workaround: When a real run-time L2 Cache ECC machine check occurs, a corresponding valid error will
normally be logged in the IA32_MC0_STATUS register. BIOS may clear IA32_MC2_STATUS
and/or IA32_MC1_STATUS for these specific errors when IA32_MC0_STATUS does not have its
VAL flag set.
Status: No Fix
U80. Debug Status Register (DR6) Breakpoint Condition Detected Flags May be
Set Incorrectly
Problem: The Debug Status Register (DR6) may report detection of a spurious breakpoint condition under
certain boundary conditions when either:
• A "MOV SS" or "POP SS" instruction is immediately followed by a hardware
debugger breakpoint instruction, or
• Any debug register access ("MOV DRx, r32" or "MOV r32, DRx") results in a
general-detect exception condition.
Implication: Due to this erratum the breakpoint condition detected flags may be set incorrectly.
Workaround: None identified.
Status: No Fix.
U81 A Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E
or PDPTE
Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is reserved in
PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a
PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an
entry is ignored and no page fault will occur due to its being set.
Implication: Software may not operate properly if it relies on the processor to deliver page faults when reserved
bits are set in paging-structure entries.
Workaround: Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to “1”.
Status: No Fix.