64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

8 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update
Identification Information
NOTES:
1. The Extended Family corresponds to bits [27:20] of the EDX register after RESET, bits [27:20] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation
field of the Device ID register accessible through Boundary Scan.
2. The Extended Model corresponds to bits [19:16] of the EDX register after RESET, bits [19:16] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of
the Device ID register accessible through Boundary Scan.
3. The Type corresponds to bits [13:12] of the EDX register after RESET, bits [13:12] of the EAX register
after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the
Device ID register accessible through Boundary Scan.
4. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register
after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the
Device ID register accessible through Boundary Scan.
5. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after
the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID
register accessible through Boundary Scan.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers
after the CPUID instruction is executed with a 2 in the EAX register. Please refer to the AP-485
Intel
®
Processor Identification and the CPUID Instruction Application Note for further
information on the CPUID instruction.
NOTES:
1. These components have Hyper-Threading Technology (HT Technology) enabled.
2. These parts have been enabled with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
3. These parts have Tcontrol programmed.
4. These parts are enabled for Enhanced Intel SpeedStep
®
Technology (EIST).
5. These parts are enabled for Enhanced Halt State (CIE).
6. These parts do not support Thermal Monitor 2 feature.
Table 1. Identification Information
Extended Family
1
Extended Model
2
Type
3
Family
4
Model
5
00000000b 0000b 00b
1111b 0100b
Table 2. 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Identification Information
S-Spec
Core
Stepping
CPUID
Core
Freq
(GHz)
Data Bus
Freq
(MHz)
L3
Cache
Size
Processor
Package
Revision
Package And Revision Notes
SL8EY C-0 00000F41h 3.333 667 8 MB 01 604-pin micro-PGA with
53.3 x 53.3 mm
FC-PGA4 package
1, 2, 3, 4, 5
SL8EW C-0 00000F41h 3.000 667 8 MB 01 604-pin micro-PGA with
53.3 x 53.3 mm
FC-PGA4 package
1, 2, 3, 4, 5
SL8ED C-0 00000F41h 2.830 667 4 MB 01 604-pin micro-PGA with
53.3 x 53.3 mm
FC-PGA4 package
1, 2, 3, 4, 5,
6