64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update

16 64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Summary Table of Changes
S63 XFixedWrites to IA32_MISC_ENABLE may not update flags for both
logical processors
S64 XFixedExecute Disable Bit set with CR4.PAE may cause livelock
S65 XFixedSYSENTER or SYSEXIT instructions may experience
incorrect canonical address checking on processors
supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
S66 XXXXXNo FixChecking of Page Table Base Address may not match
Address Bit Width supported by the platform
S67 XXXXXNo FixIA32_MCi_STATUS MSR may improperly indicate that
additional MCA information may have been captured
S68 XXXXXNo FixWith Trap Flag (TF) asserted, FP instruction that triggers
unmasked FP Exception may take single step trap before
retirement of instruction
S69 XXXXXNo FixPDE/PTE loads and continuous locked updates to the same
cache line may cause system livelock
S70 XFixedMCA-corrected memory hierarchy error counter may not
increment correctly
S71 XXXXXNo FixBranch Trace Store (BTS) and Precise Event-Based
Sampling (PEBS) may update memory outside the
BTS/PEBS buffer
S72 XXX FixedL-bit of CS and LMA bit of IA32_EFER register may have
erroneous value for one instruction following mode transition
in Hyper-Threading Technology-Enabled processor
supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
S73 XXXX FixedThe base of an LDT (Local Descriptor Table) register may be
non-zero on a processor supporting Intel® Extended Memory
64 Technology (Intel® EM64T)
S74 XFixedUnaligned Page-Directory-Pointer (PDPTR) Base with 32-bit
mode PAE (Page Address Extension) paging may cause
processor to hang
S75 XXXXXNo FixMemory ordering failure may occur with snoop filtering
third-party agents after issuing and completing a BWIL (Bus
Write Invalidate Line) or BLW (Bus Locked Write) transaction
S76 XXXXXNo FixControl Register 2 (CR2) can be updated during a REP
MOVS/STOS instruction with fast strings enabled
S77 XXXXXNo FixREP STOS/MOVS instructions with RCX >= 2^32 may cause
system hang
S78 XXXX FixedREP MOVS or REP STOS instruction with RCX >= 2^32 may
fail to execute to completion or may write to incorrect memory
locations on processors supporting Intel® Extended Memory
64 Technology (Intel® EM64T)
S79 XXXXXPlan FixAn REP LODSB or an REP LODSD or an REP LODSQ
instruction with RCX >= 2^32 may cause a system hang on
processors supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
S80 XXXX FixedData access which spans both canonical and non-canonical
address space may hang system
Errata (Sheet 4 of 5)
No.
D-0/
0F34h
E-0/
0F41h
G-1/
0F49h
N-0/
0F43h
R-0/
0F4Ah
Plans Errata