Intel Xeon Processor 2.80 GHz Specification Update

Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update 29
Errata
Status: No Fix
J56. Writing shared unaligned data that crosses a cache line without proper
semaphores or barriers may expose a memory ordering issue.
Problem: Software which is written so that multiple agents can modify the same shared unaligned memory
location at the same time may experience a memory ordering issue if multiple loads access this
shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans
a cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with
any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying shared data by
multiple agents:
• The shared data is aligned.
• Proper semaphores or barriers are used in order to prevent concurrent data accesses.
Status: No Fix
J57. Processor may hang during entry into No-Fill Mode or No-Eviction Mode.
Problem: Only one logical processor per core can be active when processor is put in No-Fill Mode or No-
Eviction Mode. If the other logical processor is active or there is an internal or external event
pending to wake that logical processor, the processor may hang when writing to MSR
IA32_BIOS_CACHE_AS_RAM (80H).
Implication: A processor may hang due to this erratum. Intel has not observed this erratum with any commer-
cially available software or system.
Workaround: None identified.
Status: No Fix
J58. FPU Operand pointer may not be cleared following FINIT/FNINIT.
Problem: Initializing the floating point state with either FINIT or FNINT, may not clear the x87 FPU
Operand (Data) Pointer Offset and the x87 FPU Operand (Data) Pointer Selector (both fields form
the FPUDataPointer). Saving the floating point environment with FSTENV, FNSTENV, or
floating point state with FSAVE, FNSAVE or FXSAVE before an intervening FP instruction may
save uninitialized values for the FPUDataPointer.
Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point image or
floating point environment structure may appear to be random values. Executing any non-control
FP instruction with memory operand will initialize the FPUDataPointer. Intel has not observed this
erratum with any commercially available software.
Workaround: After initialization, do not expect the FPUDataPointer in a floating point state or floating point
environment saved memory image to be correct, until at least one non-control FP instruction with a
memory operand has been executed.
Status: No Fix
D59. The IA32_MC0_STATUS/ IA32_MC1_STATUS overflow bit is not set when
multiple un-correctable machine check errors occur at the same time.
Problem: When two MC0/MC1 enabled un-correctable machine check errors are detected in the same
internal clock cycle, the highest priority error will be logged in IA32_MC0_STATUS /
IA32_MC1_STATUS register, but the overflow bit may not be set.
Implication: The highest priority error will be logged and signaled if enabled, but the overflow bit in the
IA32_MC0_STATUS/ IA32_MC1_STATUS register may not be set.