Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 19
Introduction
Pad The electrical contact point of a semiconductor die to the package substrate. A
pad is only observable in simulations.
Pin The contact point of a component package to the traces on a substrate, such as
the motherboard. Signal quality and timings can be measured at the pin.
Power-Good “Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal)
indicates that all of the system power supplies and clocks are stable.
PWRGOOD should go active a predetermined time after system voltages are
stable and should go inactive as soon as any of these voltages fail their
specifications.
Power Rails A power supply has five power rails: +12 V, –12 V, +5 V, +3.3 V, and +5 VSB. In
addition to these power rails from the power supply, several other power rails are
derived on the motherboard by on-board regulators.
Ringback The voltage to which a signal changes after reaching its maximum absolute
value. Ringback may be caused by reflections, driver oscillations, or other
transmission line phenomena.
System Bus The System Bus is the bus which connects the processor to the platform.
Setup Window The time between the beginning of Setup to Clock (TSU_MIN) and the arrival of
a valid clock edge. This window may be different for each type of bus agent in
the system.
Simultaneous Switching
Output (SSO)
Effects which are differences in electrical timing parameters and degradation in
signal quality caused by multiple signal outputs simultaneously switching voltage
levels in the opposite direction from a single signal or in the same direction.
These are called odd mode and even mode switching, respectively. This
simultaneous switching of multiple outputs creates higher current swings that
may cause additional propagation delay (“push-out”) or a decrease in
propagation delay (“pull-in”). These SSO effects may impact the setup and/or
hold times and are not always taken into account by simulations. System timing
budgets should include margin for SSO effects.
Standby Power Rail Standby power is supplied by the power supply during times when the system is
powered down. The purpose is to maintain functions that always need to be
enabled, such as the date and time-of-day within the BIOS. The power supply
provides a +5 VSB power rail.
Stub The branch from the bus trunk terminating at the pad of an agent.
Trunk The main connection, excluding interconnect branches, from one end agent pad
to the other end agent pad.
Undershoot The minimum voltage extending below VSS observed for a signal at the device
pad.
VCC_CPU VCC_CPU is the core power for the processor. The system bus is terminated to
VCC_CPU.
Victim A network that receives a coupled crosstalk signal from another network is called
the victim network.
Voltage Regulator Down
(VRD)
A VRD refers to a processor voltage regulator which is placed directly onto the
system motherboard.
Voltage Regulator Module
(VRM)
A VRM refers to a processor voltage regulator which is designed on an add-in
card that interfaces with the system design through a connector on the platform.
Intel
®
x4 Single Device
Data Correction (x4 SDDC)
In a x4 DDR memory device, provides error detection and correction for 1, 2, 3 or
4 data bits within that single device and in two x4 DDR memory devices,
provides error detection in up to 8 data bits within those two devices.
Terminology Description