Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Schematic Checklist
242 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
13.5 CK408 Schematic Checklist
For additional information, refer to the CK408 Clock Synthesizer/Driver Specification and your
component’s datasheet.
Table 13-5. CK408 Schematic Checklist
Checklist Items Recommendations Reason/Impact
V3_CLK,
V3_CLKA
• Isolate from the 3.3 V power plane and use
extra decoupling.
• Refer to Section 4.7.
66BUFF[2:0] • Connect to an Intel
®
P64H2 using a series
43
Ω ± 5% resistor.
• Refer to Section 4.2.
66IN • No Connect.
3V66_0 • Connect to Intel
®
ICH3-S using a series
43
Ω ± 5% resistor.
• Refer to Section 4.2.
3V66_1_VCH • Connect to MCH using a series
43
Ω ± 5% resistor.
• Refer to Section 4.2.
CPU[3:0]
CPU[3:0]#
• Connect to the processor, MCH, or ITP
using a series 33
Ω ± 5% resistor, and
terminate to ground through a 49.9
Ω ± 1%
resistor. On the ITP port, use a 10 k
Ω ± 5%
pull-up resistor to V3_CLK close to CK408B.
• Refer to Section 4.1.
DOT_48MHz • No Connect.
IREF • 475
Ω ± 1% pull-down to ground.
MULT0 • 10 k
Ω ± 5% pull-up to V3_CLK.
PCI[4:0] • Connect to a series 33
Ω ± 5% resistor for
PCI33_CLK33, VIDEO_CLK33,
FWH_CLK33, SIO_CLK33, and
LPC_CLK33.
• Refer to Section 4.4.
PCI[6:5] • No Connect.
PCIF[0] • Connect to a series 33
Ω ± 5% resistor for
ICH3_CLK33.
• Refer to Section 4.3.
PCIF[2:1] • No Connect.
PCI_STOP# • 10 k
Ω ± 5% pull-up to V3_CLK.
PWRDWN# • Connect to SLP_S3_N.
REF0 • Connect to a series 22
Ω ± 5% resistor for
CLK 14 output to LPC, VIDEO, SIO, and
ICH3-S.
• Refer to Section 4.5.
S[1] • Connect to Processor 0 BSEL0. • Refer to Section 5.6.3.
SCLK, SDTA • Connect to 3.3 V SMBus partition.
USB_48MHz • Connect to ICH3-S using a 33
Ω ± 5%
series resistor to ICH3 CLK48 pin.
• Refer to Section 4.6.
VDD, VDD_48MHz,
VDDA
• Terminate to V3_CLK_A. • Refer to Section 4.8.
VSS, VSS_48MHz,
VSS_IREF
• Terminate to ground. • Refer to Section 4.8.
VTT_PWRGD# • Do not enable until Processor 0 is driving
valid BSEL.
• Refer to Section 11.2.6.
XTAL_IN
XTAL_OUT
• Terminate to ground.