Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Layout Checklist
248 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
Power / Ground Planes
VRM VO-sen+ /
VO-sen- remote
sense
• If available on the VRM, route the VR’s
differential remote sense input signals to the
middle of the VCC_CPU plane.
• Route the positive feedback line to a point on
the VCC_CPU power plane in the middle of
and equidistant from both processors. Route
the negative feedback line to the
corresponding X-Y location, but on the
VCC_VSS ground plane.
• The traces should be carefully routed to
avoid picking up noise
• They must affect less than 1
Ω round-trip
resistance to minimize the voltage drop
between the sense point and VR input.
• Route each of the feedback lines with less
than 5 inches total trace length. Do not route
near signal lines unless shielding is
provided.
• Refer to Section 11.2.4 for an
example of sense point locations
for the example VRM topology.
• Middle is defined as a point that
provides the shortest geometrical
mid-point between the centers of
the processor sockets.
VRD voltage
feedback
• Route the positive (and negative if the VRD
provides differential inputs) voltage feedback
inputs for the VRD to the VCC_CPU plane
with the following conditions.
• They must be connected to the power plane
through a series resistor. This resistor should
be sized to provide the correct droop to
satisfy the load line requirement.
• They must affect less than 1
Ω round-trip
resistance to minimize the voltage drop
between the sense point and VR input.
• Route the positive feedback line to a point on
the VCC_CPU power plane in the middle of
and equidistant from both processors.
• Route the negative feedback line to the
corresponding X-Y location, but on the
VCC_VSS ground plane.
• Route each of the feedback lines with less
than 5 inches total trace length. Do not route
near signal lines unless shielding is
provided.
• The trace(s) should be carefully routed to
avoid picking up noise.
• Refer to Section 11.2.5 for an
example of sense point locations
for the example VRD topologies.
• Contact your VRD component
vendors for their specific
recommended implementation.
Refer to the applicable CRB
schematics for feedback details
specific to these platforms and
specific VRD solution used. The
recommendations included in this
entry are generic.
• Middle is defined as a point that
provides the shortest geometrical
mid-point between the centers of
the processor sockets.
VCCSENSE /
VSSSENSE
• Do not connect the VRD / VRM inputs to the
processor VCCSENSE / VSSSENSE
signals.
• Refer to Section 11.2.2.
• These processor SENSE signals
are measurement points used for
processor power validation
purposes only.
• Connecting these processor
signals to the VRD/VRM will result
in incorrect VRD/VRM sensing
operation.
Table 14-2. Processor Power Delivery Layout Checklist (Sheet 2 of 4)
Checklist Items Recommendations Comments