Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

System Bus Routing Guidelines

80 Intel

Xeon™ Processor and Intel

E7500/E7501 Chipset Compatible Platform Design Guide

5.5.5 Alternative Method to Obtain PIROM Data

Since the Intel Xeon processor with 533 MHz system bus does not contain a PIROM device,

systems must not rely on these data contents. However, some of the PIROM data field contents

may be obtained by alternative methods using either the CPUID instruction or by reading certain

processor mode-specific registers. Table 5-11 summarizes the information available and the

method for obtaining the data. Contact your Intel representative for more information Refer to the

AP-485 Intel

Processor Identification and CPUID Instruction and your Intel representative for

complete details.

NOTE: This register provides the core frequency-to-system bus ratio. Processor core frequency may be

obtained by multiplying the ratio times the system bus frequency.

5.6 Boot Critical Signals

Processors can only run in certain dual-processor configurations. The following section discusses

which signals dictate certain processor signals, which dictate processor settings, and a sample

circuit.

5.6.1 VID[4:0]

Route the VID[4:0] signals of the processor to the VID[4:0] inputs of the voltage regulator

controller. The voltage regulator controller should provide internal pull-up resistors for these

signals. Refer to the VRM 9.1 DC-DC Converter Design Guidelines and the specification of the

voltage controller specific to your design for further details.

Since both processors must operate at the same voltage, the designer should provide a way to check

the VID[4:0] signals to ensure a processor does not operate out of specification. Refer to

Figure 11-4 for more information.

Table 5-11. Alternative Method to Obtain Processor Information

PIROM Data Field

Alternative Method for

Obtaining Information

Processor Core Data

Processor Core Type CPUID with input 1

Processor Core Model CPUID with input 1

Processor Core Family CPUID with input 1

Processor Core Stepping CPUID with input 1

System Bus Speed MSR_EBC_FREQUENCY_ID

Maximum Core Frequency MSR_EBC_FREQUENCY_ID

Cache Size

L2 Cache Size CPUID with input 2