Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Memory Interface Routing Guidelines

96 Intel

Xeon™ Processor and Intel

E7500/E7501 Chipset Compatible Platform Design Guide

6.7.2 DDR Comp

The MCH uses DDRCOMP_x to calibrate the DDR channel buffers. This is periodically done by

sampling the DDRCOMP pin on the MCH. The E7500 chipset MCH calibrates using a

6.98 Ω ± 1% pull-up to VTERM. The E7501 chipset MCH calibrates using a 24.9 Ω ± 1% pull-

down to ground. This can be implemented by routing a 15-mil wide trace to a resistive network

where the correct pull-up or pull-down is stuffed and the other is not populated, as depicted in

Figure 6-13. Place a decoupling capacitor between the VTERM pull-up and any other terminations.

NOTE: ‘x’ indicates channel A or B.

Table 6-11. DDRCOMP Routing Guidelines

Parameter Intel

E7500 Chipset MCH Intel

E7501 Chipset MCH

Topology pull-up pull-down

Nominal Trace Width 15 mil 15 mil

Nominal Trace Spacing 20 mil 20 mil

Trace Length - MCH to Rtt < 1.0” < 1.0”

Termination Resistor (Rtt) 6.98

Ω ± 1% 24.9 Ω ± 1%

Termination Voltage DDR VTERM Ground

Figure 6-13. DDRCOMP Resistive Compensation

Intel

E7500

chipset MCH

Intel

E7501

chipset MCH

DDR VTERM

(1.25 V)

E7500: 6.98 Ω ± 1%

E7501: no pop

<1"

DDRCOMP_x

E7500: no pop

E7501: 24.9 Ω ± 1%