Intel Xeon Processor LV and ULV Specification Update

Summary Tables of Changes
Specification Update 13
Number
Stepping
Plans
ERRATA
C0
D0
AF23
X
X
No Fix
Disabling of Single-step On Branch Operation May be Delayed
following a POPFD Instruction
AF24
X
X
No Fix
Performance Monitoring Counters that Count External Bus Events May
Report Incorrect Values after Processor Power State Transitions
AF25
X
X
No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
Exception Record (LER) MSR
AF26
X
X
No Fix
General Protection (#GP) Fault May Not Be Signaled On Data Segment
Limit Violation Above 4G Limit
AF27
X
X
No Fix
Performance Monitoring Events for Retired Floating Point Operations
(C1h) May Not be Accurate
AF28
X
X
No Fix
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFH)
AF29
X
X
No Fix
Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not be Flushed by RSM instruction before Restoring the Architectural
State from SMRAM
AF30
X
X
No Fix
Data Breakpoint/Single Step on MOV SS/POP SS May be Lost after
Entry into SMM
AF31
X
X
No Fix
CS Limit Violation on RSM May be Serviced before Higher Priority
Interrupts/Exceptions
AF32
X
No Fix
Hardware Prefetch Performance Monitoring Events May be Counted
Inaccurately
AF33
X
X
No Fix
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
AF34
X
Plan Fix
CPU_CLK_UNHALTED Performance Monitoring Event (3CH) Counts
Clocks when the Processor is in the C1/C2 Processor Power States
AF35
X
X
No Fix
The Processor May Report a #TS Instead of a #GP Fault
AF36
X
X
No Fix
BTS Message May be Lost When the STPCLK# Signal is Active
AF37
X
X
No Fix
Certain Performance Monitoring Counters Related to Bus, L2 Cache
and Power Management are Inaccurate
AF38
X
X
No Fix
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
AF39
X
X
No Fix
IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly
AF40
X
X
Plan Fix
IO_SMI Indication in SMRAM State Save Area May be Lost
AF41
X
X
No Fix
Logical Processors May Not Detect Write-Back (WB) Memory Writes
AF42
X
X
No Fix
Last Exception Record (LER) MSRs May be Incorrectly Updated
AF43
X
X
No Fix
At a 7:1 Core Frequency to Bus Clock Ratio, the Processor May
Livelock when Sending an EOI to MSI Interrupt
AF44
X
X
No Fix
SYSENTER/SYSEXIT Instructions Can Implicitly Load ―Null Segment
Selector‖ to SS and CS Registers