Intel Xeon Processor LV and ULV Specification Update

Summary Tables of Changes
14 Specification Update
Number
Stepping
Plans
ERRATA
C0
D0
AF45
X
X
No Fix
Simultaneous Access to the Same Page Table Entries by both Cores
May Lead to Unexpected Processor Behavior
AF46
X
X
No Fix
Writing the Local Vector Table (LVT) when an Interrupt is Pending May
Cause an Unexpected Interrupt
AF47
X
X
No Fix
Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
Address Translations
AF48
X
X
No Fix
Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and
IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Architectural
Performance Monitoring) Specification
AF49
X
X
No Fix
Premature Execution of a Load Operation Prior to Exception Handler
Invocation
AF50
X
X
No Fix
Performance Monitoring Events for Retired Instructions (C0H) May Not
Be Accurate
AF51
X
X
No Fix
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE[34] When
Execute Disable Bit is Not Supported
AF52
X
X
No Fix
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
AF53
X
X
No Fix
SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC)
Event May Cause Unexpected Behavior
AF54
X
X
No Fix
Shutdown Condition May Disable Non-Bootstrap Processors
AF55
X
X
No Fix
Split Locked Stores May not Trigger the Monitoring Hardware
AF56
X
X
No Fix
Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
AF57
X
X
No Fix
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
AF58
X
X
No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
AF59
X
X
No Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image
Leads to Partial Memory Update
AF60
X
X
No Fix
Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AF61
X
X
No Fix
Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
AF62
Errata – Removed
AF63
X
X
No Fix
EFLAGS Discrepancy on Page Faults after a Translation Change
AF64
X
X
No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
AF65
X
X
No Fix
Performance Monitoring Event FP_ASSIST May Not be Accurate
AF66
X
X
No Fix
The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception