Intel Xeon Processor LV and ULV Specification Update

Errata
Specification Update 21
AF10. Invalid Entries in Page-Directory-Pointer-Table Register (PDPTR) May
Cause General Protection (#GP) Exception If the Reserved Bits Are
Set to One
Problem: Invalid entries in the Page-Directory-Pointer-Table Register (PDPTR) that have the
reserved bits set to one may cause a General Protection (#GP) exception.
Implication: Intel has not observed this erratum with any commercially available software.
Workaround: Do not set the reserved bits to one when PDPTR entries are invalid.
Status: For the steppings affected, see the Summary Tables of Changes.
AF11. VMCALL When Executed during VMX Root Operation while CPL > 0
May Not Generate #GP Fault
Problem: If VMCALL is executed during VMX root operation with CPL > 0, the expected behavior
is for the processor to generate a General Protection Fault (#GP). Due to this
erratum, the #GP fault may not be generated.
Implication: VM Monitor code running with CPL > 0 may not generate #GP fault on VMCALL, but
still will behave as if VM Exit had occurred.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF12. FP Inexact-Result Exception Flag May Not be Set Title Case
Problem: When the result of a floating-point operation is not exactly representable in the
destination format (1/3 in binary form, for example), an inexact-result (precision)
exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is
normally set by the processor. Under certain rare conditions, this bit may not be set
when this rounding occurs. However, other actions taken by the processor (invoking
the software exception handler if the exception is unmasked) are not affected. This
erratum can only occur if the floating-point operation which causes the precision
exception is immediately followed by one of the following instructions:
• FST m32real
• FST m64real
• FSTP m32real
• FSTP m64real
• FSTP m80real
• FIST m16int
• FIST m32int
• FISTP m16in
• FISTP m32int
• FISTP m64int
Note that even if this combination of instructions is encountered, there is also a
dependency on the internal pipelining and execution state of both instructions in the
processor.
Implication: Inexact-result exceptions are commonly masked or ignored by applications, as it
happens frequently, and produces a rounded result acceptable to most applications.