Intel Xeon Processor LV and ULV Specification Update

Errata
22 Specification Update
The PE bit of the FPU status word may not always be set upon receiving an inexact-
result exception. Thus, if these exceptions are unmasked, a floating-point error
exception handler may not recognize that a precision exception occurred. Note that
this is a ―sticky‖ bit, i.e., once set by an inexact-result condition, it remains set until
cleared by software.
Workaround: This condition can be avoided by inserting two non-floating-point instructions between
the two floating-point instructions.
Status: For the steppings affected, see the Summary Tables of Changes.
AF13. A Locked Data Access that Spans Across Two Pages May Cause the
System to Hang
Problem: An instruction with lock data access that spans across two pages may, given some
rare internal conditions, hang the system
Implication: When this erratum occurs, the system may hang. Intel has not observed this erratum
with any commercially available software or system.
Workaround: A locked data access should always be aligned.
Status: For the steppings affected, see the Summary Tables of Changes.
AF14. MOV To/From Debug Registers Causes Debug Exception
Problem: When in V86 mode, if a MOV instruction is executed to/from a debug register, a
general-protection exception (#GP) should be generated. However, in the case when
the general detect enable flag (GD) bit is set, the observed behavior is that a debug
exception (#DB) is generated instead.
Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to
execute a MOV on debug registers in V86 mode, a debug exception will be generated
instead of the expected general-protection fault.
Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The
GD bit is generally set and used by debuggers. The debug exception handler should
check that the exception did not occur in V86 mode before continuing. If the exception
did occur in V86 mode, the exception may be directed to the general-protection
exception handler.
Status: For the steppings affected, see the Summary Tables of Changes.
AF15. INIT Does Not Clear Global Entries in the TLB
Problem: Problem: INIT may not flush a TLB entry when:
1. The processor is in protected mode with paging enabled and the page global
enable flag is set (PGE bit of CR4 register)
2. G bit for the page table entry is set
3. TLB entry is present in TLB when INIT occurs
Implication: Software may encounter unexpected page fault or incorrect address translation due to
a TLB entry erroneously left in TLB after INIT.