Intel Xeon Processor LV and ULV Specification Update

Errata
Specification Update 23
Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE)
registers before writing to memory early in BIOS code to clear all the global entries
from TLB.
Status: For the steppings affected, see the Summary Tables of Changes.
AF16. Use of Memory Aliasing with Inconsistent Memory Type May Cause
System Hang or a Machine Check Exception
Problem: Software that implements memory aliasing by having more than one linear addresses
mapped to the same physical page with different cache types may cause the system
to hang or to report a machine check exception (MCE). This would occur if one of the
addresses is non-cacheable used in code segment and the other a cacheable address.
If the cacheable address finds its way in instruction cache, and non-cacheable address
is fetched in IFU, the processor may invalidate the non-cacheable address from the
fetch unit. Any micro-architectural event that causes instruction restart will expect this
instruction to still be in fetch unit and lack of it will cause a system hang or an MCE.
Implication: This erratum has not been observed with commercially available software.
Workaround: Although it is possible to have a single physical page mapped by two different linear
addresses with different memory types, Intel has strongly discouraged this practice as
it may lead to undefined results. Software that needs to implement memory aliasing
should manage the memory type consistency.
Status: For the steppings affected, see the Summary Tables of Changes.
AF17. Machine Check Exception May Occur When Interleaving Code between
Different Memory Types
Problem: A small window of opportunity exists where code fetches interleaved between different
memory types may cause a machine check exception. A complex set of micro-
architectural boundary conditions is required to expose this window.
Implication: Interleaved instruction fetches between different memory types may result in a
machine check exception. The system may hang if machine check exceptions are
disabled. Intel has not observed the occurrence of this erratum while running
commercially available applications or operating systems.
Workaround: Software can avoid this erratum by placing a serializing instruction between code
fetches between different memory types.
Status: For the steppings affected, see the Summary Tables of Changes.
AF18. Data Prefetch Performance Monitoring Events Can Only be Enabled on
a Single Core
Problem: Current implementation of Data Prefetch performance monitoring events allow
counting only for a single core at a time.
Implication: Dual-core support for counting Data Prefetch performance monitoring events is not
currently available.