Intel Xeon Processor LV and ULV Specification Update

Errata
24 Specification Update
Workaround: Software should enable Data Prefetch performance monitoring events on one core at a
time.
Status: For the steppings affected, see the Summary Tables of Changes.
AF19. LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly De-assert
Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is
received during a snoop phase and the Locked transaction is pipelined on the front
side bus (FSB), LOCK# may unexpectedly de-assert.
Implication: When this erratum occurs, the system may hang during shutdown. Intel has not
observed this erratum with any commercially available systems or software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF20. Disable Execution-Disable Bit (IA32_MISC_ENABLES [34]) Is Shared
between Cores
Problem: The bit 34 of the IA32_MISC_ENABLES Model Specific Register (MSR) is shared
between the execution cores.
Implication: Both cores will operate according to the shared value of bit IA32_MISC_ENABLES
[34].
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF21. Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
Problem: A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value to
the LBR_TO value.
Implication: The LBR_FROM will have the incorrect address of the Branch Instruction.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF22. Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May be Incorrect
Problem: When correctable single-bit ECC errors occur in the L2 cache the address is logged in
the MCA address register (MCi_ADDR). Under some scenarios, the address reported
may be incorrect.
Implication: Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC
errors