Intel Xeon Processor LV and ULV Specification Update

Errata
26 Specification Update
Workaround: Software exception handlers that rely on the LER MSR value should read the LER MSR
before executing VERW/VERR/LSL/LAR instructions.
Status: For the steppings affected, see the Summary Tables of Changes.
AF26. General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
Problem: Memory accesses to flat data segments (base = 00000000h) that occur above the 4G
limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur, the system may not issue a #GP fault.
Workaround: Software should ensure that memory accesses do not occur above the 4G limit
(0ffffffffh).
Status: For the steppings affected, see the Summary Tables of Changes.
AF27. Performance Monitoring Events for Retired Floating Point Operations
(C1h) May Not Be Accurate
Problem: Performance monitoring events that count retired floating point operations may be too
high.
Implication: The Performance Monitoring Event may have an inaccurate count.
Workaround: Software should ensure that memory accesses do not occur above the 4G limit
(0ffffffffh).
Status: For the steppings affected, see the Summary Tables of Changes.
AF28. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFH)
Problem: The Resume from System Management Mode (RSM) instruction does not flush global
pages from the Data Translation Look-Aside Buffer (DTLB) prior to reloading the saved
architectural state.
Implication: The value observed for performance monitoring count for saturating SIMD instructions
retired may be too high. The size of the error is dependent on the number of
occurrences of the conditions described above, while the counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF29. Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not be Flushed by RSM instruction before Restoring the Architectural
State from SMRAMTitle Case