Intel Xeon Processor LV and ULV Specification Update

Errata
28 Specification Update
AF32. Hardware Prefetch Performance Monitoring Events May Be Counted
Inaccurately
Problem: Hardware prefetch activity is not accurately reflected in the hardware prefetch
performance monitoring.
Implication: This erratum may cause inaccurate counting for all hardware prefetch performance
monitoring events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF33. Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
before Higher Priority Interrupts
Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag)
instruction are normally serviced immediately after the instruction following the STI.
An exception to this is if the following instruction triggers a #MF. In this situation, the
interrupt should be serviced before the #MF. Because of this erratum, if following STI,
an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel
SpeedStep® Technology transitions or Thermal Monitor 1 events occur, the pending
#MF may be serviced before higher priority interrupts.
Implication: Software may observe #MF being serviced before higher priority interrupts
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF34. CPU_CLK_UNHALTED Performance Monitoring Event (3CH) Counts
Clocks when the Processor is in the C1/C2 Processor Power States
Problem: The CPU_CLK_UNHALTED performance monitoring event should only count clocks
when the processor is running. However, due to this erratum, CPU_CLK_UNHALTED
performance monitoring event may count clocks when the cores have been halted in
the C1/C2 processor power states. The count may be incorrect when the two cores
are not in C1/C2 state simultaneously.
Implication: The CPU_CLK_UNHALTED performance monitoring event may read a somewhat larger
value than expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF35. The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.