Intel Xeon Processor LV and ULV Specification Update

Errata
Specification Update 29
Status: For the steppings affected, see the Summary Tables of Changes.
AF36. BTS Message May Be Lost When the STPCLK# Signal is Active
Problem: STPCLK# is asserted to enable the processor to enter a low-power state. Under some
circumstances, when STPCLK# becomes active, a pending BTS (Branch Trace Store)
message may be either lost and not written or written with corrupted branch address
to the Debug Store area.
Implication: BTS messages may be lost in the presence of STPCLK# assertions.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF37. Certain Performance Monitoring Counters Related to Bus, L2 Cache
and Power Management are Inaccurate
Problem: All Performance Monitoring Counters in the ranges 21H-3DH and 60H-7FH may have
inaccurate results up to +/- 7.
Implication: There may be a small error in the affected counts.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF38. A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
Problem: With respect to the retirement of instructions, stores to the uncacheable memory-
based APIC register space are handled in a non-synchronized way. For example if an
instruction that masks the interrupt flag, e.g. CLI, is executed soon after an
uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the
interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR, but
higher than the final TPR, to not be serviced until the interrupt enabled flag is finally
set, i.e. by STI instruction. Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay their
service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read after the
APIC register write. This will force the store to the APIC register before any
subsequent instructions are executed. No commercial operating system is known to be
impacted by this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AF39. IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
Problem: The IO_SMI bit in SMRAM‘s location 7FA4H is set to "1" by the CPU to indicate a
System Management Interrupt (SMI) occurred as the result of executing an instruction
that reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly