Intel Xeon Processor LV and ULV Specification Update

Errata

30 Specification Update

set by:

• A non-I/O instruction

• SMI is pending while a lower priority event interrupts

• A REP I/O read

• An I/O read that redirects to MWAIT

• In systems supporting Intel® Virtualization Technology a fault in the middle of an

IO operation that causes a VM Exit

Implication: SMM handlers may get false IO_SMI indication.

Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was

triggered by an instruction that read from an I/O port. The SMM handler must not

restart an I/O instruction if the platform has not been configured to generate a

synchronous SMI for the recorded I/O port address.

Status: For the steppings affected, see the Summary Tables of Changes.

AF40. IO_SMI Indication in SMRAM State Save Area May Be Lost

Problem: The IO_SMI bit in SMRAM‘s location 7FA4H is set to "1" by the CPU to indicate a

System Management Interrupt (SMI) that occurred as the result of executing an

instruction that read from an I/O port. Due to this erratum, the setting of the IO_SMI

bit may be lost. This may happen if following the instruction that read from an I/O

port, there is an instruction with a memory operand that results in one of the

following:

• Update of a Page Table Entry (PTE) Accessed (A) or Dirty (D) bits.

• Page Fault (#PF)

• A REP I/O read

• Unaligned Memory access where either address of the first or last byte of the

access (ex: (Address1stByte AND NOT 0x3F) OR (AddressLastByte AND NOT 0x3F) ) is

equal to the address in one of the Debug Address Registers (DR0-DR3) (ex. DRx AND

NOT 0x3F ) as long as any address breakpoint is enabled through the Debug Control

Implication: SMI handlers may not be able to identify the occurrence of I/O SMIs.

Workaround: It is possible for BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

AF41. Logical Processors May Not Detect Write-Back (WB) Memory Writes

Problem: Multiprocessor systems may use polling of memory semaphores to synchronize

software activity. Because of this erratum, if a logical processor is polling a WB

memory location while it is being updated by another logical processor, the update

may not be detected.

Implication: System may livelock due to polling loop and undetected semaphore change. Intel has

not observed this erratum on commercially available systems.

Workaround: It is possible for BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.