Intel Xeon Processor LV and ULV Specification Update

Errata
32 Specification Update
Status: For the steppings affected, see the Summary Tables of Changes.
AF45. Simultaneous Access to the Same Page Translation Entries by Both
Cores May Lead to Unexpected Processor Behavior
Problem: When the following conditions occur simultaneously, this may create a rare internal
condition which may lead to unexpected processor behavior.
• One core is updating a page table entry, including the processor setting the
Accessed and/or Dirty bits in the PTE as the result of an access
• The other core is using the same translation entry
Implication: Unpredictable behavior in the processor may lead to livelock and shutdown. Intel has
not observed this erratum with any commercially available software.
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes.
AF46. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no Interrupt
Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does
not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service
register and mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear
any unexpected interrupts that may occur. The ISR associated with the spurious
vector does not generate an EOI, therefore the spurious vector should not be used
when writing the LVT.
Status: For the steppings affected, see the Summary Tables of Changes.
AF47. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
Address Translations
Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero)
to emulates real-address mode address wraparound at 1 megabyte. However, if all of
the following conditions are met, address bit 20 may not be masked.
• paging is enabled
• a linear address has bit 20 set
• the address references a large page
• A20M# is enabled
Implication: When A20M# is enabled and an address references a large page the resulting
translated physical address may be incorrect. This erratum has not been observed
with any commercially available operating system.