Intel Xeon Processor LV and ULV Specification Update

Errata
34 Specification Update
Status: For the steppings affected, see the Summary Tables of Changes.
AF50. Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
Problem: The INST_RETIRED performance monitor may miscount retired instructions as follows:
• Repeat string and repeat I/O operations are not counted when a hardware interrupt
is received during or after the last iteration of the repeat flow.
• VMLAUNCH and VMRESUME instructions are not counted.
• HLT and MWAIT instructions are not counted. The following instructions, if
executed during HLT or MWAIT events, are also not counted:
a) RSM from a C-state SMI during an MWAIT instruction.
b) RSM from an SMI during a HLT instruction.
Implication: There may be a smaller than expected value in the INST_RETIRED performance
monitoring counter. The extent to which this value is smaller than expected is
determined by the frequency of the above cases.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF51. #GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable Bit is Not Supported
Problem: A #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a processor
which does not support Execute Disable Bit functionality.
Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF52. Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
Problem: Updating a page table entry by changing R/W, U/S or P bits without TLB shootdown
(as defined by the 4 step procedure in "Propagation of Page Table and Page Directory
Entry Changes to Multiple Processors" In volume 3A of the IA-32 Intel® Architecture
Software Developer's Manual), in conjunction with a complex sequence of internal
processor micro-architectural events, may lead to unexpected processor behavior
Implication: This erratum may lead to livelock, shutdown or other unexpected processor behavior.
Intel has not observed this erratum on any commercially available systems.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.