Intel Xeon Processor LV and ULV Specification Update

Errata
36 Specification Update
Problem: Software which is written so that multiple agents can modify the same shared
unaligned memory location at the same time may experience a memory ordering
issue if multiple loads access this shared data shortly thereafter. Exposure to this
problem requires the use of a data write which spans a cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not observed this
erratum with any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying shared
data by multiple agents:
- The shared data is aligned
- Proper semaphores or barriers are used in order to prevent concurrent data
accesses
Status: For the steppings affected, see the Summary Tables of Changes.
AF57. MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after Machine Check Exception (MCE)
Problem: When an MCE occurs during execution of a RDMSR instruction for MSRs Actual
Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock Count
(IA32_MPERF), the current and subsequent RDMSR instructions for these MSRs may
contain incorrect data
Implication: After an MCE event, accesses to the IA32_APERF and IA32_MPERF MSRs may return
incorrect data. A subsequent reset will clear this condition.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF58. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints
until after execution of the following instruction. This is intended to allow the
sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without
having an invalid stack during interrupt handling. However, an enabled debug
breakpoint or single step trap may be taken after MOV SS/POP SS if this instruction is
followed by an instruction that signals a floating point exception rather than a MOV
[r/e]SP, [r/e]BP instruction. This results in a debug exception being signaled on an
unexpected instruction boundary since the MOV SS/POP SS and the following
instruction should be executed atomically.
Implication: This can result in incorrect signaling of a debug exception and possibly a mismatched
Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV
[r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any
exception. Intel has not observed this erratum with any commercially available
software, or system.
Workaround: As recommended in the IA32 Intel® Architecture Software Developer‘s Manual, the
use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure