Intel Xeon Processor LV and ULV Specification Update

Errata
Specification Update 41
transferring to ring 0. Intel has not observed this erratum on any commercially
available software.
Workaround: Software that conforms to the Intel
®
64 and IA-32 Architectures Software Developer's
Manual, Volume 3A, section ―Buffering of Write Combining Memory Locations‖ will
operate correctly.
Status: For the steppings affected, see the Summary Tables of Changes.
AF73. Unaligned Accesses to Paging Structures may Cause the Processor to
Hang
Problem: When an unaligned access is performed on paging structure entries, accessing a
portion of two different entries simultaneously, the processor may live lock.
Implication: When this erratum occurs, the processor may live lock causing a system hang.
Workaround: Do not perform unaligned accesses on paging structure entries.
Status: For the steppings affected, see the Summary Tables of Changes.
AF74. Microcode Updates Performed During VMX Non-root Operation Could
Result in Unexpected Behavior
Problem: When Intel
®
Virtualization Technology is enabled, microcode updates are allowed only
during VMX root operations. Attempts to apply microcode updates while in VMX non-
root operation should be silently ignored. Due to this erratum, the processor may
allow microcode updates during VMX non-root operations if not explicitly prevented by
the host software.
Implication: Microcode updates performed in non-root operation may result in unexpected system
behavior.
Workaround: Host software should intercept and prevent loads to IA32_BIOS_UPDT_TRIG MSR
(79H) during VMX non-root operations. There are two mechanism that can be used (1)
Enabling MSR access protection in the VM-execution controls or (2) Enabling selective
MSR protection of IA32_BIOS_UPDT_TRIG MSR.
Status: For the steppings affected, see the Summary Tables of Changes.
AF76. AF76. Page Access Bit May be Set Prior to Signaling a Code Segment
Limit Fault
Problem: If code segment limit is set close to the end of a code page, then due to this erratum
the memory page Access bit (A bit) may be set for the subsequent page prior to
general protection fault on code segment limit.
Implication: When this erratum occurs, a non-accessed page which is present in memory and
follows a page that contains the code segment limit may be tagged as accessed.
Workaround: Erratum can be avoided by placing a guard page (non-present or non-executable
page) as the last page of the segment or after the page that includes the code
segment limit.