Intel Xeon Processor Specification Update

Intel
®
Xeon
®
Processor Specification Update 49
Errata
Implication: Due to this erratum, the system may livelock until some external event interrupts the locked
update. Intel has not observed this erratum with any commercially available software.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
P79 Branch Trace Store (BTS) and Precise Event Based Sampling (PEBS) may
update memory outside the BTS/PREBS buffer
Problem: If the BTS/PREBS buffer is defined such that:
• The difference between BTS/PREBS buffer base and BTS/PREBS absolute maximum is not
an integer multiple of the corresponding record sizes.
• BTS/PREBS absolute maximum is less than a record size from the end of the virtual address
space.
• The record that would cross BTS/PREBS absolute maximum will also continue past the end of
the virtual address space.
A BTS/PREBS record can be written that will wrap at the 4G boundary (IA-32) or 2^64 boundary
(Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) mode), and write memory outside of the
BTS/PREBS buffer.
Implication: Software that uses BTS/PREBS near the 4G boundary (IA-32) or 2^64 boundary (Intel EM64T
mode), and defines the buffer such that it does not hold an integer multiple of records can update
memory outside the BTS/PREBS buffer.
Workaround: Define BTS/PREBS buffer such that BTS/PREBS absolute maximum minus BTS/PREBS buffer
base is integer multiple of the corresponding record sizes as recommended in the IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 3.
Status: For the steppings affected, see the Summary Table of Changes.
P80 Memory Ordering Failure may occur with Snoop Filtering Third-Party
Agents after Issuing and completing a BWIL (Bus Write Invalidate Line) or
BLW (Bus Locked Write) transaction
Problem: Under limited circumstances, the processors may, after issuing and completing a BWIL or BLW
transaction, retain data from the addressed cache line in shared state even though the specification
requires complete invalidation. This data retention may also occur when a BWIL transaction’s
self-snooping yields HITM snoop results.
Implication: A system may suffer memory ordering failures if its central agent incorporates coherence
sequencing which depends on full self-invalidation of the cache line associated with (1) BWIL and
BLW transactions, or (2) all HITM snoop results without regard to the transaction type and snoop
results’ source.
Workaround:
1. The central agent can issue a bus cycle that causes a cache line to be invalidated (Bus Read
Invalidate Line (BRIL) or BWIL transaction) in response to a processor-generated BWIL (or
BLW) transaction to insure complete invalidation of the associated cache line. If there are no
intervening processor-originated transactions to that cache line, the central agent’s invalidating
snoop will get a clean snoop result.
Or
2. Snoop filtering central agents can:
a. Not use processor-originated BWIL or BLW transactions to update their snoop filter
information, or