ITP700 Debug Port Design Guide

R
100 ITP700 Debug Port Design Guide
Receive Pins:
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* BCK
* BCLK(pn), LOAD MODEL LEVEL 1
* CREATED: NOVEMBER 22, 1999
* EXPANDED DOCUMENTATION: AUGUST 18, 2000
*
* PINS:
* M2=MINITEK* BCKP CONN AT TARGET
* M4=MINITEK* BCKN CONN AT TARGET
* ECLP=BCKP ECL INPUT
* ECLN=BCKN ECL INPUT
*
* ADDITIONAL REQUIRED SUBCIRCUITS INCLUDED IN PACKAGES.TXT:
* QSOP = QSOP PIN MODEL, PACKAGE APPROXIMATION
* MINITEK* = ITP DPA HEADER MODEL
*
* ADDITIONAL MODELS THAT MAY BE ADDED:
* mc100lvel17 = MOTOROLA ECL RECEIVER
* qs3vh125 = QUALITY SEMICONDUCTOR* QUICKSWITCH
*
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*
.SUBCKT BCK M2 M4 ECLP ECLN GNDREF
* Voltages supplied by the DPA
VINIT1 VEE GNDREF -1.2
VINIT2 VCC GNDREF 2.1
*