ITP700 Debug Port Design Guide

16 ITP700 Debug Port Design Guide

1.3.3 Execution Signal Layout Guidelines

Table 4. Execution Signal Layout Guidelines

Debug Port Signal Layout Guideline

BPM[5:0]# These signals are extremely routing critical. The debug port recovers these

signals relative to BCLK at the debug port pins. Therefore, the signals

must be routed with closely matched electrical lengths (within ±50 ps) and

no greater than 1.0 ns from the processor to the debug port.

BPM5DR# The debug port BPM5DR# output pin should be connected on the board to

the BPM5# pin of the debug port. This allows the ITP or run-control tool to

drive BPM5# at reset. It also allows ITP to assert BPM5# if ITP needs to

assert a trigger signal that can be seen directly by the target system. Note

that ITP asserts / de-asserts this signal asynchronous to the bus BCLK.

The debug port should be placed as close as is physically reasonable to the processor and no

further than 1.0 ns flight time (as measured by trace length of the BPM[5:0]# signals) from the

processor. System designers should record the flight time of the BPM[5:0]# signals from the

processor to the debug port. This value will be important during the routing of several other debug

port signals. Ideally BPM[5]# will be routed from the processor to the debug port BPM[5]# pin

matched with the other BPM# signals. From pin 13 the trace will route directly to the debug port

BPM5DR# pin and continue to the termination of the transmission line.

Assuming BCLK(p/n) signals are routed from the system clock buffer to each of the synchronous

clock agents with a matched length, the copy of BCLK(p/n) from the system clock buffer to the

ITP debug port must have a flight time equal to the matched length of the other synchronous clock

agents plus the flight time of the BPM[5:0]# signals from the processor to the debug port noted

above. This will ensure that the same BCLK to BPM[5:0]# phase relationship seen at the

processor will be present at the debug port pins. BCLK trace lengths may be adjusted to center the

recovery of BPM[5:0]# and RESET# at the debug port within the ITP receiver setup and hold

window.

Multiple layer transitions of the BCLK, BPM, and TCK signals will compromise signal integrity.

An effort should be made to minimize the number of layer transitions for these signals. Try to keep

the BCLK, BPM, and TCK signals referenced to GND whenever possible. If layer transitions are

required, stitching vias should be included near ever every layer transition of the BCLK, BPM,

and TCK signals, even when not referencing the same voltage. This is recommended to reduce the

lengths of return current loops. Adding an AC bypass capacitor near every layer transition or plane

split between the two referenced planes will also help to minimize AC return current loops. An

effort should be made to not share ITP AC bypass capacitors with other high-speed signals.

TCK and TMS must be routed with pull-up / pull-downs located at the driver. FBO is routed such

that it is connected to the TCK at the processor, and routed back to the debug port with an

electrical length equal to the flight time of the BPM[5:0]# and RESET# signals from the processor

to the debug port. This is done to guarantee that the BCLK to TCK phase relationship at the

processor will be seen at the debug port FBO and BCLK(p/n) pins. The diagram below illustrates

these routing relationships.