ITP700 Debug Port Design Guide

ITP700 Debug Port Design Guide 57

6 Intel

Xeon

™

Processor with 512-

KB L2 Cache at 2.20, 2.0, and 1.80

GHz DP / Intel

Xeon™ Processor

MP Server System Implementation

Guidelines

6.1 Termination and Routing Guidelines

The following specifications are for an ITP700 implementation that is terminated according to the

content in the Multi-processor ITP debug port Implementation Guidelines chapter of this

document adjusted for Intel

Xeon™ processor specific implementation guidelines dictated in

section 4.3 of this document. If the system design does not conform to the required terminations

exactly, the additional drive specifications listed in the ITP700 DPA Specifications chapter of this

document can be used to interpolate specifications at the non-standard operating ranges

All of the termination and routing guidelines defined in Chapter 2 must be adhered to for a multi-

processor ITP700 debug port implementation with the following exceptions and clarifications:

Figure 16. BPM[5:0]# Connectivity for Intel

Xeon™ Processor with 512-KB L2 Cache at 2.20,

2.0, and 1.80 GHz DP / Intel

Xeon™ Processor MP Servers

ebug Port

Connector

BPM[0]# Signal

BPM[1]# Signal

BPM[2]# Signal

BPM[3]# Signal

BPM[4]# Signal

BPM[5]# Signal

Rt Rt

Vcc

BPM#

0 1 2 3 4 5

Chipset

Rt Rt

Vcc

BPM#

0 1 2 3 4 5

uProcessor

BPM